1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
31 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 #define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131 #define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 #define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
140 union cvmx_npei_bar1_indexx
{
142 struct cvmx_npei_bar1_indexx_s
{
143 #ifdef __BIG_ENDIAN_BITFIELD
144 uint32_t reserved_18_31
:14;
145 uint32_t addr_idx
:14;
153 uint32_t addr_idx
:14;
154 uint32_t reserved_18_31
:14;
159 union cvmx_npei_bist_status
{
161 struct cvmx_npei_bist_status_s
{
162 #ifdef __BIG_ENDIAN_BITFIELD
164 uint64_t reserved_60_62
:3;
172 uint64_t reserved_50_52
:3;
175 uint64_t reserved_36_47
:12;
180 uint64_t reserved_31_31
:1;
209 uint64_t reserved_2_2
:1;
215 uint64_t reserved_2_2
:1;
244 uint64_t reserved_31_31
:1;
249 uint64_t reserved_36_47
:12;
252 uint64_t reserved_50_52
:3;
260 uint64_t reserved_60_62
:3;
264 struct cvmx_npei_bist_status_cn52xx
{
265 #ifdef __BIG_ENDIAN_BITFIELD
267 uint64_t reserved_60_62
:3;
278 uint64_t reserved_48_49
:2;
287 uint64_t reserved_36_39
:4;
361 uint64_t reserved_36_39
:4;
370 uint64_t reserved_48_49
:2;
381 uint64_t reserved_60_62
:3;
385 struct cvmx_npei_bist_status_cn52xxp1
{
386 #ifdef __BIG_ENDIAN_BITFIELD
387 uint64_t reserved_46_63
:18;
481 uint64_t reserved_46_63
:18;
484 struct cvmx_npei_bist_status_cn56xxp1
{
485 #ifdef __BIG_ENDIAN_BITFIELD
486 uint64_t reserved_58_63
:6;
604 uint64_t reserved_58_63
:6;
609 union cvmx_npei_bist_status2
{
611 struct cvmx_npei_bist_status2_s
{
612 #ifdef __BIG_ENDIAN_BITFIELD
613 uint64_t reserved_14_63
:50;
643 uint64_t reserved_14_63
:50;
648 union cvmx_npei_ctl_port0
{
650 struct cvmx_npei_ctl_port0_s
{
651 #ifdef __BIG_ENDIAN_BITFIELD
652 uint64_t reserved_21_63
:43;
653 uint64_t waitl_com
:1;
663 uint64_t reserved_6_6
:1;
675 uint64_t reserved_6_6
:1;
685 uint64_t waitl_com
:1;
686 uint64_t reserved_21_63
:43;
691 union cvmx_npei_ctl_port1
{
693 struct cvmx_npei_ctl_port1_s
{
694 #ifdef __BIG_ENDIAN_BITFIELD
695 uint64_t reserved_21_63
:43;
696 uint64_t waitl_com
:1;
706 uint64_t reserved_6_6
:1;
718 uint64_t reserved_6_6
:1;
728 uint64_t waitl_com
:1;
729 uint64_t reserved_21_63
:43;
734 union cvmx_npei_ctl_status
{
736 struct cvmx_npei_ctl_status_s
{
737 #ifdef __BIG_ENDIAN_BITFIELD
738 uint64_t reserved_44_63
:20;
741 uint64_t cfg_rtry
:16;
746 uint64_t host_mode
:1;
750 uint64_t host_mode
:1;
755 uint64_t cfg_rtry
:16;
758 uint64_t reserved_44_63
:20;
761 struct cvmx_npei_ctl_status_cn52xxp1
{
762 #ifdef __BIG_ENDIAN_BITFIELD
763 uint64_t reserved_44_63
:20;
766 uint64_t cfg_rtry
:16;
767 uint64_t reserved_15_15
:1;
770 uint64_t reserved_9_12
:4;
771 uint64_t host_mode
:1;
775 uint64_t host_mode
:1;
776 uint64_t reserved_9_12
:4;
779 uint64_t reserved_15_15
:1;
780 uint64_t cfg_rtry
:16;
783 uint64_t reserved_44_63
:20;
786 struct cvmx_npei_ctl_status_cn56xxp1
{
787 #ifdef __BIG_ENDIAN_BITFIELD
788 uint64_t reserved_15_63
:49;
792 uint64_t host_mode
:1;
796 uint64_t host_mode
:1;
800 uint64_t reserved_15_63
:49;
805 union cvmx_npei_ctl_status2
{
807 struct cvmx_npei_ctl_status2_s
{
808 #ifdef __BIG_ENDIAN_BITFIELD
809 uint64_t reserved_16_63
:48;
831 uint64_t reserved_16_63
:48;
836 union cvmx_npei_data_out_cnt
{
838 struct cvmx_npei_data_out_cnt_s
{
839 #ifdef __BIG_ENDIAN_BITFIELD
840 uint64_t reserved_44_63
:20;
850 uint64_t reserved_44_63
:20;
855 union cvmx_npei_dbg_data
{
857 struct cvmx_npei_dbg_data_s
{
858 #ifdef __BIG_ENDIAN_BITFIELD
859 uint64_t reserved_28_63
:36;
860 uint64_t qlm0_rev_lanes
:1;
861 uint64_t reserved_25_26
:2;
871 uint64_t reserved_25_26
:2;
872 uint64_t qlm0_rev_lanes
:1;
873 uint64_t reserved_28_63
:36;
876 struct cvmx_npei_dbg_data_cn52xx
{
877 #ifdef __BIG_ENDIAN_BITFIELD
878 uint64_t reserved_29_63
:35;
879 uint64_t qlm0_link_width
:1;
880 uint64_t qlm0_rev_lanes
:1;
881 uint64_t qlm1_mode
:2;
891 uint64_t qlm1_mode
:2;
892 uint64_t qlm0_rev_lanes
:1;
893 uint64_t qlm0_link_width
:1;
894 uint64_t reserved_29_63
:35;
897 struct cvmx_npei_dbg_data_cn56xx
{
898 #ifdef __BIG_ENDIAN_BITFIELD
899 uint64_t reserved_29_63
:35;
900 uint64_t qlm2_rev_lanes
:1;
901 uint64_t qlm0_rev_lanes
:1;
913 uint64_t qlm0_rev_lanes
:1;
914 uint64_t qlm2_rev_lanes
:1;
915 uint64_t reserved_29_63
:35;
920 union cvmx_npei_dbg_select
{
922 struct cvmx_npei_dbg_select_s
{
923 #ifdef __BIG_ENDIAN_BITFIELD
924 uint64_t reserved_16_63
:48;
928 uint64_t reserved_16_63
:48;
933 union cvmx_npei_dmax_counts
{
935 struct cvmx_npei_dmax_counts_s
{
936 #ifdef __BIG_ENDIAN_BITFIELD
937 uint64_t reserved_39_63
:25;
943 uint64_t reserved_39_63
:25;
948 union cvmx_npei_dmax_dbell
{
950 struct cvmx_npei_dmax_dbell_s
{
951 #ifdef __BIG_ENDIAN_BITFIELD
952 uint32_t reserved_16_31
:16;
956 uint32_t reserved_16_31
:16;
961 union cvmx_npei_dmax_ibuff_saddr
{
963 struct cvmx_npei_dmax_ibuff_saddr_s
{
964 #ifdef __BIG_ENDIAN_BITFIELD
965 uint64_t reserved_37_63
:27;
968 uint64_t reserved_0_6
:7;
970 uint64_t reserved_0_6
:7;
973 uint64_t reserved_37_63
:27;
976 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1
{
977 #ifdef __BIG_ENDIAN_BITFIELD
978 uint64_t reserved_36_63
:28;
980 uint64_t reserved_0_6
:7;
982 uint64_t reserved_0_6
:7;
984 uint64_t reserved_36_63
:28;
989 union cvmx_npei_dmax_naddr
{
991 struct cvmx_npei_dmax_naddr_s
{
992 #ifdef __BIG_ENDIAN_BITFIELD
993 uint64_t reserved_36_63
:28;
997 uint64_t reserved_36_63
:28;
1002 union cvmx_npei_dma0_int_level
{
1004 struct cvmx_npei_dma0_int_level_s
{
1005 #ifdef __BIG_ENDIAN_BITFIELD
1015 union cvmx_npei_dma1_int_level
{
1017 struct cvmx_npei_dma1_int_level_s
{
1018 #ifdef __BIG_ENDIAN_BITFIELD
1028 union cvmx_npei_dma_cnts
{
1030 struct cvmx_npei_dma_cnts_s
{
1031 #ifdef __BIG_ENDIAN_BITFIELD
1041 union cvmx_npei_dma_control
{
1043 struct cvmx_npei_dma_control_s
{
1044 #ifdef __BIG_ENDIAN_BITFIELD
1045 uint64_t reserved_40_63
:24;
1047 uint64_t dma4_enb
:1;
1048 uint64_t dma3_enb
:1;
1049 uint64_t dma2_enb
:1;
1050 uint64_t dma1_enb
:1;
1051 uint64_t dma0_enb
:1;
1053 uint64_t dwb_denb
:1;
1054 uint64_t dwb_ichk
:9;
1070 uint64_t dwb_ichk
:9;
1071 uint64_t dwb_denb
:1;
1073 uint64_t dma0_enb
:1;
1074 uint64_t dma1_enb
:1;
1075 uint64_t dma2_enb
:1;
1076 uint64_t dma3_enb
:1;
1077 uint64_t dma4_enb
:1;
1079 uint64_t reserved_40_63
:24;
1082 struct cvmx_npei_dma_control_cn52xxp1
{
1083 #ifdef __BIG_ENDIAN_BITFIELD
1084 uint64_t reserved_38_63
:26;
1085 uint64_t dma3_enb
:1;
1086 uint64_t dma2_enb
:1;
1087 uint64_t dma1_enb
:1;
1088 uint64_t dma0_enb
:1;
1090 uint64_t dwb_denb
:1;
1091 uint64_t dwb_ichk
:9;
1107 uint64_t dwb_ichk
:9;
1108 uint64_t dwb_denb
:1;
1110 uint64_t dma0_enb
:1;
1111 uint64_t dma1_enb
:1;
1112 uint64_t dma2_enb
:1;
1113 uint64_t dma3_enb
:1;
1114 uint64_t reserved_38_63
:26;
1117 struct cvmx_npei_dma_control_cn56xxp1
{
1118 #ifdef __BIG_ENDIAN_BITFIELD
1119 uint64_t reserved_39_63
:25;
1120 uint64_t dma4_enb
:1;
1121 uint64_t dma3_enb
:1;
1122 uint64_t dma2_enb
:1;
1123 uint64_t dma1_enb
:1;
1124 uint64_t dma0_enb
:1;
1126 uint64_t dwb_denb
:1;
1127 uint64_t dwb_ichk
:9;
1143 uint64_t dwb_ichk
:9;
1144 uint64_t dwb_denb
:1;
1146 uint64_t dma0_enb
:1;
1147 uint64_t dma1_enb
:1;
1148 uint64_t dma2_enb
:1;
1149 uint64_t dma3_enb
:1;
1150 uint64_t dma4_enb
:1;
1151 uint64_t reserved_39_63
:25;
1156 union cvmx_npei_dma_pcie_req_num
{
1158 struct cvmx_npei_dma_pcie_req_num_s
{
1159 #ifdef __BIG_ENDIAN_BITFIELD
1161 uint64_t reserved_53_62
:10;
1163 uint64_t reserved_45_47
:3;
1164 uint64_t dma4_cnt
:5;
1165 uint64_t reserved_37_39
:3;
1166 uint64_t dma3_cnt
:5;
1167 uint64_t reserved_29_31
:3;
1168 uint64_t dma2_cnt
:5;
1169 uint64_t reserved_21_23
:3;
1170 uint64_t dma1_cnt
:5;
1171 uint64_t reserved_13_15
:3;
1172 uint64_t dma0_cnt
:5;
1173 uint64_t reserved_5_7
:3;
1177 uint64_t reserved_5_7
:3;
1178 uint64_t dma0_cnt
:5;
1179 uint64_t reserved_13_15
:3;
1180 uint64_t dma1_cnt
:5;
1181 uint64_t reserved_21_23
:3;
1182 uint64_t dma2_cnt
:5;
1183 uint64_t reserved_29_31
:3;
1184 uint64_t dma3_cnt
:5;
1185 uint64_t reserved_37_39
:3;
1186 uint64_t dma4_cnt
:5;
1187 uint64_t reserved_45_47
:3;
1189 uint64_t reserved_53_62
:10;
1195 union cvmx_npei_dma_state1
{
1197 struct cvmx_npei_dma_state1_s
{
1198 #ifdef __BIG_ENDIAN_BITFIELD
1199 uint64_t reserved_40_63
:24;
1211 uint64_t reserved_40_63
:24;
1216 union cvmx_npei_dma_state1_p1
{
1218 struct cvmx_npei_dma_state1_p1_s
{
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t reserved_60_63
:4;
1221 uint64_t d0_difst
:7;
1222 uint64_t d1_difst
:7;
1223 uint64_t d2_difst
:7;
1224 uint64_t d3_difst
:7;
1225 uint64_t d4_difst
:7;
1226 uint64_t d0_reqst
:5;
1227 uint64_t d1_reqst
:5;
1228 uint64_t d2_reqst
:5;
1229 uint64_t d3_reqst
:5;
1230 uint64_t d4_reqst
:5;
1232 uint64_t d4_reqst
:5;
1233 uint64_t d3_reqst
:5;
1234 uint64_t d2_reqst
:5;
1235 uint64_t d1_reqst
:5;
1236 uint64_t d0_reqst
:5;
1237 uint64_t d4_difst
:7;
1238 uint64_t d3_difst
:7;
1239 uint64_t d2_difst
:7;
1240 uint64_t d1_difst
:7;
1241 uint64_t d0_difst
:7;
1242 uint64_t reserved_60_63
:4;
1245 struct cvmx_npei_dma_state1_p1_cn52xxp1
{
1246 #ifdef __BIG_ENDIAN_BITFIELD
1247 uint64_t reserved_60_63
:4;
1248 uint64_t d0_difst
:7;
1249 uint64_t d1_difst
:7;
1250 uint64_t d2_difst
:7;
1251 uint64_t d3_difst
:7;
1252 uint64_t reserved_25_31
:7;
1253 uint64_t d0_reqst
:5;
1254 uint64_t d1_reqst
:5;
1255 uint64_t d2_reqst
:5;
1256 uint64_t d3_reqst
:5;
1257 uint64_t reserved_0_4
:5;
1259 uint64_t reserved_0_4
:5;
1260 uint64_t d3_reqst
:5;
1261 uint64_t d2_reqst
:5;
1262 uint64_t d1_reqst
:5;
1263 uint64_t d0_reqst
:5;
1264 uint64_t reserved_25_31
:7;
1265 uint64_t d3_difst
:7;
1266 uint64_t d2_difst
:7;
1267 uint64_t d1_difst
:7;
1268 uint64_t d0_difst
:7;
1269 uint64_t reserved_60_63
:4;
1274 union cvmx_npei_dma_state2
{
1276 struct cvmx_npei_dma_state2_s
{
1277 #ifdef __BIG_ENDIAN_BITFIELD
1278 uint64_t reserved_28_63
:36;
1280 uint64_t reserved_21_23
:3;
1282 uint64_t reserved_10_15
:6;
1286 uint64_t reserved_10_15
:6;
1288 uint64_t reserved_21_23
:3;
1290 uint64_t reserved_28_63
:36;
1295 union cvmx_npei_dma_state2_p1
{
1297 struct cvmx_npei_dma_state2_p1_s
{
1298 #ifdef __BIG_ENDIAN_BITFIELD
1299 uint64_t reserved_45_63
:19;
1300 uint64_t d0_dffst
:9;
1301 uint64_t d1_dffst
:9;
1302 uint64_t d2_dffst
:9;
1303 uint64_t d3_dffst
:9;
1304 uint64_t d4_dffst
:9;
1306 uint64_t d4_dffst
:9;
1307 uint64_t d3_dffst
:9;
1308 uint64_t d2_dffst
:9;
1309 uint64_t d1_dffst
:9;
1310 uint64_t d0_dffst
:9;
1311 uint64_t reserved_45_63
:19;
1314 struct cvmx_npei_dma_state2_p1_cn52xxp1
{
1315 #ifdef __BIG_ENDIAN_BITFIELD
1316 uint64_t reserved_45_63
:19;
1317 uint64_t d0_dffst
:9;
1318 uint64_t d1_dffst
:9;
1319 uint64_t d2_dffst
:9;
1320 uint64_t d3_dffst
:9;
1321 uint64_t reserved_0_8
:9;
1323 uint64_t reserved_0_8
:9;
1324 uint64_t d3_dffst
:9;
1325 uint64_t d2_dffst
:9;
1326 uint64_t d1_dffst
:9;
1327 uint64_t d0_dffst
:9;
1328 uint64_t reserved_45_63
:19;
1333 union cvmx_npei_dma_state3_p1
{
1335 struct cvmx_npei_dma_state3_p1_s
{
1336 #ifdef __BIG_ENDIAN_BITFIELD
1337 uint64_t reserved_60_63
:4;
1338 uint64_t d0_drest
:15;
1339 uint64_t d1_drest
:15;
1340 uint64_t d2_drest
:15;
1341 uint64_t d3_drest
:15;
1343 uint64_t d3_drest
:15;
1344 uint64_t d2_drest
:15;
1345 uint64_t d1_drest
:15;
1346 uint64_t d0_drest
:15;
1347 uint64_t reserved_60_63
:4;
1352 union cvmx_npei_dma_state4_p1
{
1354 struct cvmx_npei_dma_state4_p1_s
{
1355 #ifdef __BIG_ENDIAN_BITFIELD
1356 uint64_t reserved_52_63
:12;
1357 uint64_t d0_dwest
:13;
1358 uint64_t d1_dwest
:13;
1359 uint64_t d2_dwest
:13;
1360 uint64_t d3_dwest
:13;
1362 uint64_t d3_dwest
:13;
1363 uint64_t d2_dwest
:13;
1364 uint64_t d1_dwest
:13;
1365 uint64_t d0_dwest
:13;
1366 uint64_t reserved_52_63
:12;
1371 union cvmx_npei_dma_state5_p1
{
1373 struct cvmx_npei_dma_state5_p1_s
{
1374 #ifdef __BIG_ENDIAN_BITFIELD
1375 uint64_t reserved_28_63
:36;
1376 uint64_t d4_drest
:15;
1377 uint64_t d4_dwest
:13;
1379 uint64_t d4_dwest
:13;
1380 uint64_t d4_drest
:15;
1381 uint64_t reserved_28_63
:36;
1386 union cvmx_npei_int_a_enb
{
1388 struct cvmx_npei_int_a_enb_s
{
1389 #ifdef __BIG_ENDIAN_BITFIELD
1390 uint64_t reserved_10_63
:54;
1391 uint64_t pout_err
:1;
1398 uint64_t pins_err
:1;
1399 uint64_t dma1_cpl
:1;
1400 uint64_t dma0_cpl
:1;
1402 uint64_t dma0_cpl
:1;
1403 uint64_t dma1_cpl
:1;
1404 uint64_t pins_err
:1;
1411 uint64_t pout_err
:1;
1412 uint64_t reserved_10_63
:54;
1415 struct cvmx_npei_int_a_enb_cn52xxp1
{
1416 #ifdef __BIG_ENDIAN_BITFIELD
1417 uint64_t reserved_2_63
:62;
1418 uint64_t dma1_cpl
:1;
1419 uint64_t dma0_cpl
:1;
1421 uint64_t dma0_cpl
:1;
1422 uint64_t dma1_cpl
:1;
1423 uint64_t reserved_2_63
:62;
1428 union cvmx_npei_int_a_enb2
{
1430 struct cvmx_npei_int_a_enb2_s
{
1431 #ifdef __BIG_ENDIAN_BITFIELD
1432 uint64_t reserved_10_63
:54;
1433 uint64_t pout_err
:1;
1440 uint64_t pins_err
:1;
1441 uint64_t dma1_cpl
:1;
1442 uint64_t dma0_cpl
:1;
1444 uint64_t dma0_cpl
:1;
1445 uint64_t dma1_cpl
:1;
1446 uint64_t pins_err
:1;
1453 uint64_t pout_err
:1;
1454 uint64_t reserved_10_63
:54;
1457 struct cvmx_npei_int_a_enb2_cn52xxp1
{
1458 #ifdef __BIG_ENDIAN_BITFIELD
1459 uint64_t reserved_2_63
:62;
1460 uint64_t dma1_cpl
:1;
1461 uint64_t dma0_cpl
:1;
1463 uint64_t dma0_cpl
:1;
1464 uint64_t dma1_cpl
:1;
1465 uint64_t reserved_2_63
:62;
1470 union cvmx_npei_int_a_sum
{
1472 struct cvmx_npei_int_a_sum_s
{
1473 #ifdef __BIG_ENDIAN_BITFIELD
1474 uint64_t reserved_10_63
:54;
1475 uint64_t pout_err
:1;
1482 uint64_t pins_err
:1;
1483 uint64_t dma1_cpl
:1;
1484 uint64_t dma0_cpl
:1;
1486 uint64_t dma0_cpl
:1;
1487 uint64_t dma1_cpl
:1;
1488 uint64_t pins_err
:1;
1495 uint64_t pout_err
:1;
1496 uint64_t reserved_10_63
:54;
1499 struct cvmx_npei_int_a_sum_cn52xxp1
{
1500 #ifdef __BIG_ENDIAN_BITFIELD
1501 uint64_t reserved_2_63
:62;
1502 uint64_t dma1_cpl
:1;
1503 uint64_t dma0_cpl
:1;
1505 uint64_t dma0_cpl
:1;
1506 uint64_t dma1_cpl
:1;
1507 uint64_t reserved_2_63
:62;
1512 union cvmx_npei_int_enb
{
1514 struct cvmx_npei_int_enb_s
{
1515 #ifdef __BIG_ENDIAN_BITFIELD
1516 uint64_t mio_inta
:1;
1517 uint64_t reserved_62_62
:1;
1523 uint64_t c1_up_wf
:1;
1524 uint64_t c0_up_wf
:1;
1525 uint64_t c1_un_wf
:1;
1526 uint64_t c0_un_wf
:1;
1527 uint64_t c1_un_bx
:1;
1528 uint64_t c1_un_wi
:1;
1529 uint64_t c1_un_b2
:1;
1530 uint64_t c1_un_b1
:1;
1531 uint64_t c1_un_b0
:1;
1532 uint64_t c1_up_bx
:1;
1533 uint64_t c1_up_wi
:1;
1534 uint64_t c1_up_b2
:1;
1535 uint64_t c1_up_b1
:1;
1536 uint64_t c1_up_b0
:1;
1537 uint64_t c0_un_bx
:1;
1538 uint64_t c0_un_wi
:1;
1539 uint64_t c0_un_b2
:1;
1540 uint64_t c0_un_b1
:1;
1541 uint64_t c0_un_b0
:1;
1542 uint64_t c0_up_bx
:1;
1543 uint64_t c0_up_wi
:1;
1544 uint64_t c0_up_b2
:1;
1545 uint64_t c0_up_b1
:1;
1546 uint64_t c0_up_b0
:1;
1547 uint64_t c1_hpint
:1;
1554 uint64_t c0_hpint
:1;
1606 uint64_t c0_hpint
:1;
1613 uint64_t c1_hpint
:1;
1614 uint64_t c0_up_b0
:1;
1615 uint64_t c0_up_b1
:1;
1616 uint64_t c0_up_b2
:1;
1617 uint64_t c0_up_wi
:1;
1618 uint64_t c0_up_bx
:1;
1619 uint64_t c0_un_b0
:1;
1620 uint64_t c0_un_b1
:1;
1621 uint64_t c0_un_b2
:1;
1622 uint64_t c0_un_wi
:1;
1623 uint64_t c0_un_bx
:1;
1624 uint64_t c1_up_b0
:1;
1625 uint64_t c1_up_b1
:1;
1626 uint64_t c1_up_b2
:1;
1627 uint64_t c1_up_wi
:1;
1628 uint64_t c1_up_bx
:1;
1629 uint64_t c1_un_b0
:1;
1630 uint64_t c1_un_b1
:1;
1631 uint64_t c1_un_b2
:1;
1632 uint64_t c1_un_wi
:1;
1633 uint64_t c1_un_bx
:1;
1634 uint64_t c0_un_wf
:1;
1635 uint64_t c1_un_wf
:1;
1636 uint64_t c0_up_wf
:1;
1637 uint64_t c1_up_wf
:1;
1643 uint64_t reserved_62_62
:1;
1644 uint64_t mio_inta
:1;
1647 struct cvmx_npei_int_enb_cn52xxp1
{
1648 #ifdef __BIG_ENDIAN_BITFIELD
1649 uint64_t mio_inta
:1;
1650 uint64_t reserved_62_62
:1;
1656 uint64_t c1_up_wf
:1;
1657 uint64_t c0_up_wf
:1;
1658 uint64_t c1_un_wf
:1;
1659 uint64_t c0_un_wf
:1;
1660 uint64_t c1_un_bx
:1;
1661 uint64_t c1_un_wi
:1;
1662 uint64_t c1_un_b2
:1;
1663 uint64_t c1_un_b1
:1;
1664 uint64_t c1_un_b0
:1;
1665 uint64_t c1_up_bx
:1;
1666 uint64_t c1_up_wi
:1;
1667 uint64_t c1_up_b2
:1;
1668 uint64_t c1_up_b1
:1;
1669 uint64_t c1_up_b0
:1;
1670 uint64_t c0_un_bx
:1;
1671 uint64_t c0_un_wi
:1;
1672 uint64_t c0_un_b2
:1;
1673 uint64_t c0_un_b1
:1;
1674 uint64_t c0_un_b0
:1;
1675 uint64_t c0_up_bx
:1;
1676 uint64_t c0_up_wi
:1;
1677 uint64_t c0_up_b2
:1;
1678 uint64_t c0_up_b1
:1;
1679 uint64_t c0_up_b0
:1;
1680 uint64_t c1_hpint
:1;
1687 uint64_t c0_hpint
:1;
1704 uint64_t reserved_8_8
:1;
1722 uint64_t reserved_8_8
:1;
1739 uint64_t c0_hpint
:1;
1746 uint64_t c1_hpint
:1;
1747 uint64_t c0_up_b0
:1;
1748 uint64_t c0_up_b1
:1;
1749 uint64_t c0_up_b2
:1;
1750 uint64_t c0_up_wi
:1;
1751 uint64_t c0_up_bx
:1;
1752 uint64_t c0_un_b0
:1;
1753 uint64_t c0_un_b1
:1;
1754 uint64_t c0_un_b2
:1;
1755 uint64_t c0_un_wi
:1;
1756 uint64_t c0_un_bx
:1;
1757 uint64_t c1_up_b0
:1;
1758 uint64_t c1_up_b1
:1;
1759 uint64_t c1_up_b2
:1;
1760 uint64_t c1_up_wi
:1;
1761 uint64_t c1_up_bx
:1;
1762 uint64_t c1_un_b0
:1;
1763 uint64_t c1_un_b1
:1;
1764 uint64_t c1_un_b2
:1;
1765 uint64_t c1_un_wi
:1;
1766 uint64_t c1_un_bx
:1;
1767 uint64_t c0_un_wf
:1;
1768 uint64_t c1_un_wf
:1;
1769 uint64_t c0_up_wf
:1;
1770 uint64_t c1_up_wf
:1;
1776 uint64_t reserved_62_62
:1;
1777 uint64_t mio_inta
:1;
1780 struct cvmx_npei_int_enb_cn56xxp1
{
1781 #ifdef __BIG_ENDIAN_BITFIELD
1782 uint64_t mio_inta
:1;
1783 uint64_t reserved_61_62
:2;
1788 uint64_t c1_up_wf
:1;
1789 uint64_t c0_up_wf
:1;
1790 uint64_t c1_un_wf
:1;
1791 uint64_t c0_un_wf
:1;
1792 uint64_t c1_un_bx
:1;
1793 uint64_t c1_un_wi
:1;
1794 uint64_t c1_un_b2
:1;
1795 uint64_t c1_un_b1
:1;
1796 uint64_t c1_un_b0
:1;
1797 uint64_t c1_up_bx
:1;
1798 uint64_t c1_up_wi
:1;
1799 uint64_t c1_up_b2
:1;
1800 uint64_t c1_up_b1
:1;
1801 uint64_t c1_up_b0
:1;
1802 uint64_t c0_un_bx
:1;
1803 uint64_t c0_un_wi
:1;
1804 uint64_t c0_un_b2
:1;
1805 uint64_t c0_un_b1
:1;
1806 uint64_t c0_un_b0
:1;
1807 uint64_t c0_up_bx
:1;
1808 uint64_t c0_up_wi
:1;
1809 uint64_t c0_up_b2
:1;
1810 uint64_t c0_up_b1
:1;
1811 uint64_t c0_up_b0
:1;
1812 uint64_t c1_hpint
:1;
1815 uint64_t reserved_29_29
:1;
1817 uint64_t reserved_27_27
:1;
1819 uint64_t c0_hpint
:1;
1822 uint64_t reserved_22_22
:1;
1824 uint64_t reserved_20_20
:1;
1866 uint64_t reserved_20_20
:1;
1868 uint64_t reserved_22_22
:1;
1871 uint64_t c0_hpint
:1;
1873 uint64_t reserved_27_27
:1;
1875 uint64_t reserved_29_29
:1;
1878 uint64_t c1_hpint
:1;
1879 uint64_t c0_up_b0
:1;
1880 uint64_t c0_up_b1
:1;
1881 uint64_t c0_up_b2
:1;
1882 uint64_t c0_up_wi
:1;
1883 uint64_t c0_up_bx
:1;
1884 uint64_t c0_un_b0
:1;
1885 uint64_t c0_un_b1
:1;
1886 uint64_t c0_un_b2
:1;
1887 uint64_t c0_un_wi
:1;
1888 uint64_t c0_un_bx
:1;
1889 uint64_t c1_up_b0
:1;
1890 uint64_t c1_up_b1
:1;
1891 uint64_t c1_up_b2
:1;
1892 uint64_t c1_up_wi
:1;
1893 uint64_t c1_up_bx
:1;
1894 uint64_t c1_un_b0
:1;
1895 uint64_t c1_un_b1
:1;
1896 uint64_t c1_un_b2
:1;
1897 uint64_t c1_un_wi
:1;
1898 uint64_t c1_un_bx
:1;
1899 uint64_t c0_un_wf
:1;
1900 uint64_t c1_un_wf
:1;
1901 uint64_t c0_up_wf
:1;
1902 uint64_t c1_up_wf
:1;
1907 uint64_t reserved_61_62
:2;
1908 uint64_t mio_inta
:1;
1913 union cvmx_npei_int_enb2
{
1915 struct cvmx_npei_int_enb2_s
{
1916 #ifdef __BIG_ENDIAN_BITFIELD
1917 uint64_t reserved_62_63
:2;
1923 uint64_t c1_up_wf
:1;
1924 uint64_t c0_up_wf
:1;
1925 uint64_t c1_un_wf
:1;
1926 uint64_t c0_un_wf
:1;
1927 uint64_t c1_un_bx
:1;
1928 uint64_t c1_un_wi
:1;
1929 uint64_t c1_un_b2
:1;
1930 uint64_t c1_un_b1
:1;
1931 uint64_t c1_un_b0
:1;
1932 uint64_t c1_up_bx
:1;
1933 uint64_t c1_up_wi
:1;
1934 uint64_t c1_up_b2
:1;
1935 uint64_t c1_up_b1
:1;
1936 uint64_t c1_up_b0
:1;
1937 uint64_t c0_un_bx
:1;
1938 uint64_t c0_un_wi
:1;
1939 uint64_t c0_un_b2
:1;
1940 uint64_t c0_un_b1
:1;
1941 uint64_t c0_un_b0
:1;
1942 uint64_t c0_up_bx
:1;
1943 uint64_t c0_up_wi
:1;
1944 uint64_t c0_up_b2
:1;
1945 uint64_t c0_up_b1
:1;
1946 uint64_t c0_up_b0
:1;
1947 uint64_t c1_hpint
:1;
1954 uint64_t c0_hpint
:1;
2006 uint64_t c0_hpint
:1;
2013 uint64_t c1_hpint
:1;
2014 uint64_t c0_up_b0
:1;
2015 uint64_t c0_up_b1
:1;
2016 uint64_t c0_up_b2
:1;
2017 uint64_t c0_up_wi
:1;
2018 uint64_t c0_up_bx
:1;
2019 uint64_t c0_un_b0
:1;
2020 uint64_t c0_un_b1
:1;
2021 uint64_t c0_un_b2
:1;
2022 uint64_t c0_un_wi
:1;
2023 uint64_t c0_un_bx
:1;
2024 uint64_t c1_up_b0
:1;
2025 uint64_t c1_up_b1
:1;
2026 uint64_t c1_up_b2
:1;
2027 uint64_t c1_up_wi
:1;
2028 uint64_t c1_up_bx
:1;
2029 uint64_t c1_un_b0
:1;
2030 uint64_t c1_un_b1
:1;
2031 uint64_t c1_un_b2
:1;
2032 uint64_t c1_un_wi
:1;
2033 uint64_t c1_un_bx
:1;
2034 uint64_t c0_un_wf
:1;
2035 uint64_t c1_un_wf
:1;
2036 uint64_t c0_up_wf
:1;
2037 uint64_t c1_up_wf
:1;
2043 uint64_t reserved_62_63
:2;
2046 struct cvmx_npei_int_enb2_cn52xxp1
{
2047 #ifdef __BIG_ENDIAN_BITFIELD
2048 uint64_t reserved_62_63
:2;
2054 uint64_t c1_up_wf
:1;
2055 uint64_t c0_up_wf
:1;
2056 uint64_t c1_un_wf
:1;
2057 uint64_t c0_un_wf
:1;
2058 uint64_t c1_un_bx
:1;
2059 uint64_t c1_un_wi
:1;
2060 uint64_t c1_un_b2
:1;
2061 uint64_t c1_un_b1
:1;
2062 uint64_t c1_un_b0
:1;
2063 uint64_t c1_up_bx
:1;
2064 uint64_t c1_up_wi
:1;
2065 uint64_t c1_up_b2
:1;
2066 uint64_t c1_up_b1
:1;
2067 uint64_t c1_up_b0
:1;
2068 uint64_t c0_un_bx
:1;
2069 uint64_t c0_un_wi
:1;
2070 uint64_t c0_un_b2
:1;
2071 uint64_t c0_un_b1
:1;
2072 uint64_t c0_un_b0
:1;
2073 uint64_t c0_up_bx
:1;
2074 uint64_t c0_up_wi
:1;
2075 uint64_t c0_up_b2
:1;
2076 uint64_t c0_up_b1
:1;
2077 uint64_t c0_up_b0
:1;
2078 uint64_t c1_hpint
:1;
2085 uint64_t c0_hpint
:1;
2102 uint64_t reserved_8_8
:1;
2120 uint64_t reserved_8_8
:1;
2137 uint64_t c0_hpint
:1;
2144 uint64_t c1_hpint
:1;
2145 uint64_t c0_up_b0
:1;
2146 uint64_t c0_up_b1
:1;
2147 uint64_t c0_up_b2
:1;
2148 uint64_t c0_up_wi
:1;
2149 uint64_t c0_up_bx
:1;
2150 uint64_t c0_un_b0
:1;
2151 uint64_t c0_un_b1
:1;
2152 uint64_t c0_un_b2
:1;
2153 uint64_t c0_un_wi
:1;
2154 uint64_t c0_un_bx
:1;
2155 uint64_t c1_up_b0
:1;
2156 uint64_t c1_up_b1
:1;
2157 uint64_t c1_up_b2
:1;
2158 uint64_t c1_up_wi
:1;
2159 uint64_t c1_up_bx
:1;
2160 uint64_t c1_un_b0
:1;
2161 uint64_t c1_un_b1
:1;
2162 uint64_t c1_un_b2
:1;
2163 uint64_t c1_un_wi
:1;
2164 uint64_t c1_un_bx
:1;
2165 uint64_t c0_un_wf
:1;
2166 uint64_t c1_un_wf
:1;
2167 uint64_t c0_up_wf
:1;
2168 uint64_t c1_up_wf
:1;
2174 uint64_t reserved_62_63
:2;
2177 struct cvmx_npei_int_enb2_cn56xxp1
{
2178 #ifdef __BIG_ENDIAN_BITFIELD
2179 uint64_t reserved_61_63
:3;
2184 uint64_t c1_up_wf
:1;
2185 uint64_t c0_up_wf
:1;
2186 uint64_t c1_un_wf
:1;
2187 uint64_t c0_un_wf
:1;
2188 uint64_t c1_un_bx
:1;
2189 uint64_t c1_un_wi
:1;
2190 uint64_t c1_un_b2
:1;
2191 uint64_t c1_un_b1
:1;
2192 uint64_t c1_un_b0
:1;
2193 uint64_t c1_up_bx
:1;
2194 uint64_t c1_up_wi
:1;
2195 uint64_t c1_up_b2
:1;
2196 uint64_t c1_up_b1
:1;
2197 uint64_t c1_up_b0
:1;
2198 uint64_t c0_un_bx
:1;
2199 uint64_t c0_un_wi
:1;
2200 uint64_t c0_un_b2
:1;
2201 uint64_t c0_un_b1
:1;
2202 uint64_t c0_un_b0
:1;
2203 uint64_t c0_up_bx
:1;
2204 uint64_t c0_up_wi
:1;
2205 uint64_t c0_up_b2
:1;
2206 uint64_t c0_up_b1
:1;
2207 uint64_t c0_up_b0
:1;
2208 uint64_t c1_hpint
:1;
2211 uint64_t reserved_29_29
:1;
2213 uint64_t reserved_27_27
:1;
2215 uint64_t c0_hpint
:1;
2218 uint64_t reserved_22_22
:1;
2220 uint64_t reserved_20_20
:1;
2262 uint64_t reserved_20_20
:1;
2264 uint64_t reserved_22_22
:1;
2267 uint64_t c0_hpint
:1;
2269 uint64_t reserved_27_27
:1;
2271 uint64_t reserved_29_29
:1;
2274 uint64_t c1_hpint
:1;
2275 uint64_t c0_up_b0
:1;
2276 uint64_t c0_up_b1
:1;
2277 uint64_t c0_up_b2
:1;
2278 uint64_t c0_up_wi
:1;
2279 uint64_t c0_up_bx
:1;
2280 uint64_t c0_un_b0
:1;
2281 uint64_t c0_un_b1
:1;
2282 uint64_t c0_un_b2
:1;
2283 uint64_t c0_un_wi
:1;
2284 uint64_t c0_un_bx
:1;
2285 uint64_t c1_up_b0
:1;
2286 uint64_t c1_up_b1
:1;
2287 uint64_t c1_up_b2
:1;
2288 uint64_t c1_up_wi
:1;
2289 uint64_t c1_up_bx
:1;
2290 uint64_t c1_un_b0
:1;
2291 uint64_t c1_un_b1
:1;
2292 uint64_t c1_un_b2
:1;
2293 uint64_t c1_un_wi
:1;
2294 uint64_t c1_un_bx
:1;
2295 uint64_t c0_un_wf
:1;
2296 uint64_t c1_un_wf
:1;
2297 uint64_t c0_up_wf
:1;
2298 uint64_t c1_up_wf
:1;
2303 uint64_t reserved_61_63
:3;
2308 union cvmx_npei_int_info
{
2310 struct cvmx_npei_int_info_s
{
2311 #ifdef __BIG_ENDIAN_BITFIELD
2312 uint64_t reserved_12_63
:52;
2318 uint64_t reserved_12_63
:52;
2323 union cvmx_npei_int_sum
{
2325 struct cvmx_npei_int_sum_s
{
2326 #ifdef __BIG_ENDIAN_BITFIELD
2327 uint64_t mio_inta
:1;
2328 uint64_t reserved_62_62
:1;
2334 uint64_t c1_up_wf
:1;
2335 uint64_t c0_up_wf
:1;
2336 uint64_t c1_un_wf
:1;
2337 uint64_t c0_un_wf
:1;
2338 uint64_t c1_un_bx
:1;
2339 uint64_t c1_un_wi
:1;
2340 uint64_t c1_un_b2
:1;
2341 uint64_t c1_un_b1
:1;
2342 uint64_t c1_un_b0
:1;
2343 uint64_t c1_up_bx
:1;
2344 uint64_t c1_up_wi
:1;
2345 uint64_t c1_up_b2
:1;
2346 uint64_t c1_up_b1
:1;
2347 uint64_t c1_up_b0
:1;
2348 uint64_t c0_un_bx
:1;
2349 uint64_t c0_un_wi
:1;
2350 uint64_t c0_un_b2
:1;
2351 uint64_t c0_un_b1
:1;
2352 uint64_t c0_un_b0
:1;
2353 uint64_t c0_up_bx
:1;
2354 uint64_t c0_up_wi
:1;
2355 uint64_t c0_up_b2
:1;
2356 uint64_t c0_up_b1
:1;
2357 uint64_t c0_up_b0
:1;
2358 uint64_t c1_hpint
:1;
2365 uint64_t c0_hpint
:1;
2417 uint64_t c0_hpint
:1;
2424 uint64_t c1_hpint
:1;
2425 uint64_t c0_up_b0
:1;
2426 uint64_t c0_up_b1
:1;
2427 uint64_t c0_up_b2
:1;
2428 uint64_t c0_up_wi
:1;
2429 uint64_t c0_up_bx
:1;
2430 uint64_t c0_un_b0
:1;
2431 uint64_t c0_un_b1
:1;
2432 uint64_t c0_un_b2
:1;
2433 uint64_t c0_un_wi
:1;
2434 uint64_t c0_un_bx
:1;
2435 uint64_t c1_up_b0
:1;
2436 uint64_t c1_up_b1
:1;
2437 uint64_t c1_up_b2
:1;
2438 uint64_t c1_up_wi
:1;
2439 uint64_t c1_up_bx
:1;
2440 uint64_t c1_un_b0
:1;
2441 uint64_t c1_un_b1
:1;
2442 uint64_t c1_un_b2
:1;
2443 uint64_t c1_un_wi
:1;
2444 uint64_t c1_un_bx
:1;
2445 uint64_t c0_un_wf
:1;
2446 uint64_t c1_un_wf
:1;
2447 uint64_t c0_up_wf
:1;
2448 uint64_t c1_up_wf
:1;
2454 uint64_t reserved_62_62
:1;
2455 uint64_t mio_inta
:1;
2458 struct cvmx_npei_int_sum_cn52xxp1
{
2459 #ifdef __BIG_ENDIAN_BITFIELD
2460 uint64_t mio_inta
:1;
2461 uint64_t reserved_62_62
:1;
2467 uint64_t c1_up_wf
:1;
2468 uint64_t c0_up_wf
:1;
2469 uint64_t c1_un_wf
:1;
2470 uint64_t c0_un_wf
:1;
2471 uint64_t c1_un_bx
:1;
2472 uint64_t c1_un_wi
:1;
2473 uint64_t c1_un_b2
:1;
2474 uint64_t c1_un_b1
:1;
2475 uint64_t c1_un_b0
:1;
2476 uint64_t c1_up_bx
:1;
2477 uint64_t c1_up_wi
:1;
2478 uint64_t c1_up_b2
:1;
2479 uint64_t c1_up_b1
:1;
2480 uint64_t c1_up_b0
:1;
2481 uint64_t c0_un_bx
:1;
2482 uint64_t c0_un_wi
:1;
2483 uint64_t c0_un_b2
:1;
2484 uint64_t c0_un_b1
:1;
2485 uint64_t c0_un_b0
:1;
2486 uint64_t c0_up_bx
:1;
2487 uint64_t c0_up_wi
:1;
2488 uint64_t c0_up_b2
:1;
2489 uint64_t c0_up_b1
:1;
2490 uint64_t c0_up_b0
:1;
2491 uint64_t c1_hpint
:1;
2498 uint64_t c0_hpint
:1;
2505 uint64_t reserved_15_18
:4;
2512 uint64_t reserved_8_8
:1;
2530 uint64_t reserved_8_8
:1;
2537 uint64_t reserved_15_18
:4;
2544 uint64_t c0_hpint
:1;
2551 uint64_t c1_hpint
:1;
2552 uint64_t c0_up_b0
:1;
2553 uint64_t c0_up_b1
:1;
2554 uint64_t c0_up_b2
:1;
2555 uint64_t c0_up_wi
:1;
2556 uint64_t c0_up_bx
:1;
2557 uint64_t c0_un_b0
:1;
2558 uint64_t c0_un_b1
:1;
2559 uint64_t c0_un_b2
:1;
2560 uint64_t c0_un_wi
:1;
2561 uint64_t c0_un_bx
:1;
2562 uint64_t c1_up_b0
:1;
2563 uint64_t c1_up_b1
:1;
2564 uint64_t c1_up_b2
:1;
2565 uint64_t c1_up_wi
:1;
2566 uint64_t c1_up_bx
:1;
2567 uint64_t c1_un_b0
:1;
2568 uint64_t c1_un_b1
:1;
2569 uint64_t c1_un_b2
:1;
2570 uint64_t c1_un_wi
:1;
2571 uint64_t c1_un_bx
:1;
2572 uint64_t c0_un_wf
:1;
2573 uint64_t c1_un_wf
:1;
2574 uint64_t c0_up_wf
:1;
2575 uint64_t c1_up_wf
:1;
2581 uint64_t reserved_62_62
:1;
2582 uint64_t mio_inta
:1;
2585 struct cvmx_npei_int_sum_cn56xxp1
{
2586 #ifdef __BIG_ENDIAN_BITFIELD
2587 uint64_t mio_inta
:1;
2588 uint64_t reserved_61_62
:2;
2593 uint64_t c1_up_wf
:1;
2594 uint64_t c0_up_wf
:1;
2595 uint64_t c1_un_wf
:1;
2596 uint64_t c0_un_wf
:1;
2597 uint64_t c1_un_bx
:1;
2598 uint64_t c1_un_wi
:1;
2599 uint64_t c1_un_b2
:1;
2600 uint64_t c1_un_b1
:1;
2601 uint64_t c1_un_b0
:1;
2602 uint64_t c1_up_bx
:1;
2603 uint64_t c1_up_wi
:1;
2604 uint64_t c1_up_b2
:1;
2605 uint64_t c1_up_b1
:1;
2606 uint64_t c1_up_b0
:1;
2607 uint64_t c0_un_bx
:1;
2608 uint64_t c0_un_wi
:1;
2609 uint64_t c0_un_b2
:1;
2610 uint64_t c0_un_b1
:1;
2611 uint64_t c0_un_b0
:1;
2612 uint64_t c0_up_bx
:1;
2613 uint64_t c0_up_wi
:1;
2614 uint64_t c0_up_b2
:1;
2615 uint64_t c0_up_b1
:1;
2616 uint64_t c0_up_b0
:1;
2617 uint64_t c1_hpint
:1;
2620 uint64_t reserved_29_29
:1;
2622 uint64_t reserved_27_27
:1;
2624 uint64_t c0_hpint
:1;
2627 uint64_t reserved_22_22
:1;
2629 uint64_t reserved_20_20
:1;
2631 uint64_t reserved_15_18
:4;
2663 uint64_t reserved_15_18
:4;
2665 uint64_t reserved_20_20
:1;
2667 uint64_t reserved_22_22
:1;
2670 uint64_t c0_hpint
:1;
2672 uint64_t reserved_27_27
:1;
2674 uint64_t reserved_29_29
:1;
2677 uint64_t c1_hpint
:1;
2678 uint64_t c0_up_b0
:1;
2679 uint64_t c0_up_b1
:1;
2680 uint64_t c0_up_b2
:1;
2681 uint64_t c0_up_wi
:1;
2682 uint64_t c0_up_bx
:1;
2683 uint64_t c0_un_b0
:1;
2684 uint64_t c0_un_b1
:1;
2685 uint64_t c0_un_b2
:1;
2686 uint64_t c0_un_wi
:1;
2687 uint64_t c0_un_bx
:1;
2688 uint64_t c1_up_b0
:1;
2689 uint64_t c1_up_b1
:1;
2690 uint64_t c1_up_b2
:1;
2691 uint64_t c1_up_wi
:1;
2692 uint64_t c1_up_bx
:1;
2693 uint64_t c1_un_b0
:1;
2694 uint64_t c1_un_b1
:1;
2695 uint64_t c1_un_b2
:1;
2696 uint64_t c1_un_wi
:1;
2697 uint64_t c1_un_bx
:1;
2698 uint64_t c0_un_wf
:1;
2699 uint64_t c1_un_wf
:1;
2700 uint64_t c0_up_wf
:1;
2701 uint64_t c1_up_wf
:1;
2706 uint64_t reserved_61_62
:2;
2707 uint64_t mio_inta
:1;
2712 union cvmx_npei_int_sum2
{
2714 struct cvmx_npei_int_sum2_s
{
2715 #ifdef __BIG_ENDIAN_BITFIELD
2716 uint64_t mio_inta
:1;
2717 uint64_t reserved_62_62
:1;
2723 uint64_t c1_up_wf
:1;
2724 uint64_t c0_up_wf
:1;
2725 uint64_t c1_un_wf
:1;
2726 uint64_t c0_un_wf
:1;
2727 uint64_t c1_un_bx
:1;
2728 uint64_t c1_un_wi
:1;
2729 uint64_t c1_un_b2
:1;
2730 uint64_t c1_un_b1
:1;
2731 uint64_t c1_un_b0
:1;
2732 uint64_t c1_up_bx
:1;
2733 uint64_t c1_up_wi
:1;
2734 uint64_t c1_up_b2
:1;
2735 uint64_t c1_up_b1
:1;
2736 uint64_t c1_up_b0
:1;
2737 uint64_t c0_un_bx
:1;
2738 uint64_t c0_un_wi
:1;
2739 uint64_t c0_un_b2
:1;
2740 uint64_t c0_un_b1
:1;
2741 uint64_t c0_un_b0
:1;
2742 uint64_t c0_up_bx
:1;
2743 uint64_t c0_up_wi
:1;
2744 uint64_t c0_up_b2
:1;
2745 uint64_t c0_up_b1
:1;
2746 uint64_t c0_up_b0
:1;
2747 uint64_t c1_hpint
:1;
2754 uint64_t c0_hpint
:1;
2761 uint64_t reserved_15_18
:4;
2768 uint64_t reserved_8_8
:1;
2786 uint64_t reserved_8_8
:1;
2793 uint64_t reserved_15_18
:4;
2800 uint64_t c0_hpint
:1;
2807 uint64_t c1_hpint
:1;
2808 uint64_t c0_up_b0
:1;
2809 uint64_t c0_up_b1
:1;
2810 uint64_t c0_up_b2
:1;
2811 uint64_t c0_up_wi
:1;
2812 uint64_t c0_up_bx
:1;
2813 uint64_t c0_un_b0
:1;
2814 uint64_t c0_un_b1
:1;
2815 uint64_t c0_un_b2
:1;
2816 uint64_t c0_un_wi
:1;
2817 uint64_t c0_un_bx
:1;
2818 uint64_t c1_up_b0
:1;
2819 uint64_t c1_up_b1
:1;
2820 uint64_t c1_up_b2
:1;
2821 uint64_t c1_up_wi
:1;
2822 uint64_t c1_up_bx
:1;
2823 uint64_t c1_un_b0
:1;
2824 uint64_t c1_un_b1
:1;
2825 uint64_t c1_un_b2
:1;
2826 uint64_t c1_un_wi
:1;
2827 uint64_t c1_un_bx
:1;
2828 uint64_t c0_un_wf
:1;
2829 uint64_t c1_un_wf
:1;
2830 uint64_t c0_up_wf
:1;
2831 uint64_t c1_up_wf
:1;
2837 uint64_t reserved_62_62
:1;
2838 uint64_t mio_inta
:1;
2843 union cvmx_npei_last_win_rdata0
{
2845 struct cvmx_npei_last_win_rdata0_s
{
2846 #ifdef __BIG_ENDIAN_BITFIELD
2854 union cvmx_npei_last_win_rdata1
{
2856 struct cvmx_npei_last_win_rdata1_s
{
2857 #ifdef __BIG_ENDIAN_BITFIELD
2865 union cvmx_npei_mem_access_ctl
{
2867 struct cvmx_npei_mem_access_ctl_s
{
2868 #ifdef __BIG_ENDIAN_BITFIELD
2869 uint64_t reserved_14_63
:50;
2870 uint64_t max_word
:4;
2874 uint64_t max_word
:4;
2875 uint64_t reserved_14_63
:50;
2880 union cvmx_npei_mem_access_subidx
{
2882 struct cvmx_npei_mem_access_subidx_s
{
2883 #ifdef __BIG_ENDIAN_BITFIELD
2884 uint64_t reserved_42_63
:22;
2906 uint64_t reserved_42_63
:22;
2911 union cvmx_npei_msi_enb0
{
2913 struct cvmx_npei_msi_enb0_s
{
2914 #ifdef __BIG_ENDIAN_BITFIELD
2922 union cvmx_npei_msi_enb1
{
2924 struct cvmx_npei_msi_enb1_s
{
2925 #ifdef __BIG_ENDIAN_BITFIELD
2933 union cvmx_npei_msi_enb2
{
2935 struct cvmx_npei_msi_enb2_s
{
2936 #ifdef __BIG_ENDIAN_BITFIELD
2944 union cvmx_npei_msi_enb3
{
2946 struct cvmx_npei_msi_enb3_s
{
2947 #ifdef __BIG_ENDIAN_BITFIELD
2955 union cvmx_npei_msi_rcv0
{
2957 struct cvmx_npei_msi_rcv0_s
{
2958 #ifdef __BIG_ENDIAN_BITFIELD
2966 union cvmx_npei_msi_rcv1
{
2968 struct cvmx_npei_msi_rcv1_s
{
2969 #ifdef __BIG_ENDIAN_BITFIELD
2977 union cvmx_npei_msi_rcv2
{
2979 struct cvmx_npei_msi_rcv2_s
{
2980 #ifdef __BIG_ENDIAN_BITFIELD
2988 union cvmx_npei_msi_rcv3
{
2990 struct cvmx_npei_msi_rcv3_s
{
2991 #ifdef __BIG_ENDIAN_BITFIELD
2999 union cvmx_npei_msi_rd_map
{
3001 struct cvmx_npei_msi_rd_map_s
{
3002 #ifdef __BIG_ENDIAN_BITFIELD
3003 uint64_t reserved_16_63
:48;
3009 uint64_t reserved_16_63
:48;
3014 union cvmx_npei_msi_w1c_enb0
{
3016 struct cvmx_npei_msi_w1c_enb0_s
{
3017 #ifdef __BIG_ENDIAN_BITFIELD
3025 union cvmx_npei_msi_w1c_enb1
{
3027 struct cvmx_npei_msi_w1c_enb1_s
{
3028 #ifdef __BIG_ENDIAN_BITFIELD
3036 union cvmx_npei_msi_w1c_enb2
{
3038 struct cvmx_npei_msi_w1c_enb2_s
{
3039 #ifdef __BIG_ENDIAN_BITFIELD
3047 union cvmx_npei_msi_w1c_enb3
{
3049 struct cvmx_npei_msi_w1c_enb3_s
{
3050 #ifdef __BIG_ENDIAN_BITFIELD
3058 union cvmx_npei_msi_w1s_enb0
{
3060 struct cvmx_npei_msi_w1s_enb0_s
{
3061 #ifdef __BIG_ENDIAN_BITFIELD
3069 union cvmx_npei_msi_w1s_enb1
{
3071 struct cvmx_npei_msi_w1s_enb1_s
{
3072 #ifdef __BIG_ENDIAN_BITFIELD
3080 union cvmx_npei_msi_w1s_enb2
{
3082 struct cvmx_npei_msi_w1s_enb2_s
{
3083 #ifdef __BIG_ENDIAN_BITFIELD
3091 union cvmx_npei_msi_w1s_enb3
{
3093 struct cvmx_npei_msi_w1s_enb3_s
{
3094 #ifdef __BIG_ENDIAN_BITFIELD
3102 union cvmx_npei_msi_wr_map
{
3104 struct cvmx_npei_msi_wr_map_s
{
3105 #ifdef __BIG_ENDIAN_BITFIELD
3106 uint64_t reserved_16_63
:48;
3112 uint64_t reserved_16_63
:48;
3117 union cvmx_npei_pcie_credit_cnt
{
3119 struct cvmx_npei_pcie_credit_cnt_s
{
3120 #ifdef __BIG_ENDIAN_BITFIELD
3121 uint64_t reserved_48_63
:16;
3135 uint64_t reserved_48_63
:16;
3140 union cvmx_npei_pcie_msi_rcv
{
3142 struct cvmx_npei_pcie_msi_rcv_s
{
3143 #ifdef __BIG_ENDIAN_BITFIELD
3144 uint64_t reserved_8_63
:56;
3148 uint64_t reserved_8_63
:56;
3153 union cvmx_npei_pcie_msi_rcv_b1
{
3155 struct cvmx_npei_pcie_msi_rcv_b1_s
{
3156 #ifdef __BIG_ENDIAN_BITFIELD
3157 uint64_t reserved_16_63
:48;
3159 uint64_t reserved_0_7
:8;
3161 uint64_t reserved_0_7
:8;
3163 uint64_t reserved_16_63
:48;
3168 union cvmx_npei_pcie_msi_rcv_b2
{
3170 struct cvmx_npei_pcie_msi_rcv_b2_s
{
3171 #ifdef __BIG_ENDIAN_BITFIELD
3172 uint64_t reserved_24_63
:40;
3174 uint64_t reserved_0_15
:16;
3176 uint64_t reserved_0_15
:16;
3178 uint64_t reserved_24_63
:40;
3183 union cvmx_npei_pcie_msi_rcv_b3
{
3185 struct cvmx_npei_pcie_msi_rcv_b3_s
{
3186 #ifdef __BIG_ENDIAN_BITFIELD
3187 uint64_t reserved_32_63
:32;
3189 uint64_t reserved_0_23
:24;
3191 uint64_t reserved_0_23
:24;
3193 uint64_t reserved_32_63
:32;
3198 union cvmx_npei_pktx_cnts
{
3200 struct cvmx_npei_pktx_cnts_s
{
3201 #ifdef __BIG_ENDIAN_BITFIELD
3202 uint64_t reserved_54_63
:10;
3208 uint64_t reserved_54_63
:10;
3213 union cvmx_npei_pktx_in_bp
{
3215 struct cvmx_npei_pktx_in_bp_s
{
3216 #ifdef __BIG_ENDIAN_BITFIELD
3226 union cvmx_npei_pktx_instr_baddr
{
3228 struct cvmx_npei_pktx_instr_baddr_s
{
3229 #ifdef __BIG_ENDIAN_BITFIELD
3231 uint64_t reserved_0_2
:3;
3233 uint64_t reserved_0_2
:3;
3239 union cvmx_npei_pktx_instr_baoff_dbell
{
3241 struct cvmx_npei_pktx_instr_baoff_dbell_s
{
3242 #ifdef __BIG_ENDIAN_BITFIELD
3252 union cvmx_npei_pktx_instr_fifo_rsize
{
3254 struct cvmx_npei_pktx_instr_fifo_rsize_s
{
3255 #ifdef __BIG_ENDIAN_BITFIELD
3271 union cvmx_npei_pktx_instr_header
{
3273 struct cvmx_npei_pktx_instr_header_s
{
3274 #ifdef __BIG_ENDIAN_BITFIELD
3275 uint64_t reserved_44_63
:20;
3277 uint64_t reserved_38_42
:5;
3278 uint64_t rparmode
:2;
3279 uint64_t reserved_35_35
:1;
3280 uint64_t rskp_len
:7;
3281 uint64_t reserved_22_27
:6;
3282 uint64_t use_ihdr
:1;
3283 uint64_t reserved_16_20
:5;
3284 uint64_t par_mode
:2;
3285 uint64_t reserved_13_13
:1;
3287 uint64_t reserved_0_5
:6;
3289 uint64_t reserved_0_5
:6;
3291 uint64_t reserved_13_13
:1;
3292 uint64_t par_mode
:2;
3293 uint64_t reserved_16_20
:5;
3294 uint64_t use_ihdr
:1;
3295 uint64_t reserved_22_27
:6;
3296 uint64_t rskp_len
:7;
3297 uint64_t reserved_35_35
:1;
3298 uint64_t rparmode
:2;
3299 uint64_t reserved_38_42
:5;
3301 uint64_t reserved_44_63
:20;
3306 union cvmx_npei_pktx_slist_baddr
{
3308 struct cvmx_npei_pktx_slist_baddr_s
{
3309 #ifdef __BIG_ENDIAN_BITFIELD
3311 uint64_t reserved_0_3
:4;
3313 uint64_t reserved_0_3
:4;
3319 union cvmx_npei_pktx_slist_baoff_dbell
{
3321 struct cvmx_npei_pktx_slist_baoff_dbell_s
{
3322 #ifdef __BIG_ENDIAN_BITFIELD
3332 union cvmx_npei_pktx_slist_fifo_rsize
{
3334 struct cvmx_npei_pktx_slist_fifo_rsize_s
{
3335 #ifdef __BIG_ENDIAN_BITFIELD
3336 uint64_t reserved_32_63
:32;
3340 uint64_t reserved_32_63
:32;
3345 union cvmx_npei_pkt_cnt_int
{
3347 struct cvmx_npei_pkt_cnt_int_s
{
3348 #ifdef __BIG_ENDIAN_BITFIELD
3349 uint64_t reserved_32_63
:32;
3353 uint64_t reserved_32_63
:32;
3358 union cvmx_npei_pkt_cnt_int_enb
{
3360 struct cvmx_npei_pkt_cnt_int_enb_s
{
3361 #ifdef __BIG_ENDIAN_BITFIELD
3362 uint64_t reserved_32_63
:32;
3366 uint64_t reserved_32_63
:32;
3371 union cvmx_npei_pkt_data_out_es
{
3373 struct cvmx_npei_pkt_data_out_es_s
{
3374 #ifdef __BIG_ENDIAN_BITFIELD
3382 union cvmx_npei_pkt_data_out_ns
{
3384 struct cvmx_npei_pkt_data_out_ns_s
{
3385 #ifdef __BIG_ENDIAN_BITFIELD
3386 uint64_t reserved_32_63
:32;
3390 uint64_t reserved_32_63
:32;
3395 union cvmx_npei_pkt_data_out_ror
{
3397 struct cvmx_npei_pkt_data_out_ror_s
{
3398 #ifdef __BIG_ENDIAN_BITFIELD
3399 uint64_t reserved_32_63
:32;
3403 uint64_t reserved_32_63
:32;
3408 union cvmx_npei_pkt_dpaddr
{
3410 struct cvmx_npei_pkt_dpaddr_s
{
3411 #ifdef __BIG_ENDIAN_BITFIELD
3412 uint64_t reserved_32_63
:32;
3416 uint64_t reserved_32_63
:32;
3421 union cvmx_npei_pkt_in_bp
{
3423 struct cvmx_npei_pkt_in_bp_s
{
3424 #ifdef __BIG_ENDIAN_BITFIELD
3425 uint64_t reserved_32_63
:32;
3429 uint64_t reserved_32_63
:32;
3434 union cvmx_npei_pkt_in_donex_cnts
{
3436 struct cvmx_npei_pkt_in_donex_cnts_s
{
3437 #ifdef __BIG_ENDIAN_BITFIELD
3438 uint64_t reserved_32_63
:32;
3442 uint64_t reserved_32_63
:32;
3447 union cvmx_npei_pkt_in_instr_counts
{
3449 struct cvmx_npei_pkt_in_instr_counts_s
{
3450 #ifdef __BIG_ENDIAN_BITFIELD
3460 union cvmx_npei_pkt_in_pcie_port
{
3462 struct cvmx_npei_pkt_in_pcie_port_s
{
3463 #ifdef __BIG_ENDIAN_BITFIELD
3471 union cvmx_npei_pkt_input_control
{
3473 struct cvmx_npei_pkt_input_control_s
{
3474 #ifdef __BIG_ENDIAN_BITFIELD
3475 uint64_t reserved_23_63
:41;
3477 uint64_t pbp_dhi
:13;
3493 uint64_t pbp_dhi
:13;
3495 uint64_t reserved_23_63
:41;
3500 union cvmx_npei_pkt_instr_enb
{
3502 struct cvmx_npei_pkt_instr_enb_s
{
3503 #ifdef __BIG_ENDIAN_BITFIELD
3504 uint64_t reserved_32_63
:32;
3508 uint64_t reserved_32_63
:32;
3513 union cvmx_npei_pkt_instr_rd_size
{
3515 struct cvmx_npei_pkt_instr_rd_size_s
{
3516 #ifdef __BIG_ENDIAN_BITFIELD
3524 union cvmx_npei_pkt_instr_size
{
3526 struct cvmx_npei_pkt_instr_size_s
{
3527 #ifdef __BIG_ENDIAN_BITFIELD
3528 uint64_t reserved_32_63
:32;
3532 uint64_t reserved_32_63
:32;
3537 union cvmx_npei_pkt_int_levels
{
3539 struct cvmx_npei_pkt_int_levels_s
{
3540 #ifdef __BIG_ENDIAN_BITFIELD
3541 uint64_t reserved_54_63
:10;
3547 uint64_t reserved_54_63
:10;
3552 union cvmx_npei_pkt_iptr
{
3554 struct cvmx_npei_pkt_iptr_s
{
3555 #ifdef __BIG_ENDIAN_BITFIELD
3556 uint64_t reserved_32_63
:32;
3560 uint64_t reserved_32_63
:32;
3565 union cvmx_npei_pkt_out_bmode
{
3567 struct cvmx_npei_pkt_out_bmode_s
{
3568 #ifdef __BIG_ENDIAN_BITFIELD
3569 uint64_t reserved_32_63
:32;
3573 uint64_t reserved_32_63
:32;
3578 union cvmx_npei_pkt_out_enb
{
3580 struct cvmx_npei_pkt_out_enb_s
{
3581 #ifdef __BIG_ENDIAN_BITFIELD
3582 uint64_t reserved_32_63
:32;
3586 uint64_t reserved_32_63
:32;
3591 union cvmx_npei_pkt_output_wmark
{
3593 struct cvmx_npei_pkt_output_wmark_s
{
3594 #ifdef __BIG_ENDIAN_BITFIELD
3595 uint64_t reserved_32_63
:32;
3599 uint64_t reserved_32_63
:32;
3604 union cvmx_npei_pkt_pcie_port
{
3606 struct cvmx_npei_pkt_pcie_port_s
{
3607 #ifdef __BIG_ENDIAN_BITFIELD
3615 union cvmx_npei_pkt_port_in_rst
{
3617 struct cvmx_npei_pkt_port_in_rst_s
{
3618 #ifdef __BIG_ENDIAN_BITFIELD
3620 uint64_t out_rst
:32;
3622 uint64_t out_rst
:32;
3628 union cvmx_npei_pkt_slist_es
{
3630 struct cvmx_npei_pkt_slist_es_s
{
3631 #ifdef __BIG_ENDIAN_BITFIELD
3639 union cvmx_npei_pkt_slist_id_size
{
3641 struct cvmx_npei_pkt_slist_id_size_s
{
3642 #ifdef __BIG_ENDIAN_BITFIELD
3643 uint64_t reserved_23_63
:41;
3649 uint64_t reserved_23_63
:41;
3654 union cvmx_npei_pkt_slist_ns
{
3656 struct cvmx_npei_pkt_slist_ns_s
{
3657 #ifdef __BIG_ENDIAN_BITFIELD
3658 uint64_t reserved_32_63
:32;
3662 uint64_t reserved_32_63
:32;
3667 union cvmx_npei_pkt_slist_ror
{
3669 struct cvmx_npei_pkt_slist_ror_s
{
3670 #ifdef __BIG_ENDIAN_BITFIELD
3671 uint64_t reserved_32_63
:32;
3675 uint64_t reserved_32_63
:32;
3680 union cvmx_npei_pkt_time_int
{
3682 struct cvmx_npei_pkt_time_int_s
{
3683 #ifdef __BIG_ENDIAN_BITFIELD
3684 uint64_t reserved_32_63
:32;
3688 uint64_t reserved_32_63
:32;
3693 union cvmx_npei_pkt_time_int_enb
{
3695 struct cvmx_npei_pkt_time_int_enb_s
{
3696 #ifdef __BIG_ENDIAN_BITFIELD
3697 uint64_t reserved_32_63
:32;
3701 uint64_t reserved_32_63
:32;
3706 union cvmx_npei_rsl_int_blocks
{
3708 struct cvmx_npei_rsl_int_blocks_s
{
3709 #ifdef __BIG_ENDIAN_BITFIELD
3710 uint64_t reserved_31_63
:33;
3714 uint64_t reserved_24_27
:4;
3717 uint64_t reserved_21_21
:1;
3730 uint64_t reserved_8_8
:1;
3748 uint64_t reserved_8_8
:1;
3761 uint64_t reserved_21_21
:1;
3764 uint64_t reserved_24_27
:4;
3768 uint64_t reserved_31_63
:33;
3773 union cvmx_npei_scratch_1
{
3775 struct cvmx_npei_scratch_1_s
{
3776 #ifdef __BIG_ENDIAN_BITFIELD
3784 union cvmx_npei_state1
{
3786 struct cvmx_npei_state1_s
{
3787 #ifdef __BIG_ENDIAN_BITFIELD
3801 union cvmx_npei_state2
{
3803 struct cvmx_npei_state2_s
{
3804 #ifdef __BIG_ENDIAN_BITFIELD
3805 uint64_t reserved_48_63
:16;
3819 uint64_t reserved_48_63
:16;
3824 union cvmx_npei_state3
{
3826 struct cvmx_npei_state3_s
{
3827 #ifdef __BIG_ENDIAN_BITFIELD
3828 uint64_t reserved_56_63
:8;
3838 uint64_t reserved_56_63
:8;
3843 union cvmx_npei_win_rd_addr
{
3845 struct cvmx_npei_win_rd_addr_s
{
3846 #ifdef __BIG_ENDIAN_BITFIELD
3847 uint64_t reserved_51_63
:13;
3850 uint64_t rd_addr
:48;
3852 uint64_t rd_addr
:48;
3855 uint64_t reserved_51_63
:13;
3860 union cvmx_npei_win_rd_data
{
3862 struct cvmx_npei_win_rd_data_s
{
3863 #ifdef __BIG_ENDIAN_BITFIELD
3864 uint64_t rd_data
:64;
3866 uint64_t rd_data
:64;
3871 union cvmx_npei_win_wr_addr
{
3873 struct cvmx_npei_win_wr_addr_s
{
3874 #ifdef __BIG_ENDIAN_BITFIELD
3875 uint64_t reserved_49_63
:15;
3877 uint64_t wr_addr
:46;
3878 uint64_t reserved_0_1
:2;
3880 uint64_t reserved_0_1
:2;
3881 uint64_t wr_addr
:46;
3883 uint64_t reserved_49_63
:15;
3888 union cvmx_npei_win_wr_data
{
3890 struct cvmx_npei_win_wr_data_s
{
3891 #ifdef __BIG_ENDIAN_BITFIELD
3892 uint64_t wr_data
:64;
3894 uint64_t wr_data
:64;
3899 union cvmx_npei_win_wr_mask
{
3901 struct cvmx_npei_win_wr_mask_s
{
3902 #ifdef __BIG_ENDIAN_BITFIELD
3903 uint64_t reserved_8_63
:56;
3907 uint64_t reserved_8_63
:56;
3912 union cvmx_npei_window_ctl
{
3914 struct cvmx_npei_window_ctl_s
{
3915 #ifdef __BIG_ENDIAN_BITFIELD
3916 uint64_t reserved_32_63
:32;
3920 uint64_t reserved_32_63
:32;