arch/mips/include/asm/octeon/cvmx-pci-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_PCI_DEFS_H__
  29 #define __CVMX_PCI_DEFS_H__
  30
  31 #define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
  32 #define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
  33 #define CVMX_PCI_CFG00 (0x0000000000000000ull)
  34 #define CVMX_PCI_CFG01 (0x0000000000000004ull)
  35 #define CVMX_PCI_CFG02 (0x0000000000000008ull)
  36 #define CVMX_PCI_CFG03 (0x000000000000000Cull)
  37 #define CVMX_PCI_CFG04 (0x0000000000000010ull)
  38 #define CVMX_PCI_CFG05 (0x0000000000000014ull)
  39 #define CVMX_PCI_CFG06 (0x0000000000000018ull)
  40 #define CVMX_PCI_CFG07 (0x000000000000001Cull)
  41 #define CVMX_PCI_CFG08 (0x0000000000000020ull)
  42 #define CVMX_PCI_CFG09 (0x0000000000000024ull)
  43 #define CVMX_PCI_CFG10 (0x0000000000000028ull)
  44 #define CVMX_PCI_CFG11 (0x000000000000002Cull)
  45 #define CVMX_PCI_CFG12 (0x0000000000000030ull)
  46 #define CVMX_PCI_CFG13 (0x0000000000000034ull)
  47 #define CVMX_PCI_CFG15 (0x000000000000003Cull)
  48 #define CVMX_PCI_CFG16 (0x0000000000000040ull)
  49 #define CVMX_PCI_CFG17 (0x0000000000000044ull)
  50 #define CVMX_PCI_CFG18 (0x0000000000000048ull)
  51 #define CVMX_PCI_CFG19 (0x000000000000004Cull)
  52 #define CVMX_PCI_CFG20 (0x0000000000000050ull)
  53 #define CVMX_PCI_CFG21 (0x0000000000000054ull)
  54 #define CVMX_PCI_CFG22 (0x0000000000000058ull)
  55 #define CVMX_PCI_CFG56 (0x00000000000000E0ull)
  56 #define CVMX_PCI_CFG57 (0x00000000000000E4ull)
  57 #define CVMX_PCI_CFG58 (0x00000000000000E8ull)
  58 #define CVMX_PCI_CFG59 (0x00000000000000ECull)
  59 #define CVMX_PCI_CFG60 (0x00000000000000F0ull)
  60 #define CVMX_PCI_CFG61 (0x00000000000000F4ull)
  61 #define CVMX_PCI_CFG62 (0x00000000000000F8ull)
  62 #define CVMX_PCI_CFG63 (0x00000000000000FCull)
  63 #define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
  64 #define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
  65 #define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
  66 #define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
  67 #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
  68 #define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
  69 #define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
  70 #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
  71 #define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
  72 #define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
  73 #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
  74 #define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
  75 #define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
  76 #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
  77 #define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
  78 #define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
  79 #define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
  80 #define CVMX_PCI_INT_ENB (0x0000000000000038ull)
  81 #define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
  82 #define CVMX_PCI_INT_SUM (0x0000000000000030ull)
  83 #define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
  84 #define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
  85 #define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
  86 #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
  87 #define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
  88 #define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
  89 #define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
  90 #define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
  91 #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
  92 #define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
  93 #define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
  94 #define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
  95 #define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
  96 #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
  97 #define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
  98 #define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
  99 #define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
 100 #define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
 101 #define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
 102 #define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
 103 #define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
 104 #define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
 105 #define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
 106 #define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
 107 #define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
 108 #define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
 109 #define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
 110 #define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
 111 #define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
 112 #define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
 113 #define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
 114 #define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
 115 #define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
 116
 117 union cvmx_pci_bar1_indexx {
 118         uint32_t u32;
 119         struct cvmx_pci_bar1_indexx_s {
 120 #ifdef __BIG_ENDIAN_BITFIELD
 121                 uint32_t reserved_18_31:14;
 122                 uint32_t addr_idx:14;
 123                 uint32_t ca:1;
 124                 uint32_t end_swp:2;
 125                 uint32_t addr_v:1;
 126 #else
 127                 uint32_t addr_v:1;
 128                 uint32_t end_swp:2;
 129                 uint32_t ca:1;
 130                 uint32_t addr_idx:14;
 131                 uint32_t reserved_18_31:14;
 132 #endif
 133         } s;
 134 };
 135
 136 union cvmx_pci_bist_reg {
 137         uint64_t u64;
 138         struct cvmx_pci_bist_reg_s {
 139 #ifdef __BIG_ENDIAN_BITFIELD
 140                 uint64_t reserved_10_63:54;
 141                 uint64_t rsp_bs:1;
 142                 uint64_t dma0_bs:1;
 143                 uint64_t cmd0_bs:1;
 144                 uint64_t cmd_bs:1;
 145                 uint64_t csr2p_bs:1;
 146                 uint64_t csrr_bs:1;
 147                 uint64_t rsp2p_bs:1;
 148                 uint64_t csr2n_bs:1;
 149                 uint64_t dat2n_bs:1;
 150                 uint64_t dbg2n_bs:1;
 151 #else
 152                 uint64_t dbg2n_bs:1;
 153                 uint64_t dat2n_bs:1;
 154                 uint64_t csr2n_bs:1;
 155                 uint64_t rsp2p_bs:1;
 156                 uint64_t csrr_bs:1;
 157                 uint64_t csr2p_bs:1;
 158                 uint64_t cmd_bs:1;
 159                 uint64_t cmd0_bs:1;
 160                 uint64_t dma0_bs:1;
 161                 uint64_t rsp_bs:1;
 162                 uint64_t reserved_10_63:54;
 163 #endif
 164         } s;
 165 };
 166
 167 union cvmx_pci_cfg00 {
 168         uint32_t u32;
 169         struct cvmx_pci_cfg00_s {
 170 #ifdef __BIG_ENDIAN_BITFIELD
 171                 uint32_t devid:16;
 172                 uint32_t vendid:16;
 173 #else
 174                 uint32_t vendid:16;
 175                 uint32_t devid:16;
 176 #endif
 177         } s;
 178 };
 179
 180 union cvmx_pci_cfg01 {
 181         uint32_t u32;
 182         struct cvmx_pci_cfg01_s {
 183 #ifdef __BIG_ENDIAN_BITFIELD
 184                 uint32_t dpe:1;
 185                 uint32_t sse:1;
 186                 uint32_t rma:1;
 187                 uint32_t rta:1;
 188                 uint32_t sta:1;
 189                 uint32_t devt:2;
 190                 uint32_t mdpe:1;
 191                 uint32_t fbb:1;
 192                 uint32_t reserved_22_22:1;
 193                 uint32_t m66:1;
 194                 uint32_t cle:1;
 195                 uint32_t i_stat:1;
 196                 uint32_t reserved_11_18:8;
 197                 uint32_t i_dis:1;
 198                 uint32_t fbbe:1;
 199                 uint32_t see:1;
 200                 uint32_t ads:1;
 201                 uint32_t pee:1;
 202                 uint32_t vps:1;
 203                 uint32_t mwice:1;
 204                 uint32_t scse:1;
 205                 uint32_t me:1;
 206                 uint32_t msae:1;
 207                 uint32_t isae:1;
 208 #else
 209                 uint32_t isae:1;
 210                 uint32_t msae:1;
 211                 uint32_t me:1;
 212                 uint32_t scse:1;
 213                 uint32_t mwice:1;
 214                 uint32_t vps:1;
 215                 uint32_t pee:1;
 216                 uint32_t ads:1;
 217                 uint32_t see:1;
 218                 uint32_t fbbe:1;
 219                 uint32_t i_dis:1;
 220                 uint32_t reserved_11_18:8;
 221                 uint32_t i_stat:1;
 222                 uint32_t cle:1;
 223                 uint32_t m66:1;
 224                 uint32_t reserved_22_22:1;
 225                 uint32_t fbb:1;
 226                 uint32_t mdpe:1;
 227                 uint32_t devt:2;
 228                 uint32_t sta:1;
 229                 uint32_t rta:1;
 230                 uint32_t rma:1;
 231                 uint32_t sse:1;
 232                 uint32_t dpe:1;
 233 #endif
 234         } s;
 235 };
 236
 237 union cvmx_pci_cfg02 {
 238         uint32_t u32;
 239         struct cvmx_pci_cfg02_s {
 240 #ifdef __BIG_ENDIAN_BITFIELD
 241                 uint32_t cc:24;
 242                 uint32_t rid:8;
 243 #else
 244                 uint32_t rid:8;
 245                 uint32_t cc:24;
 246 #endif
 247         } s;
 248 };
 249
 250 union cvmx_pci_cfg03 {
 251         uint32_t u32;
 252         struct cvmx_pci_cfg03_s {
 253 #ifdef __BIG_ENDIAN_BITFIELD
 254                 uint32_t bcap:1;
 255                 uint32_t brb:1;
 256                 uint32_t reserved_28_29:2;
 257                 uint32_t bcod:4;
 258                 uint32_t ht:8;
 259                 uint32_t lt:8;
 260                 uint32_t cls:8;
 261 #else
 262                 uint32_t cls:8;
 263                 uint32_t lt:8;
 264                 uint32_t ht:8;
 265                 uint32_t bcod:4;
 266                 uint32_t reserved_28_29:2;
 267                 uint32_t brb:1;
 268                 uint32_t bcap:1;
 269 #endif
 270         } s;
 271 };
 272
 273 union cvmx_pci_cfg04 {
 274         uint32_t u32;
 275         struct cvmx_pci_cfg04_s {
 276 #ifdef __BIG_ENDIAN_BITFIELD
 277                 uint32_t lbase:20;
 278                 uint32_t lbasez:8;
 279                 uint32_t pf:1;
 280                 uint32_t typ:2;
 281                 uint32_t mspc:1;
 282 #else
 283                 uint32_t mspc:1;
 284                 uint32_t typ:2;
 285                 uint32_t pf:1;
 286                 uint32_t lbasez:8;
 287                 uint32_t lbase:20;
 288 #endif
 289         } s;
 290 };
 291
 292 union cvmx_pci_cfg05 {
 293         uint32_t u32;
 294         struct cvmx_pci_cfg05_s {
 295 #ifdef __BIG_ENDIAN_BITFIELD
 296                 uint32_t hbase:32;
 297 #else
 298                 uint32_t hbase:32;
 299 #endif
 300         } s;
 301 };
 302
 303 union cvmx_pci_cfg06 {
 304         uint32_t u32;
 305         struct cvmx_pci_cfg06_s {
 306 #ifdef __BIG_ENDIAN_BITFIELD
 307                 uint32_t lbase:5;
 308                 uint32_t lbasez:23;
 309                 uint32_t pf:1;
 310                 uint32_t typ:2;
 311                 uint32_t mspc:1;
 312 #else
 313                 uint32_t mspc:1;
 314                 uint32_t typ:2;
 315                 uint32_t pf:1;
 316                 uint32_t lbasez:23;
 317                 uint32_t lbase:5;
 318 #endif
 319         } s;
 320 };
 321
 322 union cvmx_pci_cfg07 {
 323         uint32_t u32;
 324         struct cvmx_pci_cfg07_s {
 325 #ifdef __BIG_ENDIAN_BITFIELD
 326                 uint32_t hbase:32;
 327 #else
 328                 uint32_t hbase:32;
 329 #endif
 330         } s;
 331 };
 332
 333 union cvmx_pci_cfg08 {
 334         uint32_t u32;
 335         struct cvmx_pci_cfg08_s {
 336 #ifdef __BIG_ENDIAN_BITFIELD
 337                 uint32_t lbasez:28;
 338                 uint32_t pf:1;
 339                 uint32_t typ:2;
 340                 uint32_t mspc:1;
 341 #else
 342                 uint32_t mspc:1;
 343                 uint32_t typ:2;
 344                 uint32_t pf:1;
 345                 uint32_t lbasez:28;
 346 #endif
 347         } s;
 348 };
 349
 350 union cvmx_pci_cfg09 {
 351         uint32_t u32;
 352         struct cvmx_pci_cfg09_s {
 353 #ifdef __BIG_ENDIAN_BITFIELD
 354                 uint32_t hbase:25;
 355                 uint32_t hbasez:7;
 356 #else
 357                 uint32_t hbasez:7;
 358                 uint32_t hbase:25;
 359 #endif
 360         } s;
 361 };
 362
 363 union cvmx_pci_cfg10 {
 364         uint32_t u32;
 365         struct cvmx_pci_cfg10_s {
 366 #ifdef __BIG_ENDIAN_BITFIELD
 367                 uint32_t cisp:32;
 368 #else
 369                 uint32_t cisp:32;
 370 #endif
 371         } s;
 372 };
 373
 374 union cvmx_pci_cfg11 {
 375         uint32_t u32;
 376         struct cvmx_pci_cfg11_s {
 377 #ifdef __BIG_ENDIAN_BITFIELD
 378                 uint32_t ssid:16;
 379                 uint32_t ssvid:16;
 380 #else
 381                 uint32_t ssvid:16;
 382                 uint32_t ssid:16;
 383 #endif
 384         } s;
 385 };
 386
 387 union cvmx_pci_cfg12 {
 388         uint32_t u32;
 389         struct cvmx_pci_cfg12_s {
 390 #ifdef __BIG_ENDIAN_BITFIELD
 391                 uint32_t erbar:16;
 392                 uint32_t erbarz:5;
 393                 uint32_t reserved_1_10:10;
 394                 uint32_t erbar_en:1;
 395 #else
 396                 uint32_t erbar_en:1;
 397                 uint32_t reserved_1_10:10;
 398                 uint32_t erbarz:5;
 399                 uint32_t erbar:16;
 400 #endif
 401         } s;
 402 };
 403
 404 union cvmx_pci_cfg13 {
 405         uint32_t u32;
 406         struct cvmx_pci_cfg13_s {
 407 #ifdef __BIG_ENDIAN_BITFIELD
 408                 uint32_t reserved_8_31:24;
 409                 uint32_t cp:8;
 410 #else
 411                 uint32_t cp:8;
 412                 uint32_t reserved_8_31:24;
 413 #endif
 414         } s;
 415 };
 416
 417 union cvmx_pci_cfg15 {
 418         uint32_t u32;
 419         struct cvmx_pci_cfg15_s {
 420 #ifdef __BIG_ENDIAN_BITFIELD
 421                 uint32_t ml:8;
 422                 uint32_t mg:8;
 423                 uint32_t inta:8;
 424                 uint32_t il:8;
 425 #else
 426                 uint32_t il:8;
 427                 uint32_t inta:8;
 428                 uint32_t mg:8;
 429                 uint32_t ml:8;
 430 #endif
 431         } s;
 432 };
 433
 434 union cvmx_pci_cfg16 {
 435         uint32_t u32;
 436         struct cvmx_pci_cfg16_s {
 437 #ifdef __BIG_ENDIAN_BITFIELD
 438                 uint32_t trdnpr:1;
 439                 uint32_t trdard:1;
 440                 uint32_t rdsati:1;
 441                 uint32_t trdrs:1;
 442                 uint32_t trtae:1;
 443                 uint32_t twsei:1;
 444                 uint32_t twsen:1;
 445                 uint32_t twtae:1;
 446                 uint32_t tmae:1;
 447                 uint32_t tslte:3;
 448                 uint32_t tilt:4;
 449                 uint32_t pbe:12;
 450                 uint32_t dppmr:1;
 451                 uint32_t reserved_2_2:1;
 452                 uint32_t tswc:1;
 453                 uint32_t mltd:1;
 454 #else
 455                 uint32_t mltd:1;
 456                 uint32_t tswc:1;
 457                 uint32_t reserved_2_2:1;
 458                 uint32_t dppmr:1;
 459                 uint32_t pbe:12;
 460                 uint32_t tilt:4;
 461                 uint32_t tslte:3;
 462                 uint32_t tmae:1;
 463                 uint32_t twtae:1;
 464                 uint32_t twsen:1;
 465                 uint32_t twsei:1;
 466                 uint32_t trtae:1;
 467                 uint32_t trdrs:1;
 468                 uint32_t rdsati:1;
 469                 uint32_t trdard:1;
 470                 uint32_t trdnpr:1;
 471 #endif
 472         } s;
 473 };
 474
 475 union cvmx_pci_cfg17 {
 476         uint32_t u32;
 477         struct cvmx_pci_cfg17_s {
 478 #ifdef __BIG_ENDIAN_BITFIELD
 479                 uint32_t tscme:32;
 480 #else
 481                 uint32_t tscme:32;
 482 #endif
 483         } s;
 484 };
 485
 486 union cvmx_pci_cfg18 {
 487         uint32_t u32;
 488         struct cvmx_pci_cfg18_s {
 489 #ifdef __BIG_ENDIAN_BITFIELD
 490                 uint32_t tdsrps:32;
 491 #else
 492                 uint32_t tdsrps:32;
 493 #endif
 494         } s;
 495 };
 496
 497 union cvmx_pci_cfg19 {
 498         uint32_t u32;
 499         struct cvmx_pci_cfg19_s {
 500 #ifdef __BIG_ENDIAN_BITFIELD
 501                 uint32_t mrbcm:1;
 502                 uint32_t mrbci:1;
 503                 uint32_t mdwe:1;
 504                 uint32_t mdre:1;
 505                 uint32_t mdrimc:1;
 506                 uint32_t mdrrmc:3;
 507                 uint32_t tmes:8;
 508                 uint32_t teci:1;
 509                 uint32_t tmei:1;
 510                 uint32_t tmse:1;
 511                 uint32_t tmdpes:1;
 512                 uint32_t tmapes:1;
 513                 uint32_t reserved_9_10:2;
 514                 uint32_t tibcd:1;
 515                 uint32_t tibde:1;
 516                 uint32_t reserved_6_6:1;
 517                 uint32_t tidomc:1;
 518                 uint32_t tdomc:5;
 519 #else
 520                 uint32_t tdomc:5;
 521                 uint32_t tidomc:1;
 522                 uint32_t reserved_6_6:1;
 523                 uint32_t tibde:1;
 524                 uint32_t tibcd:1;
 525                 uint32_t reserved_9_10:2;
 526                 uint32_t tmapes:1;
 527                 uint32_t tmdpes:1;
 528                 uint32_t tmse:1;
 529                 uint32_t tmei:1;
 530                 uint32_t teci:1;
 531                 uint32_t tmes:8;
 532                 uint32_t mdrrmc:3;
 533                 uint32_t mdrimc:1;
 534                 uint32_t mdre:1;
 535                 uint32_t mdwe:1;
 536                 uint32_t mrbci:1;
 537                 uint32_t mrbcm:1;
 538 #endif
 539         } s;
 540 };
 541
 542 union cvmx_pci_cfg20 {
 543         uint32_t u32;
 544         struct cvmx_pci_cfg20_s {
 545 #ifdef __BIG_ENDIAN_BITFIELD
 546                 uint32_t mdsp:32;
 547 #else
 548                 uint32_t mdsp:32;
 549 #endif
 550         } s;
 551 };
 552
 553 union cvmx_pci_cfg21 {
 554         uint32_t u32;
 555         struct cvmx_pci_cfg21_s {
 556 #ifdef __BIG_ENDIAN_BITFIELD
 557                 uint32_t scmre:32;
 558 #else
 559                 uint32_t scmre:32;
 560 #endif
 561         } s;
 562 };
 563
 564 union cvmx_pci_cfg22 {
 565         uint32_t u32;
 566         struct cvmx_pci_cfg22_s {
 567 #ifdef __BIG_ENDIAN_BITFIELD
 568                 uint32_t mac:7;
 569                 uint32_t reserved_19_24:6;
 570                 uint32_t flush:1;
 571                 uint32_t mra:1;
 572                 uint32_t mtta:1;
 573                 uint32_t mrv:8;
 574                 uint32_t mttv:8;
 575 #else
 576                 uint32_t mttv:8;
 577                 uint32_t mrv:8;
 578                 uint32_t mtta:1;
 579                 uint32_t mra:1;
 580                 uint32_t flush:1;
 581                 uint32_t reserved_19_24:6;
 582                 uint32_t mac:7;
 583 #endif
 584         } s;
 585 };
 586
 587 union cvmx_pci_cfg56 {
 588         uint32_t u32;
 589         struct cvmx_pci_cfg56_s {
 590 #ifdef __BIG_ENDIAN_BITFIELD
 591                 uint32_t reserved_23_31:9;
 592                 uint32_t most:3;
 593                 uint32_t mmbc:2;
 594                 uint32_t roe:1;
 595                 uint32_t dpere:1;
 596                 uint32_t ncp:8;
 597                 uint32_t pxcid:8;
 598 #else
 599                 uint32_t pxcid:8;
 600                 uint32_t ncp:8;
 601                 uint32_t dpere:1;
 602                 uint32_t roe:1;
 603                 uint32_t mmbc:2;
 604                 uint32_t most:3;
 605                 uint32_t reserved_23_31:9;
 606 #endif
 607         } s;
 608 };
 609
 610 union cvmx_pci_cfg57 {
 611         uint32_t u32;
 612         struct cvmx_pci_cfg57_s {
 613 #ifdef __BIG_ENDIAN_BITFIELD
 614                 uint32_t reserved_30_31:2;
 615                 uint32_t scemr:1;
 616                 uint32_t mcrsd:3;
 617                 uint32_t mostd:3;
 618                 uint32_t mmrbcd:2;
 619                 uint32_t dc:1;
 620                 uint32_t usc:1;
 621                 uint32_t scd:1;
 622                 uint32_t m133:1;
 623                 uint32_t w64:1;
 624                 uint32_t bn:8;
 625                 uint32_t dn:5;
 626                 uint32_t fn:3;
 627 #else
 628                 uint32_t fn:3;
 629                 uint32_t dn:5;
 630                 uint32_t bn:8;
 631                 uint32_t w64:1;
 632                 uint32_t m133:1;
 633                 uint32_t scd:1;
 634                 uint32_t usc:1;
 635                 uint32_t dc:1;
 636                 uint32_t mmrbcd:2;
 637                 uint32_t mostd:3;
 638                 uint32_t mcrsd:3;
 639                 uint32_t scemr:1;
 640                 uint32_t reserved_30_31:2;
 641 #endif
 642         } s;
 643 };
 644
 645 union cvmx_pci_cfg58 {
 646         uint32_t u32;
 647         struct cvmx_pci_cfg58_s {
 648 #ifdef __BIG_ENDIAN_BITFIELD
 649                 uint32_t pmes:5;
 650                 uint32_t d2s:1;
 651                 uint32_t d1s:1;
 652                 uint32_t auxc:3;
 653                 uint32_t dsi:1;
 654                 uint32_t reserved_20_20:1;
 655                 uint32_t pmec:1;
 656                 uint32_t pcimiv:3;
 657                 uint32_t ncp:8;
 658                 uint32_t pmcid:8;
 659 #else
 660                 uint32_t pmcid:8;
 661                 uint32_t ncp:8;
 662                 uint32_t pcimiv:3;
 663                 uint32_t pmec:1;
 664                 uint32_t reserved_20_20:1;
 665                 uint32_t dsi:1;
 666                 uint32_t auxc:3;
 667                 uint32_t d1s:1;
 668                 uint32_t d2s:1;
 669                 uint32_t pmes:5;
 670 #endif
 671         } s;
 672 };
 673
 674 union cvmx_pci_cfg59 {
 675         uint32_t u32;
 676         struct cvmx_pci_cfg59_s {
 677 #ifdef __BIG_ENDIAN_BITFIELD
 678                 uint32_t pmdia:8;
 679                 uint32_t bpccen:1;
 680                 uint32_t bd3h:1;
 681                 uint32_t reserved_16_21:6;
 682                 uint32_t pmess:1;
 683                 uint32_t pmedsia:2;
 684                 uint32_t pmds:4;
 685                 uint32_t pmeens:1;
 686                 uint32_t reserved_2_7:6;
 687                 uint32_t ps:2;
 688 #else
 689                 uint32_t ps:2;
 690                 uint32_t reserved_2_7:6;
 691                 uint32_t pmeens:1;
 692                 uint32_t pmds:4;
 693                 uint32_t pmedsia:2;
 694                 uint32_t pmess:1;
 695                 uint32_t reserved_16_21:6;
 696                 uint32_t bd3h:1;
 697                 uint32_t bpccen:1;
 698                 uint32_t pmdia:8;
 699 #endif
 700         } s;
 701 };
 702
 703 union cvmx_pci_cfg60 {
 704         uint32_t u32;
 705         struct cvmx_pci_cfg60_s {
 706 #ifdef __BIG_ENDIAN_BITFIELD
 707                 uint32_t reserved_24_31:8;
 708                 uint32_t m64:1;
 709                 uint32_t mme:3;
 710                 uint32_t mmc:3;
 711                 uint32_t msien:1;
 712                 uint32_t ncp:8;
 713                 uint32_t msicid:8;
 714 #else
 715                 uint32_t msicid:8;
 716                 uint32_t ncp:8;
 717                 uint32_t msien:1;
 718                 uint32_t mmc:3;
 719                 uint32_t mme:3;
 720                 uint32_t m64:1;
 721                 uint32_t reserved_24_31:8;
 722 #endif
 723         } s;
 724 };
 725
 726 union cvmx_pci_cfg61 {
 727         uint32_t u32;
 728         struct cvmx_pci_cfg61_s {
 729 #ifdef __BIG_ENDIAN_BITFIELD
 730                 uint32_t msi31t2:30;
 731                 uint32_t reserved_0_1:2;
 732 #else
 733                 uint32_t reserved_0_1:2;
 734                 uint32_t msi31t2:30;
 735 #endif
 736         } s;
 737 };
 738
 739 union cvmx_pci_cfg62 {
 740         uint32_t u32;
 741         struct cvmx_pci_cfg62_s {
 742 #ifdef __BIG_ENDIAN_BITFIELD
 743                 uint32_t msi:32;
 744 #else
 745                 uint32_t msi:32;
 746 #endif
 747         } s;
 748 };
 749
 750 union cvmx_pci_cfg63 {
 751         uint32_t u32;
 752         struct cvmx_pci_cfg63_s {
 753 #ifdef __BIG_ENDIAN_BITFIELD
 754                 uint32_t reserved_16_31:16;
 755                 uint32_t msimd:16;
 756 #else
 757                 uint32_t msimd:16;
 758                 uint32_t reserved_16_31:16;
 759 #endif
 760         } s;
 761 };
 762
 763 union cvmx_pci_cnt_reg {
 764         uint64_t u64;
 765         struct cvmx_pci_cnt_reg_s {
 766 #ifdef __BIG_ENDIAN_BITFIELD
 767                 uint64_t reserved_38_63:26;
 768                 uint64_t hm_pcix:1;
 769                 uint64_t hm_speed:2;
 770                 uint64_t ap_pcix:1;
 771                 uint64_t ap_speed:2;
 772                 uint64_t pcicnt:32;
 773 #else
 774                 uint64_t pcicnt:32;
 775                 uint64_t ap_speed:2;
 776                 uint64_t ap_pcix:1;
 777                 uint64_t hm_speed:2;
 778                 uint64_t hm_pcix:1;
 779                 uint64_t reserved_38_63:26;
 780 #endif
 781         } s;
 782 };
 783
 784 union cvmx_pci_ctl_status_2 {
 785         uint32_t u32;
 786         struct cvmx_pci_ctl_status_2_s {
 787 #ifdef __BIG_ENDIAN_BITFIELD
 788                 uint32_t reserved_29_31:3;
 789                 uint32_t bb1_hole:3;
 790                 uint32_t bb1_siz:1;
 791                 uint32_t bb_ca:1;
 792                 uint32_t bb_es:2;
 793                 uint32_t bb1:1;
 794                 uint32_t bb0:1;
 795                 uint32_t erst_n:1;
 796                 uint32_t bar2pres:1;
 797                 uint32_t scmtyp:1;
 798                 uint32_t scm:1;
 799                 uint32_t en_wfilt:1;
 800                 uint32_t reserved_14_14:1;
 801                 uint32_t ap_pcix:1;
 802                 uint32_t ap_64ad:1;
 803                 uint32_t b12_bist:1;
 804                 uint32_t pmo_amod:1;
 805                 uint32_t pmo_fpc:3;
 806                 uint32_t tsr_hwm:3;
 807                 uint32_t bar2_enb:1;
 808                 uint32_t bar2_esx:2;
 809                 uint32_t bar2_cax:1;
 810 #else
 811                 uint32_t bar2_cax:1;
 812                 uint32_t bar2_esx:2;
 813                 uint32_t bar2_enb:1;
 814                 uint32_t tsr_hwm:3;
 815                 uint32_t pmo_fpc:3;
 816                 uint32_t pmo_amod:1;
 817                 uint32_t b12_bist:1;
 818                 uint32_t ap_64ad:1;
 819                 uint32_t ap_pcix:1;
 820                 uint32_t reserved_14_14:1;
 821                 uint32_t en_wfilt:1;
 822                 uint32_t scm:1;
 823                 uint32_t scmtyp:1;
 824                 uint32_t bar2pres:1;
 825                 uint32_t erst_n:1;
 826                 uint32_t bb0:1;
 827                 uint32_t bb1:1;
 828                 uint32_t bb_es:2;
 829                 uint32_t bb_ca:1;
 830                 uint32_t bb1_siz:1;
 831                 uint32_t bb1_hole:3;
 832                 uint32_t reserved_29_31:3;
 833 #endif
 834         } s;
 835         struct cvmx_pci_ctl_status_2_cn31xx {
 836 #ifdef __BIG_ENDIAN_BITFIELD
 837                 uint32_t reserved_20_31:12;
 838                 uint32_t erst_n:1;
 839                 uint32_t bar2pres:1;
 840                 uint32_t scmtyp:1;
 841                 uint32_t scm:1;
 842                 uint32_t en_wfilt:1;
 843                 uint32_t reserved_14_14:1;
 844                 uint32_t ap_pcix:1;
 845                 uint32_t ap_64ad:1;
 846                 uint32_t b12_bist:1;
 847                 uint32_t pmo_amod:1;
 848                 uint32_t pmo_fpc:3;
 849                 uint32_t tsr_hwm:3;
 850                 uint32_t bar2_enb:1;
 851                 uint32_t bar2_esx:2;
 852                 uint32_t bar2_cax:1;
 853 #else
 854                 uint32_t bar2_cax:1;
 855                 uint32_t bar2_esx:2;
 856                 uint32_t bar2_enb:1;
 857                 uint32_t tsr_hwm:3;
 858                 uint32_t pmo_fpc:3;
 859                 uint32_t pmo_amod:1;
 860                 uint32_t b12_bist:1;
 861                 uint32_t ap_64ad:1;
 862                 uint32_t ap_pcix:1;
 863                 uint32_t reserved_14_14:1;
 864                 uint32_t en_wfilt:1;
 865                 uint32_t scm:1;
 866                 uint32_t scmtyp:1;
 867                 uint32_t bar2pres:1;
 868                 uint32_t erst_n:1;
 869                 uint32_t reserved_20_31:12;
 870 #endif
 871         } cn31xx;
 872 };
 873
 874 union cvmx_pci_dbellx {
 875         uint32_t u32;
 876         struct cvmx_pci_dbellx_s {
 877 #ifdef __BIG_ENDIAN_BITFIELD
 878                 uint32_t reserved_16_31:16;
 879                 uint32_t inc_val:16;
 880 #else
 881                 uint32_t inc_val:16;
 882                 uint32_t reserved_16_31:16;
 883 #endif
 884         } s;
 885 };
 886
 887 union cvmx_pci_dma_cntx {
 888         uint32_t u32;
 889         struct cvmx_pci_dma_cntx_s {
 890 #ifdef __BIG_ENDIAN_BITFIELD
 891                 uint32_t dma_cnt:32;
 892 #else
 893                 uint32_t dma_cnt:32;
 894 #endif
 895         } s;
 896 };
 897
 898 union cvmx_pci_dma_int_levx {
 899         uint32_t u32;
 900         struct cvmx_pci_dma_int_levx_s {
 901 #ifdef __BIG_ENDIAN_BITFIELD
 902                 uint32_t pkt_cnt:32;
 903 #else
 904                 uint32_t pkt_cnt:32;
 905 #endif
 906         } s;
 907 };
 908
 909 union cvmx_pci_dma_timex {
 910         uint32_t u32;
 911         struct cvmx_pci_dma_timex_s {
 912 #ifdef __BIG_ENDIAN_BITFIELD
 913                 uint32_t dma_time:32;
 914 #else
 915                 uint32_t dma_time:32;
 916 #endif
 917         } s;
 918 };
 919
 920 union cvmx_pci_instr_countx {
 921         uint32_t u32;
 922         struct cvmx_pci_instr_countx_s {
 923 #ifdef __BIG_ENDIAN_BITFIELD
 924                 uint32_t icnt:32;
 925 #else
 926                 uint32_t icnt:32;
 927 #endif
 928         } s;
 929 };
 930
 931 union cvmx_pci_int_enb {
 932         uint64_t u64;
 933         struct cvmx_pci_int_enb_s {
 934 #ifdef __BIG_ENDIAN_BITFIELD
 935                 uint64_t reserved_34_63:30;
 936                 uint64_t ill_rd:1;
 937                 uint64_t ill_wr:1;
 938                 uint64_t win_wr:1;
 939                 uint64_t dma1_fi:1;
 940                 uint64_t dma0_fi:1;
 941                 uint64_t idtime1:1;
 942                 uint64_t idtime0:1;
 943                 uint64_t idcnt1:1;
 944                 uint64_t idcnt0:1;
 945                 uint64_t iptime3:1;
 946                 uint64_t iptime2:1;
 947                 uint64_t iptime1:1;
 948                 uint64_t iptime0:1;
 949                 uint64_t ipcnt3:1;
 950                 uint64_t ipcnt2:1;
 951                 uint64_t ipcnt1:1;
 952                 uint64_t ipcnt0:1;
 953                 uint64_t irsl_int:1;
 954                 uint64_t ill_rrd:1;
 955                 uint64_t ill_rwr:1;
 956                 uint64_t idperr:1;
 957                 uint64_t iaperr:1;
 958                 uint64_t iserr:1;
 959                 uint64_t itsr_abt:1;
 960                 uint64_t imsc_msg:1;
 961                 uint64_t imsi_mabt:1;
 962                 uint64_t imsi_tabt:1;
 963                 uint64_t imsi_per:1;
 964                 uint64_t imr_tto:1;
 965                 uint64_t imr_abt:1;
 966                 uint64_t itr_abt:1;
 967                 uint64_t imr_wtto:1;
 968                 uint64_t imr_wabt:1;
 969                 uint64_t itr_wabt:1;
 970 #else
 971                 uint64_t itr_wabt:1;
 972                 uint64_t imr_wabt:1;
 973                 uint64_t imr_wtto:1;
 974                 uint64_t itr_abt:1;
 975                 uint64_t imr_abt:1;
 976                 uint64_t imr_tto:1;
 977                 uint64_t imsi_per:1;
 978                 uint64_t imsi_tabt:1;
 979                 uint64_t imsi_mabt:1;
 980                 uint64_t imsc_msg:1;
 981                 uint64_t itsr_abt:1;
 982                 uint64_t iserr:1;
 983                 uint64_t iaperr:1;
 984                 uint64_t idperr:1;
 985                 uint64_t ill_rwr:1;
 986                 uint64_t ill_rrd:1;
 987                 uint64_t irsl_int:1;
 988                 uint64_t ipcnt0:1;
 989                 uint64_t ipcnt1:1;
 990                 uint64_t ipcnt2:1;
 991                 uint64_t ipcnt3:1;
 992                 uint64_t iptime0:1;
 993                 uint64_t iptime1:1;
 994                 uint64_t iptime2:1;
 995                 uint64_t iptime3:1;
 996                 uint64_t idcnt0:1;
 997                 uint64_t idcnt1:1;
 998                 uint64_t idtime0:1;
 999                 uint64_t idtime1:1;
1000                 uint64_t dma0_fi:1;
1001                 uint64_t dma1_fi:1;
1002                 uint64_t win_wr:1;
1003                 uint64_t ill_wr:1;
1004                 uint64_t ill_rd:1;
1005                 uint64_t reserved_34_63:30;
1006 #endif
1007         } s;
1008         struct cvmx_pci_int_enb_cn30xx {
1009 #ifdef __BIG_ENDIAN_BITFIELD
1010                 uint64_t reserved_34_63:30;
1011                 uint64_t ill_rd:1;
1012                 uint64_t ill_wr:1;
1013                 uint64_t win_wr:1;
1014                 uint64_t dma1_fi:1;
1015                 uint64_t dma0_fi:1;
1016                 uint64_t idtime1:1;
1017                 uint64_t idtime0:1;
1018                 uint64_t idcnt1:1;
1019                 uint64_t idcnt0:1;
1020                 uint64_t reserved_22_24:3;
1021                 uint64_t iptime0:1;
1022                 uint64_t reserved_18_20:3;
1023                 uint64_t ipcnt0:1;
1024                 uint64_t irsl_int:1;
1025                 uint64_t ill_rrd:1;
1026                 uint64_t ill_rwr:1;
1027                 uint64_t idperr:1;
1028                 uint64_t iaperr:1;
1029                 uint64_t iserr:1;
1030                 uint64_t itsr_abt:1;
1031                 uint64_t imsc_msg:1;
1032                 uint64_t imsi_mabt:1;
1033                 uint64_t imsi_tabt:1;
1034                 uint64_t imsi_per:1;
1035                 uint64_t imr_tto:1;
1036                 uint64_t imr_abt:1;
1037                 uint64_t itr_abt:1;
1038                 uint64_t imr_wtto:1;
1039                 uint64_t imr_wabt:1;
1040                 uint64_t itr_wabt:1;
1041 #else
1042                 uint64_t itr_wabt:1;
1043                 uint64_t imr_wabt:1;
1044                 uint64_t imr_wtto:1;
1045                 uint64_t itr_abt:1;
1046                 uint64_t imr_abt:1;
1047                 uint64_t imr_tto:1;
1048                 uint64_t imsi_per:1;
1049                 uint64_t imsi_tabt:1;
1050                 uint64_t imsi_mabt:1;
1051                 uint64_t imsc_msg:1;
1052                 uint64_t itsr_abt:1;
1053                 uint64_t iserr:1;
1054                 uint64_t iaperr:1;
1055                 uint64_t idperr:1;
1056                 uint64_t ill_rwr:1;
1057                 uint64_t ill_rrd:1;
1058                 uint64_t irsl_int:1;
1059                 uint64_t ipcnt0:1;
1060                 uint64_t reserved_18_20:3;
1061                 uint64_t iptime0:1;
1062                 uint64_t reserved_22_24:3;
1063                 uint64_t idcnt0:1;
1064                 uint64_t idcnt1:1;
1065                 uint64_t idtime0:1;
1066                 uint64_t idtime1:1;
1067                 uint64_t dma0_fi:1;
1068                 uint64_t dma1_fi:1;
1069                 uint64_t win_wr:1;
1070                 uint64_t ill_wr:1;
1071                 uint64_t ill_rd:1;
1072                 uint64_t reserved_34_63:30;
1073 #endif
1074         } cn30xx;
1075         struct cvmx_pci_int_enb_cn31xx {
1076 #ifdef __BIG_ENDIAN_BITFIELD
1077                 uint64_t reserved_34_63:30;
1078                 uint64_t ill_rd:1;
1079                 uint64_t ill_wr:1;
1080                 uint64_t win_wr:1;
1081                 uint64_t dma1_fi:1;
1082                 uint64_t dma0_fi:1;
1083                 uint64_t idtime1:1;
1084                 uint64_t idtime0:1;
1085                 uint64_t idcnt1:1;
1086                 uint64_t idcnt0:1;
1087                 uint64_t reserved_23_24:2;
1088                 uint64_t iptime1:1;
1089                 uint64_t iptime0:1;
1090                 uint64_t reserved_19_20:2;
1091                 uint64_t ipcnt1:1;
1092                 uint64_t ipcnt0:1;
1093                 uint64_t irsl_int:1;
1094                 uint64_t ill_rrd:1;
1095                 uint64_t ill_rwr:1;
1096                 uint64_t idperr:1;
1097                 uint64_t iaperr:1;
1098                 uint64_t iserr:1;
1099                 uint64_t itsr_abt:1;
1100                 uint64_t imsc_msg:1;
1101                 uint64_t imsi_mabt:1;
1102                 uint64_t imsi_tabt:1;
1103                 uint64_t imsi_per:1;
1104                 uint64_t imr_tto:1;
1105                 uint64_t imr_abt:1;
1106                 uint64_t itr_abt:1;
1107                 uint64_t imr_wtto:1;
1108                 uint64_t imr_wabt:1;
1109                 uint64_t itr_wabt:1;
1110 #else
1111                 uint64_t itr_wabt:1;
1112                 uint64_t imr_wabt:1;
1113                 uint64_t imr_wtto:1;
1114                 uint64_t itr_abt:1;
1115                 uint64_t imr_abt:1;
1116                 uint64_t imr_tto:1;
1117                 uint64_t imsi_per:1;
1118                 uint64_t imsi_tabt:1;
1119                 uint64_t imsi_mabt:1;
1120                 uint64_t imsc_msg:1;
1121                 uint64_t itsr_abt:1;
1122                 uint64_t iserr:1;
1123                 uint64_t iaperr:1;
1124                 uint64_t idperr:1;
1125                 uint64_t ill_rwr:1;
1126                 uint64_t ill_rrd:1;
1127                 uint64_t irsl_int:1;
1128                 uint64_t ipcnt0:1;
1129                 uint64_t ipcnt1:1;
1130                 uint64_t reserved_19_20:2;
1131                 uint64_t iptime0:1;
1132                 uint64_t iptime1:1;
1133                 uint64_t reserved_23_24:2;
1134                 uint64_t idcnt0:1;
1135                 uint64_t idcnt1:1;
1136                 uint64_t idtime0:1;
1137                 uint64_t idtime1:1;
1138                 uint64_t dma0_fi:1;
1139                 uint64_t dma1_fi:1;
1140                 uint64_t win_wr:1;
1141                 uint64_t ill_wr:1;
1142                 uint64_t ill_rd:1;
1143                 uint64_t reserved_34_63:30;
1144 #endif
1145         } cn31xx;
1146 };
1147
1148 union cvmx_pci_int_enb2 {
1149         uint64_t u64;
1150         struct cvmx_pci_int_enb2_s {
1151 #ifdef __BIG_ENDIAN_BITFIELD
1152                 uint64_t reserved_34_63:30;
1153                 uint64_t ill_rd:1;
1154                 uint64_t ill_wr:1;
1155                 uint64_t win_wr:1;
1156                 uint64_t dma1_fi:1;
1157                 uint64_t dma0_fi:1;
1158                 uint64_t rdtime1:1;
1159                 uint64_t rdtime0:1;
1160                 uint64_t rdcnt1:1;
1161                 uint64_t rdcnt0:1;
1162                 uint64_t rptime3:1;
1163                 uint64_t rptime2:1;
1164                 uint64_t rptime1:1;
1165                 uint64_t rptime0:1;
1166                 uint64_t rpcnt3:1;
1167                 uint64_t rpcnt2:1;
1168                 uint64_t rpcnt1:1;
1169                 uint64_t rpcnt0:1;
1170                 uint64_t rrsl_int:1;
1171                 uint64_t ill_rrd:1;
1172                 uint64_t ill_rwr:1;
1173                 uint64_t rdperr:1;
1174                 uint64_t raperr:1;
1175                 uint64_t rserr:1;
1176                 uint64_t rtsr_abt:1;
1177                 uint64_t rmsc_msg:1;
1178                 uint64_t rmsi_mabt:1;
1179                 uint64_t rmsi_tabt:1;
1180                 uint64_t rmsi_per:1;
1181                 uint64_t rmr_tto:1;
1182                 uint64_t rmr_abt:1;
1183                 uint64_t rtr_abt:1;
1184                 uint64_t rmr_wtto:1;
1185                 uint64_t rmr_wabt:1;
1186                 uint64_t rtr_wabt:1;
1187 #else
1188                 uint64_t rtr_wabt:1;
1189                 uint64_t rmr_wabt:1;
1190                 uint64_t rmr_wtto:1;
1191                 uint64_t rtr_abt:1;
1192                 uint64_t rmr_abt:1;
1193                 uint64_t rmr_tto:1;
1194                 uint64_t rmsi_per:1;
1195                 uint64_t rmsi_tabt:1;
1196                 uint64_t rmsi_mabt:1;
1197                 uint64_t rmsc_msg:1;
1198                 uint64_t rtsr_abt:1;
1199                 uint64_t rserr:1;
1200                 uint64_t raperr:1;
1201                 uint64_t rdperr:1;
1202                 uint64_t ill_rwr:1;
1203                 uint64_t ill_rrd:1;
1204                 uint64_t rrsl_int:1;
1205                 uint64_t rpcnt0:1;
1206                 uint64_t rpcnt1:1;
1207                 uint64_t rpcnt2:1;
1208                 uint64_t rpcnt3:1;
1209                 uint64_t rptime0:1;
1210                 uint64_t rptime1:1;
1211                 uint64_t rptime2:1;
1212                 uint64_t rptime3:1;
1213                 uint64_t rdcnt0:1;
1214                 uint64_t rdcnt1:1;
1215                 uint64_t rdtime0:1;
1216                 uint64_t rdtime1:1;
1217                 uint64_t dma0_fi:1;
1218                 uint64_t dma1_fi:1;
1219                 uint64_t win_wr:1;
1220                 uint64_t ill_wr:1;
1221                 uint64_t ill_rd:1;
1222                 uint64_t reserved_34_63:30;
1223 #endif
1224         } s;
1225         struct cvmx_pci_int_enb2_cn30xx {
1226 #ifdef __BIG_ENDIAN_BITFIELD
1227                 uint64_t reserved_34_63:30;
1228                 uint64_t ill_rd:1;
1229                 uint64_t ill_wr:1;
1230                 uint64_t win_wr:1;
1231                 uint64_t dma1_fi:1;
1232                 uint64_t dma0_fi:1;
1233                 uint64_t rdtime1:1;
1234                 uint64_t rdtime0:1;
1235                 uint64_t rdcnt1:1;
1236                 uint64_t rdcnt0:1;
1237                 uint64_t reserved_22_24:3;
1238                 uint64_t rptime0:1;
1239                 uint64_t reserved_18_20:3;
1240                 uint64_t rpcnt0:1;
1241                 uint64_t rrsl_int:1;
1242                 uint64_t ill_rrd:1;
1243                 uint64_t ill_rwr:1;
1244                 uint64_t rdperr:1;
1245                 uint64_t raperr:1;
1246                 uint64_t rserr:1;
1247                 uint64_t rtsr_abt:1;
1248                 uint64_t rmsc_msg:1;
1249                 uint64_t rmsi_mabt:1;
1250                 uint64_t rmsi_tabt:1;
1251                 uint64_t rmsi_per:1;
1252                 uint64_t rmr_tto:1;
1253                 uint64_t rmr_abt:1;
1254                 uint64_t rtr_abt:1;
1255                 uint64_t rmr_wtto:1;
1256                 uint64_t rmr_wabt:1;
1257                 uint64_t rtr_wabt:1;
1258 #else
1259                 uint64_t rtr_wabt:1;
1260                 uint64_t rmr_wabt:1;
1261                 uint64_t rmr_wtto:1;
1262                 uint64_t rtr_abt:1;
1263                 uint64_t rmr_abt:1;
1264                 uint64_t rmr_tto:1;
1265                 uint64_t rmsi_per:1;
1266                 uint64_t rmsi_tabt:1;
1267                 uint64_t rmsi_mabt:1;
1268                 uint64_t rmsc_msg:1;
1269                 uint64_t rtsr_abt:1;
1270                 uint64_t rserr:1;
1271                 uint64_t raperr:1;
1272                 uint64_t rdperr:1;
1273                 uint64_t ill_rwr:1;
1274                 uint64_t ill_rrd:1;
1275                 uint64_t rrsl_int:1;
1276                 uint64_t rpcnt0:1;
1277                 uint64_t reserved_18_20:3;
1278                 uint64_t rptime0:1;
1279                 uint64_t reserved_22_24:3;
1280                 uint64_t rdcnt0:1;
1281                 uint64_t rdcnt1:1;
1282                 uint64_t rdtime0:1;
1283                 uint64_t rdtime1:1;
1284                 uint64_t dma0_fi:1;
1285                 uint64_t dma1_fi:1;
1286                 uint64_t win_wr:1;
1287                 uint64_t ill_wr:1;
1288                 uint64_t ill_rd:1;
1289                 uint64_t reserved_34_63:30;
1290 #endif
1291         } cn30xx;
1292         struct cvmx_pci_int_enb2_cn31xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294                 uint64_t reserved_34_63:30;
1295                 uint64_t ill_rd:1;
1296                 uint64_t ill_wr:1;
1297                 uint64_t win_wr:1;
1298                 uint64_t dma1_fi:1;
1299                 uint64_t dma0_fi:1;
1300                 uint64_t rdtime1:1;
1301                 uint64_t rdtime0:1;
1302                 uint64_t rdcnt1:1;
1303                 uint64_t rdcnt0:1;
1304                 uint64_t reserved_23_24:2;
1305                 uint64_t rptime1:1;
1306                 uint64_t rptime0:1;
1307                 uint64_t reserved_19_20:2;
1308                 uint64_t rpcnt1:1;
1309                 uint64_t rpcnt0:1;
1310                 uint64_t rrsl_int:1;
1311                 uint64_t ill_rrd:1;
1312                 uint64_t ill_rwr:1;
1313                 uint64_t rdperr:1;
1314                 uint64_t raperr:1;
1315                 uint64_t rserr:1;
1316                 uint64_t rtsr_abt:1;
1317                 uint64_t rmsc_msg:1;
1318                 uint64_t rmsi_mabt:1;
1319                 uint64_t rmsi_tabt:1;
1320                 uint64_t rmsi_per:1;
1321                 uint64_t rmr_tto:1;
1322                 uint64_t rmr_abt:1;
1323                 uint64_t rtr_abt:1;
1324                 uint64_t rmr_wtto:1;
1325                 uint64_t rmr_wabt:1;
1326                 uint64_t rtr_wabt:1;
1327 #else
1328                 uint64_t rtr_wabt:1;
1329                 uint64_t rmr_wabt:1;
1330                 uint64_t rmr_wtto:1;
1331                 uint64_t rtr_abt:1;
1332                 uint64_t rmr_abt:1;
1333                 uint64_t rmr_tto:1;
1334                 uint64_t rmsi_per:1;
1335                 uint64_t rmsi_tabt:1;
1336                 uint64_t rmsi_mabt:1;
1337                 uint64_t rmsc_msg:1;
1338                 uint64_t rtsr_abt:1;
1339                 uint64_t rserr:1;
1340                 uint64_t raperr:1;
1341                 uint64_t rdperr:1;
1342                 uint64_t ill_rwr:1;
1343                 uint64_t ill_rrd:1;
1344                 uint64_t rrsl_int:1;
1345                 uint64_t rpcnt0:1;
1346                 uint64_t rpcnt1:1;
1347                 uint64_t reserved_19_20:2;
1348                 uint64_t rptime0:1;
1349                 uint64_t rptime1:1;
1350                 uint64_t reserved_23_24:2;
1351                 uint64_t rdcnt0:1;
1352                 uint64_t rdcnt1:1;
1353                 uint64_t rdtime0:1;
1354                 uint64_t rdtime1:1;
1355                 uint64_t dma0_fi:1;
1356                 uint64_t dma1_fi:1;
1357                 uint64_t win_wr:1;
1358                 uint64_t ill_wr:1;
1359                 uint64_t ill_rd:1;
1360                 uint64_t reserved_34_63:30;
1361 #endif
1362         } cn31xx;
1363 };
1364
1365 union cvmx_pci_int_sum {
1366         uint64_t u64;
1367         struct cvmx_pci_int_sum_s {
1368 #ifdef __BIG_ENDIAN_BITFIELD
1369                 uint64_t reserved_34_63:30;
1370                 uint64_t ill_rd:1;
1371                 uint64_t ill_wr:1;
1372                 uint64_t win_wr:1;
1373                 uint64_t dma1_fi:1;
1374                 uint64_t dma0_fi:1;
1375                 uint64_t dtime1:1;
1376                 uint64_t dtime0:1;
1377                 uint64_t dcnt1:1;
1378                 uint64_t dcnt0:1;
1379                 uint64_t ptime3:1;
1380                 uint64_t ptime2:1;
1381                 uint64_t ptime1:1;
1382                 uint64_t ptime0:1;
1383                 uint64_t pcnt3:1;
1384                 uint64_t pcnt2:1;
1385                 uint64_t pcnt1:1;
1386                 uint64_t pcnt0:1;
1387                 uint64_t rsl_int:1;
1388                 uint64_t ill_rrd:1;
1389                 uint64_t ill_rwr:1;
1390                 uint64_t dperr:1;
1391                 uint64_t aperr:1;
1392                 uint64_t serr:1;
1393                 uint64_t tsr_abt:1;
1394                 uint64_t msc_msg:1;
1395                 uint64_t msi_mabt:1;
1396                 uint64_t msi_tabt:1;
1397                 uint64_t msi_per:1;
1398                 uint64_t mr_tto:1;
1399                 uint64_t mr_abt:1;
1400                 uint64_t tr_abt:1;
1401                 uint64_t mr_wtto:1;
1402                 uint64_t mr_wabt:1;
1403                 uint64_t tr_wabt:1;
1404 #else
1405                 uint64_t tr_wabt:1;
1406                 uint64_t mr_wabt:1;
1407                 uint64_t mr_wtto:1;
1408                 uint64_t tr_abt:1;
1409                 uint64_t mr_abt:1;
1410                 uint64_t mr_tto:1;
1411                 uint64_t msi_per:1;
1412                 uint64_t msi_tabt:1;
1413                 uint64_t msi_mabt:1;
1414                 uint64_t msc_msg:1;
1415                 uint64_t tsr_abt:1;
1416                 uint64_t serr:1;
1417                 uint64_t aperr:1;
1418                 uint64_t dperr:1;
1419                 uint64_t ill_rwr:1;
1420                 uint64_t ill_rrd:1;
1421                 uint64_t rsl_int:1;
1422                 uint64_t pcnt0:1;
1423                 uint64_t pcnt1:1;
1424                 uint64_t pcnt2:1;
1425                 uint64_t pcnt3:1;
1426                 uint64_t ptime0:1;
1427                 uint64_t ptime1:1;
1428                 uint64_t ptime2:1;
1429                 uint64_t ptime3:1;
1430                 uint64_t dcnt0:1;
1431                 uint64_t dcnt1:1;
1432                 uint64_t dtime0:1;
1433                 uint64_t dtime1:1;
1434                 uint64_t dma0_fi:1;
1435                 uint64_t dma1_fi:1;
1436                 uint64_t win_wr:1;
1437                 uint64_t ill_wr:1;
1438                 uint64_t ill_rd:1;
1439                 uint64_t reserved_34_63:30;
1440 #endif
1441         } s;
1442         struct cvmx_pci_int_sum_cn30xx {
1443 #ifdef __BIG_ENDIAN_BITFIELD
1444                 uint64_t reserved_34_63:30;
1445                 uint64_t ill_rd:1;
1446                 uint64_t ill_wr:1;
1447                 uint64_t win_wr:1;
1448                 uint64_t dma1_fi:1;
1449                 uint64_t dma0_fi:1;
1450                 uint64_t dtime1:1;
1451                 uint64_t dtime0:1;
1452                 uint64_t dcnt1:1;
1453                 uint64_t dcnt0:1;
1454                 uint64_t reserved_22_24:3;
1455                 uint64_t ptime0:1;
1456                 uint64_t reserved_18_20:3;
1457                 uint64_t pcnt0:1;
1458                 uint64_t rsl_int:1;
1459                 uint64_t ill_rrd:1;
1460                 uint64_t ill_rwr:1;
1461                 uint64_t dperr:1;
1462                 uint64_t aperr:1;
1463                 uint64_t serr:1;
1464                 uint64_t tsr_abt:1;
1465                 uint64_t msc_msg:1;
1466                 uint64_t msi_mabt:1;
1467                 uint64_t msi_tabt:1;
1468                 uint64_t msi_per:1;
1469                 uint64_t mr_tto:1;
1470                 uint64_t mr_abt:1;
1471                 uint64_t tr_abt:1;
1472                 uint64_t mr_wtto:1;
1473                 uint64_t mr_wabt:1;
1474                 uint64_t tr_wabt:1;
1475 #else
1476                 uint64_t tr_wabt:1;
1477                 uint64_t mr_wabt:1;
1478                 uint64_t mr_wtto:1;
1479                 uint64_t tr_abt:1;
1480                 uint64_t mr_abt:1;
1481                 uint64_t mr_tto:1;
1482                 uint64_t msi_per:1;
1483                 uint64_t msi_tabt:1;
1484                 uint64_t msi_mabt:1;
1485                 uint64_t msc_msg:1;
1486                 uint64_t tsr_abt:1;
1487                 uint64_t serr:1;
1488                 uint64_t aperr:1;
1489                 uint64_t dperr:1;
1490                 uint64_t ill_rwr:1;
1491                 uint64_t ill_rrd:1;
1492                 uint64_t rsl_int:1;
1493                 uint64_t pcnt0:1;
1494                 uint64_t reserved_18_20:3;
1495                 uint64_t ptime0:1;
1496                 uint64_t reserved_22_24:3;
1497                 uint64_t dcnt0:1;
1498                 uint64_t dcnt1:1;
1499                 uint64_t dtime0:1;
1500                 uint64_t dtime1:1;
1501                 uint64_t dma0_fi:1;
1502                 uint64_t dma1_fi:1;
1503                 uint64_t win_wr:1;
1504                 uint64_t ill_wr:1;
1505                 uint64_t ill_rd:1;
1506                 uint64_t reserved_34_63:30;
1507 #endif
1508         } cn30xx;
1509         struct cvmx_pci_int_sum_cn31xx {
1510 #ifdef __BIG_ENDIAN_BITFIELD
1511                 uint64_t reserved_34_63:30;
1512                 uint64_t ill_rd:1;
1513                 uint64_t ill_wr:1;
1514                 uint64_t win_wr:1;
1515                 uint64_t dma1_fi:1;
1516                 uint64_t dma0_fi:1;
1517                 uint64_t dtime1:1;
1518                 uint64_t dtime0:1;
1519                 uint64_t dcnt1:1;
1520                 uint64_t dcnt0:1;
1521                 uint64_t reserved_23_24:2;
1522                 uint64_t ptime1:1;
1523                 uint64_t ptime0:1;
1524                 uint64_t reserved_19_20:2;
1525                 uint64_t pcnt1:1;
1526                 uint64_t pcnt0:1;
1527                 uint64_t rsl_int:1;
1528                 uint64_t ill_rrd:1;
1529                 uint64_t ill_rwr:1;
1530                 uint64_t dperr:1;
1531                 uint64_t aperr:1;
1532                 uint64_t serr:1;
1533                 uint64_t tsr_abt:1;
1534                 uint64_t msc_msg:1;
1535                 uint64_t msi_mabt:1;
1536                 uint64_t msi_tabt:1;
1537                 uint64_t msi_per:1;
1538                 uint64_t mr_tto:1;
1539                 uint64_t mr_abt:1;
1540                 uint64_t tr_abt:1;
1541                 uint64_t mr_wtto:1;
1542                 uint64_t mr_wabt:1;
1543                 uint64_t tr_wabt:1;
1544 #else
1545                 uint64_t tr_wabt:1;
1546                 uint64_t mr_wabt:1;
1547                 uint64_t mr_wtto:1;
1548                 uint64_t tr_abt:1;
1549                 uint64_t mr_abt:1;
1550                 uint64_t mr_tto:1;
1551                 uint64_t msi_per:1;
1552                 uint64_t msi_tabt:1;
1553                 uint64_t msi_mabt:1;
1554                 uint64_t msc_msg:1;
1555                 uint64_t tsr_abt:1;
1556                 uint64_t serr:1;
1557                 uint64_t aperr:1;
1558                 uint64_t dperr:1;
1559                 uint64_t ill_rwr:1;
1560                 uint64_t ill_rrd:1;
1561                 uint64_t rsl_int:1;
1562                 uint64_t pcnt0:1;
1563                 uint64_t pcnt1:1;
1564                 uint64_t reserved_19_20:2;
1565                 uint64_t ptime0:1;
1566                 uint64_t ptime1:1;
1567                 uint64_t reserved_23_24:2;
1568                 uint64_t dcnt0:1;
1569                 uint64_t dcnt1:1;
1570                 uint64_t dtime0:1;
1571                 uint64_t dtime1:1;
1572                 uint64_t dma0_fi:1;
1573                 uint64_t dma1_fi:1;
1574                 uint64_t win_wr:1;
1575                 uint64_t ill_wr:1;
1576                 uint64_t ill_rd:1;
1577                 uint64_t reserved_34_63:30;
1578 #endif
1579         } cn31xx;
1580 };
1581
1582 union cvmx_pci_int_sum2 {
1583         uint64_t u64;
1584         struct cvmx_pci_int_sum2_s {
1585 #ifdef __BIG_ENDIAN_BITFIELD
1586                 uint64_t reserved_34_63:30;
1587                 uint64_t ill_rd:1;
1588                 uint64_t ill_wr:1;
1589                 uint64_t win_wr:1;
1590                 uint64_t dma1_fi:1;
1591                 uint64_t dma0_fi:1;
1592                 uint64_t dtime1:1;
1593                 uint64_t dtime0:1;
1594                 uint64_t dcnt1:1;
1595                 uint64_t dcnt0:1;
1596                 uint64_t ptime3:1;
1597                 uint64_t ptime2:1;
1598                 uint64_t ptime1:1;
1599                 uint64_t ptime0:1;
1600                 uint64_t pcnt3:1;
1601                 uint64_t pcnt2:1;
1602                 uint64_t pcnt1:1;
1603                 uint64_t pcnt0:1;
1604                 uint64_t rsl_int:1;
1605                 uint64_t ill_rrd:1;
1606                 uint64_t ill_rwr:1;
1607                 uint64_t dperr:1;
1608                 uint64_t aperr:1;
1609                 uint64_t serr:1;
1610                 uint64_t tsr_abt:1;
1611                 uint64_t msc_msg:1;
1612                 uint64_t msi_mabt:1;
1613                 uint64_t msi_tabt:1;
1614                 uint64_t msi_per:1;
1615                 uint64_t mr_tto:1;
1616                 uint64_t mr_abt:1;
1617                 uint64_t tr_abt:1;
1618                 uint64_t mr_wtto:1;
1619                 uint64_t mr_wabt:1;
1620                 uint64_t tr_wabt:1;
1621 #else
1622                 uint64_t tr_wabt:1;
1623                 uint64_t mr_wabt:1;
1624                 uint64_t mr_wtto:1;
1625                 uint64_t tr_abt:1;
1626                 uint64_t mr_abt:1;
1627                 uint64_t mr_tto:1;
1628                 uint64_t msi_per:1;
1629                 uint64_t msi_tabt:1;
1630                 uint64_t msi_mabt:1;
1631                 uint64_t msc_msg:1;
1632                 uint64_t tsr_abt:1;
1633                 uint64_t serr:1;
1634                 uint64_t aperr:1;
1635                 uint64_t dperr:1;
1636                 uint64_t ill_rwr:1;
1637                 uint64_t ill_rrd:1;
1638                 uint64_t rsl_int:1;
1639                 uint64_t pcnt0:1;
1640                 uint64_t pcnt1:1;
1641                 uint64_t pcnt2:1;
1642                 uint64_t pcnt3:1;
1643                 uint64_t ptime0:1;
1644                 uint64_t ptime1:1;
1645                 uint64_t ptime2:1;
1646                 uint64_t ptime3:1;
1647                 uint64_t dcnt0:1;
1648                 uint64_t dcnt1:1;
1649                 uint64_t dtime0:1;
1650                 uint64_t dtime1:1;
1651                 uint64_t dma0_fi:1;
1652                 uint64_t dma1_fi:1;
1653                 uint64_t win_wr:1;
1654                 uint64_t ill_wr:1;
1655                 uint64_t ill_rd:1;
1656                 uint64_t reserved_34_63:30;
1657 #endif
1658         } s;
1659         struct cvmx_pci_int_sum2_cn30xx {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661                 uint64_t reserved_34_63:30;
1662                 uint64_t ill_rd:1;
1663                 uint64_t ill_wr:1;
1664                 uint64_t win_wr:1;
1665                 uint64_t dma1_fi:1;
1666                 uint64_t dma0_fi:1;
1667                 uint64_t dtime1:1;
1668                 uint64_t dtime0:1;
1669                 uint64_t dcnt1:1;
1670                 uint64_t dcnt0:1;
1671                 uint64_t reserved_22_24:3;
1672                 uint64_t ptime0:1;
1673                 uint64_t reserved_18_20:3;
1674                 uint64_t pcnt0:1;
1675                 uint64_t rsl_int:1;
1676                 uint64_t ill_rrd:1;
1677                 uint64_t ill_rwr:1;
1678                 uint64_t dperr:1;
1679                 uint64_t aperr:1;
1680                 uint64_t serr:1;
1681                 uint64_t tsr_abt:1;
1682                 uint64_t msc_msg:1;
1683                 uint64_t msi_mabt:1;
1684                 uint64_t msi_tabt:1;
1685                 uint64_t msi_per:1;
1686                 uint64_t mr_tto:1;
1687                 uint64_t mr_abt:1;
1688                 uint64_t tr_abt:1;
1689                 uint64_t mr_wtto:1;
1690                 uint64_t mr_wabt:1;
1691                 uint64_t tr_wabt:1;
1692 #else
1693                 uint64_t tr_wabt:1;
1694                 uint64_t mr_wabt:1;
1695                 uint64_t mr_wtto:1;
1696                 uint64_t tr_abt:1;
1697                 uint64_t mr_abt:1;
1698                 uint64_t mr_tto:1;
1699                 uint64_t msi_per:1;
1700                 uint64_t msi_tabt:1;
1701                 uint64_t msi_mabt:1;
1702                 uint64_t msc_msg:1;
1703                 uint64_t tsr_abt:1;
1704                 uint64_t serr:1;
1705                 uint64_t aperr:1;
1706                 uint64_t dperr:1;
1707                 uint64_t ill_rwr:1;
1708                 uint64_t ill_rrd:1;
1709                 uint64_t rsl_int:1;
1710                 uint64_t pcnt0:1;
1711                 uint64_t reserved_18_20:3;
1712                 uint64_t ptime0:1;
1713                 uint64_t reserved_22_24:3;
1714                 uint64_t dcnt0:1;
1715                 uint64_t dcnt1:1;
1716                 uint64_t dtime0:1;
1717                 uint64_t dtime1:1;
1718                 uint64_t dma0_fi:1;
1719                 uint64_t dma1_fi:1;
1720                 uint64_t win_wr:1;
1721                 uint64_t ill_wr:1;
1722                 uint64_t ill_rd:1;
1723                 uint64_t reserved_34_63:30;
1724 #endif
1725         } cn30xx;
1726         struct cvmx_pci_int_sum2_cn31xx {
1727 #ifdef __BIG_ENDIAN_BITFIELD
1728                 uint64_t reserved_34_63:30;
1729                 uint64_t ill_rd:1;
1730                 uint64_t ill_wr:1;
1731                 uint64_t win_wr:1;
1732                 uint64_t dma1_fi:1;
1733                 uint64_t dma0_fi:1;
1734                 uint64_t dtime1:1;
1735                 uint64_t dtime0:1;
1736                 uint64_t dcnt1:1;
1737                 uint64_t dcnt0:1;
1738                 uint64_t reserved_23_24:2;
1739                 uint64_t ptime1:1;
1740                 uint64_t ptime0:1;
1741                 uint64_t reserved_19_20:2;
1742                 uint64_t pcnt1:1;
1743                 uint64_t pcnt0:1;
1744                 uint64_t rsl_int:1;
1745                 uint64_t ill_rrd:1;
1746                 uint64_t ill_rwr:1;
1747                 uint64_t dperr:1;
1748                 uint64_t aperr:1;
1749                 uint64_t serr:1;
1750                 uint64_t tsr_abt:1;
1751                 uint64_t msc_msg:1;
1752                 uint64_t msi_mabt:1;
1753                 uint64_t msi_tabt:1;
1754                 uint64_t msi_per:1;
1755                 uint64_t mr_tto:1;
1756                 uint64_t mr_abt:1;
1757                 uint64_t tr_abt:1;
1758                 uint64_t mr_wtto:1;
1759                 uint64_t mr_wabt:1;
1760                 uint64_t tr_wabt:1;
1761 #else
1762                 uint64_t tr_wabt:1;
1763                 uint64_t mr_wabt:1;
1764                 uint64_t mr_wtto:1;
1765                 uint64_t tr_abt:1;
1766                 uint64_t mr_abt:1;
1767                 uint64_t mr_tto:1;
1768                 uint64_t msi_per:1;
1769                 uint64_t msi_tabt:1;
1770                 uint64_t msi_mabt:1;
1771                 uint64_t msc_msg:1;
1772                 uint64_t tsr_abt:1;
1773                 uint64_t serr:1;
1774                 uint64_t aperr:1;
1775                 uint64_t dperr:1;
1776                 uint64_t ill_rwr:1;
1777                 uint64_t ill_rrd:1;
1778                 uint64_t rsl_int:1;
1779                 uint64_t pcnt0:1;
1780                 uint64_t pcnt1:1;
1781                 uint64_t reserved_19_20:2;
1782                 uint64_t ptime0:1;
1783                 uint64_t ptime1:1;
1784                 uint64_t reserved_23_24:2;
1785                 uint64_t dcnt0:1;
1786                 uint64_t dcnt1:1;
1787                 uint64_t dtime0:1;
1788                 uint64_t dtime1:1;
1789                 uint64_t dma0_fi:1;
1790                 uint64_t dma1_fi:1;
1791                 uint64_t win_wr:1;
1792                 uint64_t ill_wr:1;
1793                 uint64_t ill_rd:1;
1794                 uint64_t reserved_34_63:30;
1795 #endif
1796         } cn31xx;
1797 };
1798
1799 union cvmx_pci_msi_rcv {
1800         uint32_t u32;
1801         struct cvmx_pci_msi_rcv_s {
1802 #ifdef __BIG_ENDIAN_BITFIELD
1803                 uint32_t reserved_6_31:26;
1804                 uint32_t intr:6;
1805 #else
1806                 uint32_t intr:6;
1807                 uint32_t reserved_6_31:26;
1808 #endif
1809         } s;
1810 };
1811
1812 union cvmx_pci_pkt_creditsx {
1813         uint32_t u32;
1814         struct cvmx_pci_pkt_creditsx_s {
1815 #ifdef __BIG_ENDIAN_BITFIELD
1816                 uint32_t pkt_cnt:16;
1817                 uint32_t ptr_cnt:16;
1818 #else
1819                 uint32_t ptr_cnt:16;
1820                 uint32_t pkt_cnt:16;
1821 #endif
1822         } s;
1823 };
1824
1825 union cvmx_pci_pkts_sentx {
1826         uint32_t u32;
1827         struct cvmx_pci_pkts_sentx_s {
1828 #ifdef __BIG_ENDIAN_BITFIELD
1829                 uint32_t pkt_cnt:32;
1830 #else
1831                 uint32_t pkt_cnt:32;
1832 #endif
1833         } s;
1834 };
1835
1836 union cvmx_pci_pkts_sent_int_levx {
1837         uint32_t u32;
1838         struct cvmx_pci_pkts_sent_int_levx_s {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840                 uint32_t pkt_cnt:32;
1841 #else
1842                 uint32_t pkt_cnt:32;
1843 #endif
1844         } s;
1845 };
1846
1847 union cvmx_pci_pkts_sent_timex {
1848         uint32_t u32;
1849         struct cvmx_pci_pkts_sent_timex_s {
1850 #ifdef __BIG_ENDIAN_BITFIELD
1851                 uint32_t pkt_time:32;
1852 #else
1853                 uint32_t pkt_time:32;
1854 #endif
1855         } s;
1856 };
1857
1858 union cvmx_pci_read_cmd_6 {
1859         uint32_t u32;
1860         struct cvmx_pci_read_cmd_6_s {
1861 #ifdef __BIG_ENDIAN_BITFIELD
1862                 uint32_t reserved_9_31:23;
1863                 uint32_t min_data:6;
1864                 uint32_t prefetch:3;
1865 #else
1866                 uint32_t prefetch:3;
1867                 uint32_t min_data:6;
1868                 uint32_t reserved_9_31:23;
1869 #endif
1870         } s;
1871 };
1872
1873 union cvmx_pci_read_cmd_c {
1874         uint32_t u32;
1875         struct cvmx_pci_read_cmd_c_s {
1876 #ifdef __BIG_ENDIAN_BITFIELD
1877                 uint32_t reserved_9_31:23;
1878                 uint32_t min_data:6;
1879                 uint32_t prefetch:3;
1880 #else
1881                 uint32_t prefetch:3;
1882                 uint32_t min_data:6;
1883                 uint32_t reserved_9_31:23;
1884 #endif
1885         } s;
1886 };
1887
1888 union cvmx_pci_read_cmd_e {
1889         uint32_t u32;
1890         struct cvmx_pci_read_cmd_e_s {
1891 #ifdef __BIG_ENDIAN_BITFIELD
1892                 uint32_t reserved_9_31:23;
1893                 uint32_t min_data:6;
1894                 uint32_t prefetch:3;
1895 #else
1896                 uint32_t prefetch:3;
1897                 uint32_t min_data:6;
1898                 uint32_t reserved_9_31:23;
1899 #endif
1900         } s;
1901 };
1902
1903 union cvmx_pci_read_timeout {
1904         uint64_t u64;
1905         struct cvmx_pci_read_timeout_s {
1906 #ifdef __BIG_ENDIAN_BITFIELD
1907                 uint64_t reserved_32_63:32;
1908                 uint64_t enb:1;
1909                 uint64_t cnt:31;
1910 #else
1911                 uint64_t cnt:31;
1912                 uint64_t enb:1;
1913                 uint64_t reserved_32_63:32;
1914 #endif
1915         } s;
1916 };
1917
1918 union cvmx_pci_scm_reg {
1919         uint64_t u64;
1920         struct cvmx_pci_scm_reg_s {
1921 #ifdef __BIG_ENDIAN_BITFIELD
1922                 uint64_t reserved_32_63:32;
1923                 uint64_t scm:32;
1924 #else
1925                 uint64_t scm:32;
1926                 uint64_t reserved_32_63:32;
1927 #endif
1928         } s;
1929 };
1930
1931 union cvmx_pci_tsr_reg {
1932         uint64_t u64;
1933         struct cvmx_pci_tsr_reg_s {
1934 #ifdef __BIG_ENDIAN_BITFIELD
1935                 uint64_t reserved_36_63:28;
1936                 uint64_t tsr:36;
1937 #else
1938                 uint64_t tsr:36;
1939                 uint64_t reserved_36_63:28;
1940 #endif
1941         } s;
1942 };
1943
1944 union cvmx_pci_win_rd_addr {
1945         uint64_t u64;
1946         struct cvmx_pci_win_rd_addr_s {
1947 #ifdef __BIG_ENDIAN_BITFIELD
1948                 uint64_t reserved_49_63:15;
1949                 uint64_t iobit:1;
1950                 uint64_t reserved_0_47:48;
1951 #else
1952                 uint64_t reserved_0_47:48;
1953                 uint64_t iobit:1;
1954                 uint64_t reserved_49_63:15;
1955 #endif
1956         } s;
1957         struct cvmx_pci_win_rd_addr_cn30xx {
1958 #ifdef __BIG_ENDIAN_BITFIELD
1959                 uint64_t reserved_49_63:15;
1960                 uint64_t iobit:1;
1961                 uint64_t rd_addr:46;
1962                 uint64_t reserved_0_1:2;
1963 #else
1964                 uint64_t reserved_0_1:2;
1965                 uint64_t rd_addr:46;
1966                 uint64_t iobit:1;
1967                 uint64_t reserved_49_63:15;
1968 #endif
1969         } cn30xx;
1970         struct cvmx_pci_win_rd_addr_cn38xx {
1971 #ifdef __BIG_ENDIAN_BITFIELD
1972                 uint64_t reserved_49_63:15;
1973                 uint64_t iobit:1;
1974                 uint64_t rd_addr:45;
1975                 uint64_t reserved_0_2:3;
1976 #else
1977                 uint64_t reserved_0_2:3;
1978                 uint64_t rd_addr:45;
1979                 uint64_t iobit:1;
1980                 uint64_t reserved_49_63:15;
1981 #endif
1982         } cn38xx;
1983 };
1984
1985 union cvmx_pci_win_rd_data {
1986         uint64_t u64;
1987         struct cvmx_pci_win_rd_data_s {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989                 uint64_t rd_data:64;
1990 #else
1991                 uint64_t rd_data:64;
1992 #endif
1993         } s;
1994 };
1995
1996 union cvmx_pci_win_wr_addr {
1997         uint64_t u64;
1998         struct cvmx_pci_win_wr_addr_s {
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000                 uint64_t reserved_49_63:15;
2001                 uint64_t iobit:1;
2002                 uint64_t wr_addr:45;
2003                 uint64_t reserved_0_2:3;
2004 #else
2005                 uint64_t reserved_0_2:3;
2006                 uint64_t wr_addr:45;
2007                 uint64_t iobit:1;
2008                 uint64_t reserved_49_63:15;
2009 #endif
2010         } s;
2011 };
2012
2013 union cvmx_pci_win_wr_data {
2014         uint64_t u64;
2015         struct cvmx_pci_win_wr_data_s {
2016 #ifdef __BIG_ENDIAN_BITFIELD
2017                 uint64_t wr_data:64;
2018 #else
2019                 uint64_t wr_data:64;
2020 #endif
2021         } s;
2022 };
2023
2024 union cvmx_pci_win_wr_mask {
2025         uint64_t u64;
2026         struct cvmx_pci_win_wr_mask_s {
2027 #ifdef __BIG_ENDIAN_BITFIELD
2028                 uint64_t reserved_8_63:56;
2029                 uint64_t wr_mask:8;
2030 #else
2031                 uint64_t wr_mask:8;
2032                 uint64_t reserved_8_63:56;
2033 #endif
2034         } s;
2035 };
2036
2037 #endif