arch/mips/include/asm/octeon/cvmx-pemx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_PEMX_DEFS_H__
  29 #define __CVMX_PEMX_DEFS_H__
  30
  31 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
  32 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
  33 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
  34 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
  35 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
  36 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
  37 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
  38 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
  39 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
  40 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
  41 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
  42 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
  43 #define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
  44 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
  45 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
  46 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
  47 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
  48 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
  49 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
  50 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
  51 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
  52 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
  53
  54 union cvmx_pemx_bar1_indexx {
  55         uint64_t u64;
  56         struct cvmx_pemx_bar1_indexx_s {
  57 #ifdef __BIG_ENDIAN_BITFIELD
  58                 uint64_t reserved_20_63:44;
  59                 uint64_t addr_idx:16;
  60                 uint64_t ca:1;
  61                 uint64_t end_swp:2;
  62                 uint64_t addr_v:1;
  63 #else
  64                 uint64_t addr_v:1;
  65                 uint64_t end_swp:2;
  66                 uint64_t ca:1;
  67                 uint64_t addr_idx:16;
  68                 uint64_t reserved_20_63:44;
  69 #endif
  70         } s;
  71 };
  72
  73 union cvmx_pemx_bar2_mask {
  74         uint64_t u64;
  75         struct cvmx_pemx_bar2_mask_s {
  76 #ifdef __BIG_ENDIAN_BITFIELD
  77                 uint64_t reserved_38_63:26;
  78                 uint64_t mask:35;
  79                 uint64_t reserved_0_2:3;
  80 #else
  81                 uint64_t reserved_0_2:3;
  82                 uint64_t mask:35;
  83                 uint64_t reserved_38_63:26;
  84 #endif
  85         } s;
  86 };
  87
  88 union cvmx_pemx_bar_ctl {
  89         uint64_t u64;
  90         struct cvmx_pemx_bar_ctl_s {
  91 #ifdef __BIG_ENDIAN_BITFIELD
  92                 uint64_t reserved_7_63:57;
  93                 uint64_t bar1_siz:3;
  94                 uint64_t bar2_enb:1;
  95                 uint64_t bar2_esx:2;
  96                 uint64_t bar2_cax:1;
  97 #else
  98                 uint64_t bar2_cax:1;
  99                 uint64_t bar2_esx:2;
 100                 uint64_t bar2_enb:1;
 101                 uint64_t bar1_siz:3;
 102                 uint64_t reserved_7_63:57;
 103 #endif
 104         } s;
 105 };
 106
 107 union cvmx_pemx_bist_status {
 108         uint64_t u64;
 109         struct cvmx_pemx_bist_status_s {
 110 #ifdef __BIG_ENDIAN_BITFIELD
 111                 uint64_t reserved_8_63:56;
 112                 uint64_t retry:1;
 113                 uint64_t rqdata0:1;
 114                 uint64_t rqdata1:1;
 115                 uint64_t rqdata2:1;
 116                 uint64_t rqdata3:1;
 117                 uint64_t rqhdr1:1;
 118                 uint64_t rqhdr0:1;
 119                 uint64_t sot:1;
 120 #else
 121                 uint64_t sot:1;
 122                 uint64_t rqhdr0:1;
 123                 uint64_t rqhdr1:1;
 124                 uint64_t rqdata3:1;
 125                 uint64_t rqdata2:1;
 126                 uint64_t rqdata1:1;
 127                 uint64_t rqdata0:1;
 128                 uint64_t retry:1;
 129                 uint64_t reserved_8_63:56;
 130 #endif
 131         } s;
 132 };
 133
 134 union cvmx_pemx_bist_status2 {
 135         uint64_t u64;
 136         struct cvmx_pemx_bist_status2_s {
 137 #ifdef __BIG_ENDIAN_BITFIELD
 138                 uint64_t reserved_10_63:54;
 139                 uint64_t e2p_cpl:1;
 140                 uint64_t e2p_n:1;
 141                 uint64_t e2p_p:1;
 142                 uint64_t peai_p2e:1;
 143                 uint64_t pef_tpf1:1;
 144                 uint64_t pef_tpf0:1;
 145                 uint64_t pef_tnf:1;
 146                 uint64_t pef_tcf1:1;
 147                 uint64_t pef_tc0:1;
 148                 uint64_t ppf:1;
 149 #else
 150                 uint64_t ppf:1;
 151                 uint64_t pef_tc0:1;
 152                 uint64_t pef_tcf1:1;
 153                 uint64_t pef_tnf:1;
 154                 uint64_t pef_tpf0:1;
 155                 uint64_t pef_tpf1:1;
 156                 uint64_t peai_p2e:1;
 157                 uint64_t e2p_p:1;
 158                 uint64_t e2p_n:1;
 159                 uint64_t e2p_cpl:1;
 160                 uint64_t reserved_10_63:54;
 161 #endif
 162         } s;
 163 };
 164
 165 union cvmx_pemx_cfg_rd {
 166         uint64_t u64;
 167         struct cvmx_pemx_cfg_rd_s {
 168 #ifdef __BIG_ENDIAN_BITFIELD
 169                 uint64_t data:32;
 170                 uint64_t addr:32;
 171 #else
 172                 uint64_t addr:32;
 173                 uint64_t data:32;
 174 #endif
 175         } s;
 176 };
 177
 178 union cvmx_pemx_cfg_wr {
 179         uint64_t u64;
 180         struct cvmx_pemx_cfg_wr_s {
 181 #ifdef __BIG_ENDIAN_BITFIELD
 182                 uint64_t data:32;
 183                 uint64_t addr:32;
 184 #else
 185                 uint64_t addr:32;
 186                 uint64_t data:32;
 187 #endif
 188         } s;
 189 };
 190
 191 union cvmx_pemx_cpl_lut_valid {
 192         uint64_t u64;
 193         struct cvmx_pemx_cpl_lut_valid_s {
 194 #ifdef __BIG_ENDIAN_BITFIELD
 195                 uint64_t reserved_32_63:32;
 196                 uint64_t tag:32;
 197 #else
 198                 uint64_t tag:32;
 199                 uint64_t reserved_32_63:32;
 200 #endif
 201         } s;
 202 };
 203
 204 union cvmx_pemx_ctl_status {
 205         uint64_t u64;
 206         struct cvmx_pemx_ctl_status_s {
 207 #ifdef __BIG_ENDIAN_BITFIELD
 208                 uint64_t reserved_48_63:16;
 209                 uint64_t auto_sd:1;
 210                 uint64_t dnum:5;
 211                 uint64_t pbus:8;
 212                 uint64_t reserved_32_33:2;
 213                 uint64_t cfg_rtry:16;
 214                 uint64_t reserved_12_15:4;
 215                 uint64_t pm_xtoff:1;
 216                 uint64_t pm_xpme:1;
 217                 uint64_t ob_p_cmd:1;
 218                 uint64_t reserved_7_8:2;
 219                 uint64_t nf_ecrc:1;
 220                 uint64_t dly_one:1;
 221                 uint64_t lnk_enb:1;
 222                 uint64_t ro_ctlp:1;
 223                 uint64_t fast_lm:1;
 224                 uint64_t inv_ecrc:1;
 225                 uint64_t inv_lcrc:1;
 226 #else
 227                 uint64_t inv_lcrc:1;
 228                 uint64_t inv_ecrc:1;
 229                 uint64_t fast_lm:1;
 230                 uint64_t ro_ctlp:1;
 231                 uint64_t lnk_enb:1;
 232                 uint64_t dly_one:1;
 233                 uint64_t nf_ecrc:1;
 234                 uint64_t reserved_7_8:2;
 235                 uint64_t ob_p_cmd:1;
 236                 uint64_t pm_xpme:1;
 237                 uint64_t pm_xtoff:1;
 238                 uint64_t reserved_12_15:4;
 239                 uint64_t cfg_rtry:16;
 240                 uint64_t reserved_32_33:2;
 241                 uint64_t pbus:8;
 242                 uint64_t dnum:5;
 243                 uint64_t auto_sd:1;
 244                 uint64_t reserved_48_63:16;
 245 #endif
 246         } s;
 247 };
 248
 249 union cvmx_pemx_dbg_info {
 250         uint64_t u64;
 251         struct cvmx_pemx_dbg_info_s {
 252 #ifdef __BIG_ENDIAN_BITFIELD
 253                 uint64_t reserved_31_63:33;
 254                 uint64_t ecrc_e:1;
 255                 uint64_t rawwpp:1;
 256                 uint64_t racpp:1;
 257                 uint64_t ramtlp:1;
 258                 uint64_t rarwdns:1;
 259                 uint64_t caar:1;
 260                 uint64_t racca:1;
 261                 uint64_t racur:1;
 262                 uint64_t rauc:1;
 263                 uint64_t rqo:1;
 264                 uint64_t fcuv:1;
 265                 uint64_t rpe:1;
 266                 uint64_t fcpvwt:1;
 267                 uint64_t dpeoosd:1;
 268                 uint64_t rtwdle:1;
 269                 uint64_t rdwdle:1;
 270                 uint64_t mre:1;
 271                 uint64_t rte:1;
 272                 uint64_t acto:1;
 273                 uint64_t rvdm:1;
 274                 uint64_t rumep:1;
 275                 uint64_t rptamrc:1;
 276                 uint64_t rpmerc:1;
 277                 uint64_t rfemrc:1;
 278                 uint64_t rnfemrc:1;
 279                 uint64_t rcemrc:1;
 280                 uint64_t rpoison:1;
 281                 uint64_t recrce:1;
 282                 uint64_t rtlplle:1;
 283                 uint64_t rtlpmal:1;
 284                 uint64_t spoison:1;
 285 #else
 286                 uint64_t spoison:1;
 287                 uint64_t rtlpmal:1;
 288                 uint64_t rtlplle:1;
 289                 uint64_t recrce:1;
 290                 uint64_t rpoison:1;
 291                 uint64_t rcemrc:1;
 292                 uint64_t rnfemrc:1;
 293                 uint64_t rfemrc:1;
 294                 uint64_t rpmerc:1;
 295                 uint64_t rptamrc:1;
 296                 uint64_t rumep:1;
 297                 uint64_t rvdm:1;
 298                 uint64_t acto:1;
 299                 uint64_t rte:1;
 300                 uint64_t mre:1;
 301                 uint64_t rdwdle:1;
 302                 uint64_t rtwdle:1;
 303                 uint64_t dpeoosd:1;
 304                 uint64_t fcpvwt:1;
 305                 uint64_t rpe:1;
 306                 uint64_t fcuv:1;
 307                 uint64_t rqo:1;
 308                 uint64_t rauc:1;
 309                 uint64_t racur:1;
 310                 uint64_t racca:1;
 311                 uint64_t caar:1;
 312                 uint64_t rarwdns:1;
 313                 uint64_t ramtlp:1;
 314                 uint64_t racpp:1;
 315                 uint64_t rawwpp:1;
 316                 uint64_t ecrc_e:1;
 317                 uint64_t reserved_31_63:33;
 318 #endif
 319         } s;
 320 };
 321
 322 union cvmx_pemx_dbg_info_en {
 323         uint64_t u64;
 324         struct cvmx_pemx_dbg_info_en_s {
 325 #ifdef __BIG_ENDIAN_BITFIELD
 326                 uint64_t reserved_31_63:33;
 327                 uint64_t ecrc_e:1;
 328                 uint64_t rawwpp:1;
 329                 uint64_t racpp:1;
 330                 uint64_t ramtlp:1;
 331                 uint64_t rarwdns:1;
 332                 uint64_t caar:1;
 333                 uint64_t racca:1;
 334                 uint64_t racur:1;
 335                 uint64_t rauc:1;
 336                 uint64_t rqo:1;
 337                 uint64_t fcuv:1;
 338                 uint64_t rpe:1;
 339                 uint64_t fcpvwt:1;
 340                 uint64_t dpeoosd:1;
 341                 uint64_t rtwdle:1;
 342                 uint64_t rdwdle:1;
 343                 uint64_t mre:1;
 344                 uint64_t rte:1;
 345                 uint64_t acto:1;
 346                 uint64_t rvdm:1;
 347                 uint64_t rumep:1;
 348                 uint64_t rptamrc:1;
 349                 uint64_t rpmerc:1;
 350                 uint64_t rfemrc:1;
 351                 uint64_t rnfemrc:1;
 352                 uint64_t rcemrc:1;
 353                 uint64_t rpoison:1;
 354                 uint64_t recrce:1;
 355                 uint64_t rtlplle:1;
 356                 uint64_t rtlpmal:1;
 357                 uint64_t spoison:1;
 358 #else
 359                 uint64_t spoison:1;
 360                 uint64_t rtlpmal:1;
 361                 uint64_t rtlplle:1;
 362                 uint64_t recrce:1;
 363                 uint64_t rpoison:1;
 364                 uint64_t rcemrc:1;
 365                 uint64_t rnfemrc:1;
 366                 uint64_t rfemrc:1;
 367                 uint64_t rpmerc:1;
 368                 uint64_t rptamrc:1;
 369                 uint64_t rumep:1;
 370                 uint64_t rvdm:1;
 371                 uint64_t acto:1;
 372                 uint64_t rte:1;
 373                 uint64_t mre:1;
 374                 uint64_t rdwdle:1;
 375                 uint64_t rtwdle:1;
 376                 uint64_t dpeoosd:1;
 377                 uint64_t fcpvwt:1;
 378                 uint64_t rpe:1;
 379                 uint64_t fcuv:1;
 380                 uint64_t rqo:1;
 381                 uint64_t rauc:1;
 382                 uint64_t racur:1;
 383                 uint64_t racca:1;
 384                 uint64_t caar:1;
 385                 uint64_t rarwdns:1;
 386                 uint64_t ramtlp:1;
 387                 uint64_t racpp:1;
 388                 uint64_t rawwpp:1;
 389                 uint64_t ecrc_e:1;
 390                 uint64_t reserved_31_63:33;
 391 #endif
 392         } s;
 393 };
 394
 395 union cvmx_pemx_diag_status {
 396         uint64_t u64;
 397         struct cvmx_pemx_diag_status_s {
 398 #ifdef __BIG_ENDIAN_BITFIELD
 399                 uint64_t reserved_4_63:60;
 400                 uint64_t pm_dst:1;
 401                 uint64_t pm_stat:1;
 402                 uint64_t pm_en:1;
 403                 uint64_t aux_en:1;
 404 #else
 405                 uint64_t aux_en:1;
 406                 uint64_t pm_en:1;
 407                 uint64_t pm_stat:1;
 408                 uint64_t pm_dst:1;
 409                 uint64_t reserved_4_63:60;
 410 #endif
 411         } s;
 412 };
 413
 414 union cvmx_pemx_inb_read_credits {
 415         uint64_t u64;
 416         struct cvmx_pemx_inb_read_credits_s {
 417 #ifdef __BIG_ENDIAN_BITFIELD
 418                 uint64_t reserved_6_63:58;
 419                 uint64_t num:6;
 420 #else
 421                 uint64_t num:6;
 422                 uint64_t reserved_6_63:58;
 423 #endif
 424         } s;
 425 };
 426
 427 union cvmx_pemx_int_enb {
 428         uint64_t u64;
 429         struct cvmx_pemx_int_enb_s {
 430 #ifdef __BIG_ENDIAN_BITFIELD
 431                 uint64_t reserved_14_63:50;
 432                 uint64_t crs_dr:1;
 433                 uint64_t crs_er:1;
 434                 uint64_t rdlk:1;
 435                 uint64_t exc:1;
 436                 uint64_t un_bx:1;
 437                 uint64_t un_b2:1;
 438                 uint64_t un_b1:1;
 439                 uint64_t up_bx:1;
 440                 uint64_t up_b2:1;
 441                 uint64_t up_b1:1;
 442                 uint64_t pmem:1;
 443                 uint64_t pmei:1;
 444                 uint64_t se:1;
 445                 uint64_t aeri:1;
 446 #else
 447                 uint64_t aeri:1;
 448                 uint64_t se:1;
 449                 uint64_t pmei:1;
 450                 uint64_t pmem:1;
 451                 uint64_t up_b1:1;
 452                 uint64_t up_b2:1;
 453                 uint64_t up_bx:1;
 454                 uint64_t un_b1:1;
 455                 uint64_t un_b2:1;
 456                 uint64_t un_bx:1;
 457                 uint64_t exc:1;
 458                 uint64_t rdlk:1;
 459                 uint64_t crs_er:1;
 460                 uint64_t crs_dr:1;
 461                 uint64_t reserved_14_63:50;
 462 #endif
 463         } s;
 464 };
 465
 466 union cvmx_pemx_int_enb_int {
 467         uint64_t u64;
 468         struct cvmx_pemx_int_enb_int_s {
 469 #ifdef __BIG_ENDIAN_BITFIELD
 470                 uint64_t reserved_14_63:50;
 471                 uint64_t crs_dr:1;
 472                 uint64_t crs_er:1;
 473                 uint64_t rdlk:1;
 474                 uint64_t exc:1;
 475                 uint64_t un_bx:1;
 476                 uint64_t un_b2:1;
 477                 uint64_t un_b1:1;
 478                 uint64_t up_bx:1;
 479                 uint64_t up_b2:1;
 480                 uint64_t up_b1:1;
 481                 uint64_t pmem:1;
 482                 uint64_t pmei:1;
 483                 uint64_t se:1;
 484                 uint64_t aeri:1;
 485 #else
 486                 uint64_t aeri:1;
 487                 uint64_t se:1;
 488                 uint64_t pmei:1;
 489                 uint64_t pmem:1;
 490                 uint64_t up_b1:1;
 491                 uint64_t up_b2:1;
 492                 uint64_t up_bx:1;
 493                 uint64_t un_b1:1;
 494                 uint64_t un_b2:1;
 495                 uint64_t un_bx:1;
 496                 uint64_t exc:1;
 497                 uint64_t rdlk:1;
 498                 uint64_t crs_er:1;
 499                 uint64_t crs_dr:1;
 500                 uint64_t reserved_14_63:50;
 501 #endif
 502         } s;
 503 };
 504
 505 union cvmx_pemx_int_sum {
 506         uint64_t u64;
 507         struct cvmx_pemx_int_sum_s {
 508 #ifdef __BIG_ENDIAN_BITFIELD
 509                 uint64_t reserved_14_63:50;
 510                 uint64_t crs_dr:1;
 511                 uint64_t crs_er:1;
 512                 uint64_t rdlk:1;
 513                 uint64_t exc:1;
 514                 uint64_t un_bx:1;
 515                 uint64_t un_b2:1;
 516                 uint64_t un_b1:1;
 517                 uint64_t up_bx:1;
 518                 uint64_t up_b2:1;
 519                 uint64_t up_b1:1;
 520                 uint64_t pmem:1;
 521                 uint64_t pmei:1;
 522                 uint64_t se:1;
 523                 uint64_t aeri:1;
 524 #else
 525                 uint64_t aeri:1;
 526                 uint64_t se:1;
 527                 uint64_t pmei:1;
 528                 uint64_t pmem:1;
 529                 uint64_t up_b1:1;
 530                 uint64_t up_b2:1;
 531                 uint64_t up_bx:1;
 532                 uint64_t un_b1:1;
 533                 uint64_t un_b2:1;
 534                 uint64_t un_bx:1;
 535                 uint64_t exc:1;
 536                 uint64_t rdlk:1;
 537                 uint64_t crs_er:1;
 538                 uint64_t crs_dr:1;
 539                 uint64_t reserved_14_63:50;
 540 #endif
 541         } s;
 542 };
 543
 544 union cvmx_pemx_p2n_bar0_start {
 545         uint64_t u64;
 546         struct cvmx_pemx_p2n_bar0_start_s {
 547 #ifdef __BIG_ENDIAN_BITFIELD
 548                 uint64_t addr:50;
 549                 uint64_t reserved_0_13:14;
 550 #else
 551                 uint64_t reserved_0_13:14;
 552                 uint64_t addr:50;
 553 #endif
 554         } s;
 555 };
 556
 557 union cvmx_pemx_p2n_bar1_start {
 558         uint64_t u64;
 559         struct cvmx_pemx_p2n_bar1_start_s {
 560 #ifdef __BIG_ENDIAN_BITFIELD
 561                 uint64_t addr:38;
 562                 uint64_t reserved_0_25:26;
 563 #else
 564                 uint64_t reserved_0_25:26;
 565                 uint64_t addr:38;
 566 #endif
 567         } s;
 568 };
 569
 570 union cvmx_pemx_p2n_bar2_start {
 571         uint64_t u64;
 572         struct cvmx_pemx_p2n_bar2_start_s {
 573 #ifdef __BIG_ENDIAN_BITFIELD
 574                 uint64_t addr:23;
 575                 uint64_t reserved_0_40:41;
 576 #else
 577                 uint64_t reserved_0_40:41;
 578                 uint64_t addr:23;
 579 #endif
 580         } s;
 581 };
 582
 583 union cvmx_pemx_p2p_barx_end {
 584         uint64_t u64;
 585         struct cvmx_pemx_p2p_barx_end_s {
 586 #ifdef __BIG_ENDIAN_BITFIELD
 587                 uint64_t addr:52;
 588                 uint64_t reserved_0_11:12;
 589 #else
 590                 uint64_t reserved_0_11:12;
 591                 uint64_t addr:52;
 592 #endif
 593         } s;
 594 };
 595
 596 union cvmx_pemx_p2p_barx_start {
 597         uint64_t u64;
 598         struct cvmx_pemx_p2p_barx_start_s {
 599 #ifdef __BIG_ENDIAN_BITFIELD
 600                 uint64_t addr:52;
 601                 uint64_t reserved_0_11:12;
 602 #else
 603                 uint64_t reserved_0_11:12;
 604                 uint64_t addr:52;
 605 #endif
 606         } s;
 607 };
 608
 609 union cvmx_pemx_tlp_credits {
 610         uint64_t u64;
 611         struct cvmx_pemx_tlp_credits_s {
 612 #ifdef __BIG_ENDIAN_BITFIELD
 613                 uint64_t reserved_56_63:8;
 614                 uint64_t peai_ppf:8;
 615                 uint64_t pem_cpl:8;
 616                 uint64_t pem_np:8;
 617                 uint64_t pem_p:8;
 618                 uint64_t sli_cpl:8;
 619                 uint64_t sli_np:8;
 620                 uint64_t sli_p:8;
 621 #else
 622                 uint64_t sli_p:8;
 623                 uint64_t sli_np:8;
 624                 uint64_t sli_cpl:8;
 625                 uint64_t pem_p:8;
 626                 uint64_t pem_np:8;
 627                 uint64_t pem_cpl:8;
 628                 uint64_t peai_ppf:8;
 629                 uint64_t reserved_56_63:8;
 630 #endif
 631         } s;
 632         struct cvmx_pemx_tlp_credits_cn61xx {
 633 #ifdef __BIG_ENDIAN_BITFIELD
 634                 uint64_t reserved_56_63:8;
 635                 uint64_t peai_ppf:8;
 636                 uint64_t reserved_24_47:24;
 637                 uint64_t sli_cpl:8;
 638                 uint64_t sli_np:8;
 639                 uint64_t sli_p:8;
 640 #else
 641                 uint64_t sli_p:8;
 642                 uint64_t sli_np:8;
 643                 uint64_t sli_cpl:8;
 644                 uint64_t reserved_24_47:24;
 645                 uint64_t peai_ppf:8;
 646                 uint64_t reserved_56_63:8;
 647 #endif
 648         } cn61xx;
 649 };
 650
 651 #endif