arch/mips/include/asm/octeon/cvmx-rst-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Inc.
   3  *
   4  * Contact: support@cavium.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2014 Cavium Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Inc. for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_RST_DEFS_H__
  29 #define __CVMX_RST_DEFS_H__
  30
  31 #define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
  32 #define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
  33 #define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
  34 #define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
  35 #define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
  36 #define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
  37 #define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
  38 #define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
  39 #define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
  40 #define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
  41 #define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
  42 #define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
  43
  44 union cvmx_rst_boot {
  45         uint64_t u64;
  46         struct cvmx_rst_boot_s {
  47 #ifdef __BIG_ENDIAN_BITFIELD
  48                 uint64_t chipkill:1;
  49                 uint64_t jtcsrdis:1;
  50                 uint64_t ejtagdis:1;
  51                 uint64_t romen:1;
  52                 uint64_t ckill_ppdis:1;
  53                 uint64_t jt_tstmode:1;
  54                 uint64_t vrm_err:1;
  55                 uint64_t reserved_37_56:20;
  56                 uint64_t c_mul:7;
  57                 uint64_t pnr_mul:6;
  58                 uint64_t reserved_21_23:3;
  59                 uint64_t lboot_oci:3;
  60                 uint64_t lboot_ext:6;
  61                 uint64_t lboot:10;
  62                 uint64_t rboot:1;
  63                 uint64_t rboot_pin:1;
  64 #else
  65                 uint64_t rboot_pin:1;
  66                 uint64_t rboot:1;
  67                 uint64_t lboot:10;
  68                 uint64_t lboot_ext:6;
  69                 uint64_t lboot_oci:3;
  70                 uint64_t reserved_21_23:3;
  71                 uint64_t pnr_mul:6;
  72                 uint64_t c_mul:7;
  73                 uint64_t reserved_37_56:20;
  74                 uint64_t vrm_err:1;
  75                 uint64_t jt_tstmode:1;
  76                 uint64_t ckill_ppdis:1;
  77                 uint64_t romen:1;
  78                 uint64_t ejtagdis:1;
  79                 uint64_t jtcsrdis:1;
  80                 uint64_t chipkill:1;
  81 #endif
  82         } s;
  83 };
  84
  85 union cvmx_rst_cfg {
  86         uint64_t u64;
  87         struct cvmx_rst_cfg_s {
  88 #ifdef __BIG_ENDIAN_BITFIELD
  89                 uint64_t bist_delay:58;
  90                 uint64_t reserved_3_5:3;
  91                 uint64_t cntl_clr_bist:1;
  92                 uint64_t warm_clr_bist:1;
  93                 uint64_t soft_clr_bist:1;
  94 #else
  95                 uint64_t soft_clr_bist:1;
  96                 uint64_t warm_clr_bist:1;
  97                 uint64_t cntl_clr_bist:1;
  98                 uint64_t reserved_3_5:3;
  99                 uint64_t bist_delay:58;
 100 #endif
 101         } s;
 102 };
 103
 104 union cvmx_rst_ckill {
 105         uint64_t u64;
 106         struct cvmx_rst_ckill_s {
 107 #ifdef __BIG_ENDIAN_BITFIELD
 108                 uint64_t reserved_47_63:17;
 109                 uint64_t timer:47;
 110 #else
 111                 uint64_t timer:47;
 112                 uint64_t reserved_47_63:17;
 113 #endif
 114         } s;
 115 };
 116
 117 union cvmx_rst_ctlx {
 118         uint64_t u64;
 119         struct cvmx_rst_ctlx_s {
 120 #ifdef __BIG_ENDIAN_BITFIELD
 121                 uint64_t reserved_10_63:54;
 122                 uint64_t prst_link:1;
 123                 uint64_t rst_done:1;
 124                 uint64_t rst_link:1;
 125                 uint64_t host_mode:1;
 126                 uint64_t reserved_4_5:2;
 127                 uint64_t rst_drv:1;
 128                 uint64_t rst_rcv:1;
 129                 uint64_t rst_chip:1;
 130                 uint64_t rst_val:1;
 131 #else
 132                 uint64_t rst_val:1;
 133                 uint64_t rst_chip:1;
 134                 uint64_t rst_rcv:1;
 135                 uint64_t rst_drv:1;
 136                 uint64_t reserved_4_5:2;
 137                 uint64_t host_mode:1;
 138                 uint64_t rst_link:1;
 139                 uint64_t rst_done:1;
 140                 uint64_t prst_link:1;
 141                 uint64_t reserved_10_63:54;
 142 #endif
 143         } s;
 144 };
 145
 146 union cvmx_rst_delay {
 147         uint64_t u64;
 148         struct cvmx_rst_delay_s {
 149 #ifdef __BIG_ENDIAN_BITFIELD
 150                 uint64_t reserved_32_63:32;
 151                 uint64_t warm_rst_dly:16;
 152                 uint64_t soft_rst_dly:16;
 153 #else
 154                 uint64_t soft_rst_dly:16;
 155                 uint64_t warm_rst_dly:16;
 156                 uint64_t reserved_32_63:32;
 157 #endif
 158         } s;
 159 };
 160
 161 union cvmx_rst_eco {
 162         uint64_t u64;
 163         struct cvmx_rst_eco_s {
 164 #ifdef __BIG_ENDIAN_BITFIELD
 165                 uint64_t reserved_32_63:32;
 166                 uint64_t eco_rw:32;
 167 #else
 168                 uint64_t eco_rw:32;
 169                 uint64_t reserved_32_63:32;
 170 #endif
 171         } s;
 172 };
 173
 174 union cvmx_rst_int {
 175         uint64_t u64;
 176         struct cvmx_rst_int_s {
 177 #ifdef __BIG_ENDIAN_BITFIELD
 178                 uint64_t reserved_12_63:52;
 179                 uint64_t perst:4;
 180                 uint64_t reserved_4_7:4;
 181                 uint64_t rst_link:4;
 182 #else
 183                 uint64_t rst_link:4;
 184                 uint64_t reserved_4_7:4;
 185                 uint64_t perst:4;
 186                 uint64_t reserved_12_63:52;
 187 #endif
 188         } s;
 189         struct cvmx_rst_int_cn70xx {
 190 #ifdef __BIG_ENDIAN_BITFIELD
 191                 uint64_t reserved_11_63:53;
 192                 uint64_t perst:3;
 193                 uint64_t reserved_3_7:5;
 194                 uint64_t rst_link:3;
 195 #else
 196                 uint64_t rst_link:3;
 197                 uint64_t reserved_3_7:5;
 198                 uint64_t perst:3;
 199                 uint64_t reserved_11_63:53;
 200 #endif
 201         } cn70xx;
 202 };
 203
 204 union cvmx_rst_ocx {
 205         uint64_t u64;
 206         struct cvmx_rst_ocx_s {
 207 #ifdef __BIG_ENDIAN_BITFIELD
 208                 uint64_t reserved_3_63:61;
 209                 uint64_t rst_link:3;
 210 #else
 211                 uint64_t rst_link:3;
 212                 uint64_t reserved_3_63:61;
 213 #endif
 214         } s;
 215 };
 216
 217 union cvmx_rst_power_dbg {
 218         uint64_t u64;
 219         struct cvmx_rst_power_dbg_s {
 220 #ifdef __BIG_ENDIAN_BITFIELD
 221                 uint64_t reserved_3_63:61;
 222                 uint64_t str:3;
 223 #else
 224                 uint64_t str:3;
 225                 uint64_t reserved_3_63:61;
 226 #endif
 227         } s;
 228 };
 229
 230 union cvmx_rst_pp_power {
 231         uint64_t u64;
 232         struct cvmx_rst_pp_power_s {
 233 #ifdef __BIG_ENDIAN_BITFIELD
 234                 uint64_t reserved_48_63:16;
 235                 uint64_t gate:48;
 236 #else
 237                 uint64_t gate:48;
 238                 uint64_t reserved_48_63:16;
 239 #endif
 240         } s;
 241         struct cvmx_rst_pp_power_cn70xx {
 242 #ifdef __BIG_ENDIAN_BITFIELD
 243                 uint64_t reserved_4_63:60;
 244                 uint64_t gate:4;
 245 #else
 246                 uint64_t gate:4;
 247                 uint64_t reserved_4_63:60;
 248 #endif
 249         } cn70xx;
 250 };
 251
 252 union cvmx_rst_soft_prstx {
 253         uint64_t u64;
 254         struct cvmx_rst_soft_prstx_s {
 255 #ifdef __BIG_ENDIAN_BITFIELD
 256                 uint64_t reserved_1_63:63;
 257                 uint64_t soft_prst:1;
 258 #else
 259                 uint64_t soft_prst:1;
 260                 uint64_t reserved_1_63:63;
 261 #endif
 262         } s;
 263 };
 264
 265 union cvmx_rst_soft_rst {
 266         uint64_t u64;
 267         struct cvmx_rst_soft_rst_s {
 268 #ifdef __BIG_ENDIAN_BITFIELD
 269                 uint64_t reserved_1_63:63;
 270                 uint64_t soft_rst:1;
 271 #else
 272                 uint64_t soft_rst:1;
 273                 uint64_t reserved_1_63:63;
 274 #endif
 275         } s;
 276 };
 277
 278 #endif