arch/mips/pci/pci-lantiq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
   5  */
   6
   7 #include <linux/types.h>
   8 #include <linux/pci.h>
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/delay.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/mm.h>
  14 #include <linux/vmalloc.h>
  15 #include <linux/clk.h>
  16 #include <linux/of.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <asm/addrspace.h>
  21
  22 #include <lantiq_soc.h>
  23 #include <lantiq_irq.h>
  24
  25 #include "pci-lantiq.h"
  26
  27 #define PCI_CR_FCI_ADDR_MAP0            0x00C0
  28 #define PCI_CR_FCI_ADDR_MAP1            0x00C4
  29 #define PCI_CR_FCI_ADDR_MAP2            0x00C8
  30 #define PCI_CR_FCI_ADDR_MAP3            0x00CC
  31 #define PCI_CR_FCI_ADDR_MAP4            0x00D0
  32 #define PCI_CR_FCI_ADDR_MAP5            0x00D4
  33 #define PCI_CR_FCI_ADDR_MAP6            0x00D8
  34 #define PCI_CR_FCI_ADDR_MAP7            0x00DC
  35 #define PCI_CR_CLK_CTRL                 0x0000
  36 #define PCI_CR_PCI_MOD                  0x0030
  37 #define PCI_CR_PC_ARB                   0x0080
  38 #define PCI_CR_FCI_ADDR_MAP11hg         0x00E4
  39 #define PCI_CR_BAR11MASK                0x0044
  40 #define PCI_CR_BAR12MASK                0x0048
  41 #define PCI_CR_BAR13MASK                0x004C
  42 #define PCI_CS_BASE_ADDR1               0x0010
  43 #define PCI_CR_PCI_ADDR_MAP11           0x0064
  44 #define PCI_CR_FCI_BURST_LENGTH         0x00E8
  45 #define PCI_CR_PCI_EOI                  0x002C
  46 #define PCI_CS_STS_CMD                  0x0004
  47
  48 #define PCI_MASTER0_REQ_MASK_2BITS      8
  49 #define PCI_MASTER1_REQ_MASK_2BITS      10
  50 #define PCI_MASTER2_REQ_MASK_2BITS      12
  51 #define INTERNAL_ARB_ENABLE_BIT         0
  52
  53 #define LTQ_CGU_IFCCR           0x0018
  54 #define LTQ_CGU_PCICR           0x0034
  55
  56 #define ltq_pci_w32(x, y)       ltq_w32((x), ltq_pci_membase + (y))
  57 #define ltq_pci_r32(x)          ltq_r32(ltq_pci_membase + (x))
  58
  59 #define ltq_pci_cfg_w32(x, y)   ltq_w32((x), ltq_pci_mapped_cfg + (y))
  60 #define ltq_pci_cfg_r32(x)      ltq_r32(ltq_pci_mapped_cfg + (x))
  61
  62 __iomem void *ltq_pci_mapped_cfg;
  63 static __iomem void *ltq_pci_membase;
  64
  65 static struct gpio_desc *reset_gpio;
  66 static struct clk *clk_pci, *clk_external;
  67 static struct resource pci_io_resource;
  68 static struct resource pci_mem_resource;
  69 static struct pci_ops pci_ops = {
  70         .read   = ltq_pci_read_config_dword,
  71         .write  = ltq_pci_write_config_dword
  72 };
  73
  74 static struct pci_controller pci_controller = {
  75         .pci_ops        = &pci_ops,
  76         .mem_resource   = &pci_mem_resource,
  77         .mem_offset     = 0x00000000UL,
  78         .io_resource    = &pci_io_resource,
  79         .io_offset      = 0x00000000UL,
  80 };
  81
  82 static inline u32 ltq_calc_bar11mask(void)
  83 {
  84         u32 mem, bar11mask;
  85
  86         /* BAR11MASK value depends on available memory on system. */
  87         mem = get_num_physpages() * PAGE_SIZE;
  88         bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
  89
  90         return bar11mask;
  91 }
  92
  93 static int ltq_pci_startup(struct platform_device *pdev)
  94 {
  95         struct device_node *node = pdev->dev.of_node;
  96         const __be32 *req_mask, *bus_clk;
  97         u32 temp_buffer;
  98         int error;
  99
 100         /* get our clocks */
 101         clk_pci = clk_get(&pdev->dev, NULL);
 102         if (IS_ERR(clk_pci)) {
 103                 dev_err(&pdev->dev, "failed to get pci clock\n");
 104                 return PTR_ERR(clk_pci);
 105         }
 106
 107         clk_external = clk_get(&pdev->dev, "external");
 108         if (IS_ERR(clk_external)) {
 109                 clk_put(clk_pci);
 110                 dev_err(&pdev->dev, "failed to get external pci clock\n");
 111                 return PTR_ERR(clk_external);
 112         }
 113
 114         /* read the bus speed that we want */
 115         bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
 116         if (bus_clk)
 117                 clk_set_rate(clk_pci, *bus_clk);
 118
 119         /* and enable the clocks */
 120         clk_enable(clk_pci);
 121         if (of_property_read_bool(node, "lantiq,external-clock"))
 122                 clk_enable(clk_external);
 123         else
 124                 clk_disable(clk_external);
 125
 126         /* setup reset gpio used by pci */
 127         reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
 128                                              GPIOD_OUT_LOW);
 129         error = PTR_ERR_OR_ZERO(reset_gpio);
 130         if (error) {
 131                 dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
 132                 return error;
 133         }
 134         gpiod_set_consumer_name(reset_gpio, "pci_reset");
 135
 136         /* enable auto-switching between PCI and EBU */
 137         ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
 138
 139         /* busy, i.e. configuration is not done, PCI access has to be retried */
 140         ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
 141         wmb();
 142         /* BUS Master/IO/MEM access */
 143         ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 144
 145         /* enable external 2 PCI masters */
 146         temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
 147         /* setup the request mask */
 148         req_mask = of_get_property(node, "req-mask", NULL);
 149         if (req_mask)
 150                 temp_buffer &= ~((*req_mask & 0xf) << 16);
 151         else
 152                 temp_buffer &= ~0xf0000;
 153         /* enable internal arbiter */
 154         temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 155         /* enable internal PCI master request */
 156         temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 157
 158         /* enable EBU request */
 159         temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 160
 161         /* enable all external masters request */
 162         temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 163         ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
 164         wmb();
 165
 166         /* setup BAR memory regions */
 167         ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 168         ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 169         ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 170         ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 171         ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 172         ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 173         ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 174         ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 175         ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 176         ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
 177         ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
 178         ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
 179         /* both TX and RX endian swap are enabled */
 180         ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
 181         wmb();
 182         ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
 183                 PCI_CR_BAR12MASK);
 184         ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
 185                 PCI_CR_BAR13MASK);
 186         /*use 8 dw burst length */
 187         ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 188         ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 189         wmb();
 190
 191         /* setup irq line */
 192         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
 193         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
 194
 195         /* toggle reset pin */
 196         if (reset_gpio) {
 197                 gpiod_set_value_cansleep(reset_gpio, 1);
 198                 wmb();
 199                 mdelay(1);
 200                 gpiod_set_value_cansleep(reset_gpio, 0);
 201         }
 202         return 0;
 203 }
 204
 205 static int ltq_pci_probe(struct platform_device *pdev)
 206 {
 207         pci_clear_flags(PCI_PROBE_ONLY);
 208
 209         ltq_pci_membase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
 210         if (IS_ERR(ltq_pci_membase))
 211                 return PTR_ERR(ltq_pci_membase);
 212
 213         ltq_pci_mapped_cfg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
 214         if (IS_ERR(ltq_pci_mapped_cfg))
 215                 return PTR_ERR(ltq_pci_mapped_cfg);
 216
 217         ltq_pci_startup(pdev);
 218
 219         pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
 220         register_pci_controller(&pci_controller);
 221         return 0;
 222 }
 223
 224 static const struct of_device_id ltq_pci_match[] = {
 225         { .compatible = "lantiq,pci-xway" },
 226         {},
 227 };
 228
 229 static struct platform_driver ltq_pci_driver = {
 230         .probe = ltq_pci_probe,
 231         .driver = {
 232                 .name = "pci-xway",
 233                 .of_match_table = ltq_pci_match,
 234         },
 235 };
 236
 237 int __init pcibios_init(void)
 238 {
 239         int ret = platform_driver_register(&ltq_pci_driver);
 240         if (ret)
 241                 pr_info("pci-xway: Error registering platform driver!");
 242         return ret;
 243 }
 244
 245 arch_initcall(pcibios_init);