arch/riscv/kernel/sys_riscv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Regents of the University of California
   4  * Copyright (C) 2014 Darius Rad <darius@bluespec.com>
   5  * Copyright (C) 2017 SiFive
   6  */
   7
   8 #include <linux/syscalls.h>
   9 #include <asm/cacheflush.h>
  10
  11 static long riscv_sys_mmap(unsigned long addr, unsigned long len,
  12                            unsigned long prot, unsigned long flags,
  13                            unsigned long fd, off_t offset,
  14                            unsigned long page_shift_offset)
  15 {
  16         if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
  17                 return -EINVAL;
  18
  19         return ksys_mmap_pgoff(addr, len, prot, flags, fd,
  20                                offset >> (PAGE_SHIFT - page_shift_offset));
  21 }
  22
  23 #ifdef CONFIG_64BIT
  24 SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
  25         unsigned long, prot, unsigned long, flags,
  26         unsigned long, fd, unsigned long, offset)
  27 {
  28         return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0);
  29 }
  30 #endif
  31
  32 #if defined(CONFIG_32BIT) || defined(CONFIG_COMPAT)
  33 SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
  34         unsigned long, prot, unsigned long, flags,
  35         unsigned long, fd, unsigned long, offset)
  36 {
  37         /*
  38          * Note that the shift for mmap2 is constant (12),
  39          * regardless of PAGE_SIZE
  40          */
  41         return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12);
  42 }
  43 #endif
  44
  45 /*
  46  * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
  47  * having a direct 'fence.i' instruction available to userspace (which we
  48  * can't trap!), that's not actually viable when running on Linux because the
  49  * kernel might schedule a process on another hart.  There is no way for
  50  * userspace to handle this without invoking the kernel (as it doesn't know the
  51  * thread->hart mappings), so we've defined a RISC-V specific system call to
  52  * flush the instruction cache.
  53  *
  54  * sys_riscv_flush_icache() is defined to flush the instruction cache over an
  55  * address range, with the flush applying to either all threads or just the
  56  * caller.  We don't currently do anything with the address range, that's just
  57  * in there for forwards compatibility.
  58  */
  59 SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
  60         uintptr_t, flags)
  61 {
  62         /* Check the reserved flags. */
  63         if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))
  64                 return -EINVAL;
  65
  66         flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);
  67
  68         return 0;
  69 }
  70
  71 /* Not defined using SYSCALL_DEFINE0 to avoid error injection */
  72 asmlinkage long __riscv_sys_ni_syscall(const struct pt_regs *__unused)
  73 {
  74         return -ENOSYS;
  75 }