arch/riscv/kvm/vcpu_switch.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
   4  *
   5  * Authors:
   6  *     Anup Patel <anup.patel@wdc.com>
   7  */
   8
   9 #include <linux/linkage.h>
  10 #include <asm/asm.h>
  11 #include <asm/asm-offsets.h>
  12 #include <asm/csr.h>
  13
  14 .macro SAVE_HOST_GPRS
  15         /* Save Host GPRs (except A0 and T0-T6) */
  16         REG_S   ra, (KVM_ARCH_HOST_RA)(a0)
  17         REG_S   sp, (KVM_ARCH_HOST_SP)(a0)
  18         REG_S   gp, (KVM_ARCH_HOST_GP)(a0)
  19         REG_S   tp, (KVM_ARCH_HOST_TP)(a0)
  20         REG_S   s0, (KVM_ARCH_HOST_S0)(a0)
  21         REG_S   s1, (KVM_ARCH_HOST_S1)(a0)
  22         REG_S   a1, (KVM_ARCH_HOST_A1)(a0)
  23         REG_S   a2, (KVM_ARCH_HOST_A2)(a0)
  24         REG_S   a3, (KVM_ARCH_HOST_A3)(a0)
  25         REG_S   a4, (KVM_ARCH_HOST_A4)(a0)
  26         REG_S   a5, (KVM_ARCH_HOST_A5)(a0)
  27         REG_S   a6, (KVM_ARCH_HOST_A6)(a0)
  28         REG_S   a7, (KVM_ARCH_HOST_A7)(a0)
  29         REG_S   s2, (KVM_ARCH_HOST_S2)(a0)
  30         REG_S   s3, (KVM_ARCH_HOST_S3)(a0)
  31         REG_S   s4, (KVM_ARCH_HOST_S4)(a0)
  32         REG_S   s5, (KVM_ARCH_HOST_S5)(a0)
  33         REG_S   s6, (KVM_ARCH_HOST_S6)(a0)
  34         REG_S   s7, (KVM_ARCH_HOST_S7)(a0)
  35         REG_S   s8, (KVM_ARCH_HOST_S8)(a0)
  36         REG_S   s9, (KVM_ARCH_HOST_S9)(a0)
  37         REG_S   s10, (KVM_ARCH_HOST_S10)(a0)
  38         REG_S   s11, (KVM_ARCH_HOST_S11)(a0)
  39 .endm
  40
  41 .macro SAVE_HOST_AND_RESTORE_GUEST_CSRS __resume_addr
  42         /* Load Guest CSR values */
  43         REG_L   t0, (KVM_ARCH_GUEST_SSTATUS)(a0)
  44         la      t1, \__resume_addr
  45         REG_L   t2, (KVM_ARCH_GUEST_SEPC)(a0)
  46
  47         /* Save Host and Restore Guest SSTATUS */
  48         csrrw   t0, CSR_SSTATUS, t0
  49
  50         /* Save Host STVEC and change it to return path */
  51         csrrw   t1, CSR_STVEC, t1
  52
  53         /* Restore Guest SEPC */
  54         csrw    CSR_SEPC, t2
  55
  56         /* Save Host SSCRATCH and change it to struct kvm_vcpu_arch pointer */
  57         csrrw   t3, CSR_SSCRATCH, a0
  58
  59         /* Store Host CSR values */
  60         REG_S   t0, (KVM_ARCH_HOST_SSTATUS)(a0)
  61         REG_S   t1, (KVM_ARCH_HOST_STVEC)(a0)
  62         REG_S   t3, (KVM_ARCH_HOST_SSCRATCH)(a0)
  63 .endm
  64
  65 .macro RESTORE_GUEST_GPRS
  66         /* Restore Guest GPRs (except A0) */
  67         REG_L   ra, (KVM_ARCH_GUEST_RA)(a0)
  68         REG_L   sp, (KVM_ARCH_GUEST_SP)(a0)
  69         REG_L   gp, (KVM_ARCH_GUEST_GP)(a0)
  70         REG_L   tp, (KVM_ARCH_GUEST_TP)(a0)
  71         REG_L   t0, (KVM_ARCH_GUEST_T0)(a0)
  72         REG_L   t1, (KVM_ARCH_GUEST_T1)(a0)
  73         REG_L   t2, (KVM_ARCH_GUEST_T2)(a0)
  74         REG_L   s0, (KVM_ARCH_GUEST_S0)(a0)
  75         REG_L   s1, (KVM_ARCH_GUEST_S1)(a0)
  76         REG_L   a1, (KVM_ARCH_GUEST_A1)(a0)
  77         REG_L   a2, (KVM_ARCH_GUEST_A2)(a0)
  78         REG_L   a3, (KVM_ARCH_GUEST_A3)(a0)
  79         REG_L   a4, (KVM_ARCH_GUEST_A4)(a0)
  80         REG_L   a5, (KVM_ARCH_GUEST_A5)(a0)
  81         REG_L   a6, (KVM_ARCH_GUEST_A6)(a0)
  82         REG_L   a7, (KVM_ARCH_GUEST_A7)(a0)
  83         REG_L   s2, (KVM_ARCH_GUEST_S2)(a0)
  84         REG_L   s3, (KVM_ARCH_GUEST_S3)(a0)
  85         REG_L   s4, (KVM_ARCH_GUEST_S4)(a0)
  86         REG_L   s5, (KVM_ARCH_GUEST_S5)(a0)
  87         REG_L   s6, (KVM_ARCH_GUEST_S6)(a0)
  88         REG_L   s7, (KVM_ARCH_GUEST_S7)(a0)
  89         REG_L   s8, (KVM_ARCH_GUEST_S8)(a0)
  90         REG_L   s9, (KVM_ARCH_GUEST_S9)(a0)
  91         REG_L   s10, (KVM_ARCH_GUEST_S10)(a0)
  92         REG_L   s11, (KVM_ARCH_GUEST_S11)(a0)
  93         REG_L   t3, (KVM_ARCH_GUEST_T3)(a0)
  94         REG_L   t4, (KVM_ARCH_GUEST_T4)(a0)
  95         REG_L   t5, (KVM_ARCH_GUEST_T5)(a0)
  96         REG_L   t6, (KVM_ARCH_GUEST_T6)(a0)
  97
  98         /* Restore Guest A0 */
  99         REG_L   a0, (KVM_ARCH_GUEST_A0)(a0)
 100 .endm
 101
 102 .macro SAVE_GUEST_GPRS
 103         /* Swap Guest A0 with SSCRATCH */
 104         csrrw   a0, CSR_SSCRATCH, a0
 105
 106         /* Save Guest GPRs (except A0) */
 107         REG_S   ra, (KVM_ARCH_GUEST_RA)(a0)
 108         REG_S   sp, (KVM_ARCH_GUEST_SP)(a0)
 109         REG_S   gp, (KVM_ARCH_GUEST_GP)(a0)
 110         REG_S   tp, (KVM_ARCH_GUEST_TP)(a0)
 111         REG_S   t0, (KVM_ARCH_GUEST_T0)(a0)
 112         REG_S   t1, (KVM_ARCH_GUEST_T1)(a0)
 113         REG_S   t2, (KVM_ARCH_GUEST_T2)(a0)
 114         REG_S   s0, (KVM_ARCH_GUEST_S0)(a0)
 115         REG_S   s1, (KVM_ARCH_GUEST_S1)(a0)
 116         REG_S   a1, (KVM_ARCH_GUEST_A1)(a0)
 117         REG_S   a2, (KVM_ARCH_GUEST_A2)(a0)
 118         REG_S   a3, (KVM_ARCH_GUEST_A3)(a0)
 119         REG_S   a4, (KVM_ARCH_GUEST_A4)(a0)
 120         REG_S   a5, (KVM_ARCH_GUEST_A5)(a0)
 121         REG_S   a6, (KVM_ARCH_GUEST_A6)(a0)
 122         REG_S   a7, (KVM_ARCH_GUEST_A7)(a0)
 123         REG_S   s2, (KVM_ARCH_GUEST_S2)(a0)
 124         REG_S   s3, (KVM_ARCH_GUEST_S3)(a0)
 125         REG_S   s4, (KVM_ARCH_GUEST_S4)(a0)
 126         REG_S   s5, (KVM_ARCH_GUEST_S5)(a0)
 127         REG_S   s6, (KVM_ARCH_GUEST_S6)(a0)
 128         REG_S   s7, (KVM_ARCH_GUEST_S7)(a0)
 129         REG_S   s8, (KVM_ARCH_GUEST_S8)(a0)
 130         REG_S   s9, (KVM_ARCH_GUEST_S9)(a0)
 131         REG_S   s10, (KVM_ARCH_GUEST_S10)(a0)
 132         REG_S   s11, (KVM_ARCH_GUEST_S11)(a0)
 133         REG_S   t3, (KVM_ARCH_GUEST_T3)(a0)
 134         REG_S   t4, (KVM_ARCH_GUEST_T4)(a0)
 135         REG_S   t5, (KVM_ARCH_GUEST_T5)(a0)
 136         REG_S   t6, (KVM_ARCH_GUEST_T6)(a0)
 137 .endm
 138
 139 .macro SAVE_GUEST_AND_RESTORE_HOST_CSRS
 140         /* Load Host CSR values */
 141         REG_L   t0, (KVM_ARCH_HOST_STVEC)(a0)
 142         REG_L   t1, (KVM_ARCH_HOST_SSCRATCH)(a0)
 143         REG_L   t2, (KVM_ARCH_HOST_SSTATUS)(a0)
 144
 145         /* Save Guest A0 and Restore Host SSCRATCH */
 146         csrrw   t1, CSR_SSCRATCH, t1
 147
 148         /* Save Guest SEPC */
 149         csrr    t3, CSR_SEPC
 150
 151         /* Restore Host STVEC */
 152         csrw    CSR_STVEC, t0
 153
 154         /* Save Guest and Restore Host SSTATUS */
 155         csrrw   t2, CSR_SSTATUS, t2
 156
 157         /* Store Guest CSR values */
 158         REG_S   t1, (KVM_ARCH_GUEST_A0)(a0)
 159         REG_S   t2, (KVM_ARCH_GUEST_SSTATUS)(a0)
 160         REG_S   t3, (KVM_ARCH_GUEST_SEPC)(a0)
 161 .endm
 162
 163 .macro RESTORE_HOST_GPRS
 164         /* Restore Host GPRs (except A0 and T0-T6) */
 165         REG_L   ra, (KVM_ARCH_HOST_RA)(a0)
 166         REG_L   sp, (KVM_ARCH_HOST_SP)(a0)
 167         REG_L   gp, (KVM_ARCH_HOST_GP)(a0)
 168         REG_L   tp, (KVM_ARCH_HOST_TP)(a0)
 169         REG_L   s0, (KVM_ARCH_HOST_S0)(a0)
 170         REG_L   s1, (KVM_ARCH_HOST_S1)(a0)
 171         REG_L   a1, (KVM_ARCH_HOST_A1)(a0)
 172         REG_L   a2, (KVM_ARCH_HOST_A2)(a0)
 173         REG_L   a3, (KVM_ARCH_HOST_A3)(a0)
 174         REG_L   a4, (KVM_ARCH_HOST_A4)(a0)
 175         REG_L   a5, (KVM_ARCH_HOST_A5)(a0)
 176         REG_L   a6, (KVM_ARCH_HOST_A6)(a0)
 177         REG_L   a7, (KVM_ARCH_HOST_A7)(a0)
 178         REG_L   s2, (KVM_ARCH_HOST_S2)(a0)
 179         REG_L   s3, (KVM_ARCH_HOST_S3)(a0)
 180         REG_L   s4, (KVM_ARCH_HOST_S4)(a0)
 181         REG_L   s5, (KVM_ARCH_HOST_S5)(a0)
 182         REG_L   s6, (KVM_ARCH_HOST_S6)(a0)
 183         REG_L   s7, (KVM_ARCH_HOST_S7)(a0)
 184         REG_L   s8, (KVM_ARCH_HOST_S8)(a0)
 185         REG_L   s9, (KVM_ARCH_HOST_S9)(a0)
 186         REG_L   s10, (KVM_ARCH_HOST_S10)(a0)
 187         REG_L   s11, (KVM_ARCH_HOST_S11)(a0)
 188 .endm
 189
 190         .text
 191         .altmacro
 192         .option norelax
 193
 194         /*
 195          * Parameters:
 196          * A0 <= Pointer to struct kvm_vcpu_arch
 197          */
 198 SYM_FUNC_START(__kvm_riscv_switch_to)
 199         SAVE_HOST_GPRS
 200
 201         SAVE_HOST_AND_RESTORE_GUEST_CSRS .Lkvm_switch_return
 202
 203         RESTORE_GUEST_GPRS
 204
 205         /* Resume Guest using SRET */
 206         sret
 207
 208         /* Back to Host */
 209         .align 2
 210 .Lkvm_switch_return:
 211         SAVE_GUEST_GPRS
 212
 213         SAVE_GUEST_AND_RESTORE_HOST_CSRS
 214
 215         RESTORE_HOST_GPRS
 216
 217         /* Return to C code */
 218         ret
 219 SYM_FUNC_END(__kvm_riscv_switch_to)
 220
 221         /*
 222          * Parameters:
 223          * A0 <= Pointer to struct kvm_vcpu_arch
 224          * A1 <= SBI extension ID
 225          * A2 <= SBI function ID
 226          */
 227 SYM_FUNC_START(__kvm_riscv_nacl_switch_to)
 228         SAVE_HOST_GPRS
 229
 230         SAVE_HOST_AND_RESTORE_GUEST_CSRS .Lkvm_nacl_switch_return
 231
 232         /* Resume Guest using SBI nested acceleration */
 233         add     a6, a2, zero
 234         add     a7, a1, zero
 235         ecall
 236
 237         /* Back to Host */
 238         .align 2
 239 .Lkvm_nacl_switch_return:
 240         SAVE_GUEST_GPRS
 241
 242         SAVE_GUEST_AND_RESTORE_HOST_CSRS
 243
 244         RESTORE_HOST_GPRS
 245
 246         /* Return to C code */
 247         ret
 248 SYM_FUNC_END(__kvm_riscv_nacl_switch_to)
 249
 250 SYM_CODE_START(__kvm_riscv_unpriv_trap)
 251         /*
 252          * We assume that faulting unpriv load/store instruction is
 253          * 4-byte long and blindly increment SEPC by 4.
 254          *
 255          * The trap details will be saved at address pointed by 'A0'
 256          * register and we use 'A1' register as temporary.
 257          */
 258         csrr    a1, CSR_SEPC
 259         REG_S   a1, (KVM_ARCH_TRAP_SEPC)(a0)
 260         addi    a1, a1, 4
 261         csrw    CSR_SEPC, a1
 262         csrr    a1, CSR_SCAUSE
 263         REG_S   a1, (KVM_ARCH_TRAP_SCAUSE)(a0)
 264         csrr    a1, CSR_STVAL
 265         REG_S   a1, (KVM_ARCH_TRAP_STVAL)(a0)
 266         csrr    a1, CSR_HTVAL
 267         REG_S   a1, (KVM_ARCH_TRAP_HTVAL)(a0)
 268         csrr    a1, CSR_HTINST
 269         REG_S   a1, (KVM_ARCH_TRAP_HTINST)(a0)
 270         sret
 271 SYM_CODE_END(__kvm_riscv_unpriv_trap)
 272
 273 #ifdef  CONFIG_FPU
 274 SYM_FUNC_START(__kvm_riscv_fp_f_save)
 275         csrr t2, CSR_SSTATUS
 276         li t1, SR_FS
 277         csrs CSR_SSTATUS, t1
 278         frcsr t0
 279         fsw f0,  KVM_ARCH_FP_F_F0(a0)
 280         fsw f1,  KVM_ARCH_FP_F_F1(a0)
 281         fsw f2,  KVM_ARCH_FP_F_F2(a0)
 282         fsw f3,  KVM_ARCH_FP_F_F3(a0)
 283         fsw f4,  KVM_ARCH_FP_F_F4(a0)
 284         fsw f5,  KVM_ARCH_FP_F_F5(a0)
 285         fsw f6,  KVM_ARCH_FP_F_F6(a0)
 286         fsw f7,  KVM_ARCH_FP_F_F7(a0)
 287         fsw f8,  KVM_ARCH_FP_F_F8(a0)
 288         fsw f9,  KVM_ARCH_FP_F_F9(a0)
 289         fsw f10, KVM_ARCH_FP_F_F10(a0)
 290         fsw f11, KVM_ARCH_FP_F_F11(a0)
 291         fsw f12, KVM_ARCH_FP_F_F12(a0)
 292         fsw f13, KVM_ARCH_FP_F_F13(a0)
 293         fsw f14, KVM_ARCH_FP_F_F14(a0)
 294         fsw f15, KVM_ARCH_FP_F_F15(a0)
 295         fsw f16, KVM_ARCH_FP_F_F16(a0)
 296         fsw f17, KVM_ARCH_FP_F_F17(a0)
 297         fsw f18, KVM_ARCH_FP_F_F18(a0)
 298         fsw f19, KVM_ARCH_FP_F_F19(a0)
 299         fsw f20, KVM_ARCH_FP_F_F20(a0)
 300         fsw f21, KVM_ARCH_FP_F_F21(a0)
 301         fsw f22, KVM_ARCH_FP_F_F22(a0)
 302         fsw f23, KVM_ARCH_FP_F_F23(a0)
 303         fsw f24, KVM_ARCH_FP_F_F24(a0)
 304         fsw f25, KVM_ARCH_FP_F_F25(a0)
 305         fsw f26, KVM_ARCH_FP_F_F26(a0)
 306         fsw f27, KVM_ARCH_FP_F_F27(a0)
 307         fsw f28, KVM_ARCH_FP_F_F28(a0)
 308         fsw f29, KVM_ARCH_FP_F_F29(a0)
 309         fsw f30, KVM_ARCH_FP_F_F30(a0)
 310         fsw f31, KVM_ARCH_FP_F_F31(a0)
 311         sw t0, KVM_ARCH_FP_F_FCSR(a0)
 312         csrw CSR_SSTATUS, t2
 313         ret
 314 SYM_FUNC_END(__kvm_riscv_fp_f_save)
 315
 316 SYM_FUNC_START(__kvm_riscv_fp_d_save)
 317         csrr t2, CSR_SSTATUS
 318         li t1, SR_FS
 319         csrs CSR_SSTATUS, t1
 320         frcsr t0
 321         fsd f0,  KVM_ARCH_FP_D_F0(a0)
 322         fsd f1,  KVM_ARCH_FP_D_F1(a0)
 323         fsd f2,  KVM_ARCH_FP_D_F2(a0)
 324         fsd f3,  KVM_ARCH_FP_D_F3(a0)
 325         fsd f4,  KVM_ARCH_FP_D_F4(a0)
 326         fsd f5,  KVM_ARCH_FP_D_F5(a0)
 327         fsd f6,  KVM_ARCH_FP_D_F6(a0)
 328         fsd f7,  KVM_ARCH_FP_D_F7(a0)
 329         fsd f8,  KVM_ARCH_FP_D_F8(a0)
 330         fsd f9,  KVM_ARCH_FP_D_F9(a0)
 331         fsd f10, KVM_ARCH_FP_D_F10(a0)
 332         fsd f11, KVM_ARCH_FP_D_F11(a0)
 333         fsd f12, KVM_ARCH_FP_D_F12(a0)
 334         fsd f13, KVM_ARCH_FP_D_F13(a0)
 335         fsd f14, KVM_ARCH_FP_D_F14(a0)
 336         fsd f15, KVM_ARCH_FP_D_F15(a0)
 337         fsd f16, KVM_ARCH_FP_D_F16(a0)
 338         fsd f17, KVM_ARCH_FP_D_F17(a0)
 339         fsd f18, KVM_ARCH_FP_D_F18(a0)
 340         fsd f19, KVM_ARCH_FP_D_F19(a0)
 341         fsd f20, KVM_ARCH_FP_D_F20(a0)
 342         fsd f21, KVM_ARCH_FP_D_F21(a0)
 343         fsd f22, KVM_ARCH_FP_D_F22(a0)
 344         fsd f23, KVM_ARCH_FP_D_F23(a0)
 345         fsd f24, KVM_ARCH_FP_D_F24(a0)
 346         fsd f25, KVM_ARCH_FP_D_F25(a0)
 347         fsd f26, KVM_ARCH_FP_D_F26(a0)
 348         fsd f27, KVM_ARCH_FP_D_F27(a0)
 349         fsd f28, KVM_ARCH_FP_D_F28(a0)
 350         fsd f29, KVM_ARCH_FP_D_F29(a0)
 351         fsd f30, KVM_ARCH_FP_D_F30(a0)
 352         fsd f31, KVM_ARCH_FP_D_F31(a0)
 353         sw t0, KVM_ARCH_FP_D_FCSR(a0)
 354         csrw CSR_SSTATUS, t2
 355         ret
 356 SYM_FUNC_END(__kvm_riscv_fp_d_save)
 357
 358 SYM_FUNC_START(__kvm_riscv_fp_f_restore)
 359         csrr t2, CSR_SSTATUS
 360         li t1, SR_FS
 361         lw t0, KVM_ARCH_FP_F_FCSR(a0)
 362         csrs CSR_SSTATUS, t1
 363         flw f0,  KVM_ARCH_FP_F_F0(a0)
 364         flw f1,  KVM_ARCH_FP_F_F1(a0)
 365         flw f2,  KVM_ARCH_FP_F_F2(a0)
 366         flw f3,  KVM_ARCH_FP_F_F3(a0)
 367         flw f4,  KVM_ARCH_FP_F_F4(a0)
 368         flw f5,  KVM_ARCH_FP_F_F5(a0)
 369         flw f6,  KVM_ARCH_FP_F_F6(a0)
 370         flw f7,  KVM_ARCH_FP_F_F7(a0)
 371         flw f8,  KVM_ARCH_FP_F_F8(a0)
 372         flw f9,  KVM_ARCH_FP_F_F9(a0)
 373         flw f10, KVM_ARCH_FP_F_F10(a0)
 374         flw f11, KVM_ARCH_FP_F_F11(a0)
 375         flw f12, KVM_ARCH_FP_F_F12(a0)
 376         flw f13, KVM_ARCH_FP_F_F13(a0)
 377         flw f14, KVM_ARCH_FP_F_F14(a0)
 378         flw f15, KVM_ARCH_FP_F_F15(a0)
 379         flw f16, KVM_ARCH_FP_F_F16(a0)
 380         flw f17, KVM_ARCH_FP_F_F17(a0)
 381         flw f18, KVM_ARCH_FP_F_F18(a0)
 382         flw f19, KVM_ARCH_FP_F_F19(a0)
 383         flw f20, KVM_ARCH_FP_F_F20(a0)
 384         flw f21, KVM_ARCH_FP_F_F21(a0)
 385         flw f22, KVM_ARCH_FP_F_F22(a0)
 386         flw f23, KVM_ARCH_FP_F_F23(a0)
 387         flw f24, KVM_ARCH_FP_F_F24(a0)
 388         flw f25, KVM_ARCH_FP_F_F25(a0)
 389         flw f26, KVM_ARCH_FP_F_F26(a0)
 390         flw f27, KVM_ARCH_FP_F_F27(a0)
 391         flw f28, KVM_ARCH_FP_F_F28(a0)
 392         flw f29, KVM_ARCH_FP_F_F29(a0)
 393         flw f30, KVM_ARCH_FP_F_F30(a0)
 394         flw f31, KVM_ARCH_FP_F_F31(a0)
 395         fscsr t0
 396         csrw CSR_SSTATUS, t2
 397         ret
 398 SYM_FUNC_END(__kvm_riscv_fp_f_restore)
 399
 400 SYM_FUNC_START(__kvm_riscv_fp_d_restore)
 401         csrr t2, CSR_SSTATUS
 402         li t1, SR_FS
 403         lw t0, KVM_ARCH_FP_D_FCSR(a0)
 404         csrs CSR_SSTATUS, t1
 405         fld f0,  KVM_ARCH_FP_D_F0(a0)
 406         fld f1,  KVM_ARCH_FP_D_F1(a0)
 407         fld f2,  KVM_ARCH_FP_D_F2(a0)
 408         fld f3,  KVM_ARCH_FP_D_F3(a0)
 409         fld f4,  KVM_ARCH_FP_D_F4(a0)
 410         fld f5,  KVM_ARCH_FP_D_F5(a0)
 411         fld f6,  KVM_ARCH_FP_D_F6(a0)
 412         fld f7,  KVM_ARCH_FP_D_F7(a0)
 413         fld f8,  KVM_ARCH_FP_D_F8(a0)
 414         fld f9,  KVM_ARCH_FP_D_F9(a0)
 415         fld f10, KVM_ARCH_FP_D_F10(a0)
 416         fld f11, KVM_ARCH_FP_D_F11(a0)
 417         fld f12, KVM_ARCH_FP_D_F12(a0)
 418         fld f13, KVM_ARCH_FP_D_F13(a0)
 419         fld f14, KVM_ARCH_FP_D_F14(a0)
 420         fld f15, KVM_ARCH_FP_D_F15(a0)
 421         fld f16, KVM_ARCH_FP_D_F16(a0)
 422         fld f17, KVM_ARCH_FP_D_F17(a0)
 423         fld f18, KVM_ARCH_FP_D_F18(a0)
 424         fld f19, KVM_ARCH_FP_D_F19(a0)
 425         fld f20, KVM_ARCH_FP_D_F20(a0)
 426         fld f21, KVM_ARCH_FP_D_F21(a0)
 427         fld f22, KVM_ARCH_FP_D_F22(a0)
 428         fld f23, KVM_ARCH_FP_D_F23(a0)
 429         fld f24, KVM_ARCH_FP_D_F24(a0)
 430         fld f25, KVM_ARCH_FP_D_F25(a0)
 431         fld f26, KVM_ARCH_FP_D_F26(a0)
 432         fld f27, KVM_ARCH_FP_D_F27(a0)
 433         fld f28, KVM_ARCH_FP_D_F28(a0)
 434         fld f29, KVM_ARCH_FP_D_F29(a0)
 435         fld f30, KVM_ARCH_FP_D_F30(a0)
 436         fld f31, KVM_ARCH_FP_D_F31(a0)
 437         fscsr t0
 438         csrw CSR_SSTATUS, t2
 439         ret
 440 SYM_FUNC_END(__kvm_riscv_fp_d_restore)
 441 #endif