arch/sparc/include/asm/viking.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * viking.h:  Defines specific to the GNU/Viking MBUS module.
   4  *            This is SRMMU stuff.
   5  *
   6  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  */
   8 #ifndef _SPARC_VIKING_H
   9 #define _SPARC_VIKING_H
  10
  11 #include <asm/asi.h>
  12 #include <asm/mxcc.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/pgtsrmmu.h>
  15
  16 /* Bits in the SRMMU control register for GNU/Viking modules.
  17  *
  18  * -----------------------------------------------------------
  19  * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
  20  * -----------------------------------------------------------
  21  *  31     24 23-17 16 15 14 13 12 11  10  9  8  7  6-2  1  0
  22  *
  23  * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
  24  *                            1 = Twalks are cacheable in E-cache
  25  *
  26  * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
  27  * and never caches them internally (or so states the docs).  Therefore
  28  * for machines lacking an E-cache (ie. in MBUS mode) this bit must
  29  * remain cleared.
  30  *
  31  * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
  32  *                            1 = Passthru physical accesses cacheable
  33  *
  34  * This indicates whether accesses are cacheable when no cachable bit
  35  * is present in the pte when the processor is in boot-mode or the
  36  * access does not need pte's for translation (ie. pass-thru ASI's).
  37  * "Cachable" is only referring to E-cache (if present) and not the
  38  * on chip split I/D caches of the GNU/Viking.
  39  *
  40  * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
  41  *
  42  * This enables snooping on the GNU/Viking bus.  This must be on
  43  * for the hardware cache consistency mechanisms of the GNU/Viking
  44  * to work at all.  On non-mxcc GNU/Viking modules the split I/D
  45  * caches will snoop regardless of whether they are enabled, this
  46  * takes care of the case where the I or D or both caches are turned
  47  * off yet still contain valid data.  Note also that this bit does
  48  * not affect GNU/Viking store-buffer snoops, those happen if the
  49  * store-buffer is enabled no matter what.
  50  *
  51  * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
  52  *
  53  * This indicates whether the GNU/Viking is in boot-mode or not,
  54  * if it is then all instruction fetch physical addresses are
  55  * computed as 0xff0000000 + low 28 bits of requested address.
  56  * GNU/Viking boot-mode does not affect data accesses.  Also,
  57  * in boot mode instruction accesses bypass the split on chip I/D
  58  * caches, they may be cached by the GNU/MXCC if present and enabled.
  59  *
  60  * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
  61  *
  62  * This indicated the GNU/Viking configuration present.  If in
  63  * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache.  If it is
  64  * not then the GNU/Viking is on a module VBUS connected directly
  65  * to a GNU/MXCC cache controller.  The GNU/MXCC can be thus connected
  66  * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
  67  *
  68  * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
  69  *
  70  * The GNU/Viking store buffer allows the chip to continue execution
  71  * after a store even if the data cannot be placed in one of the
  72  * caches during that cycle.  If disabled, all stores operations
  73  * occur synchronously.
  74  *
  75  * IC: Instruction Cache -- 0 = off, 1 = on
  76  * DC: Data Cache -- 0 = off, 1 = 0n
  77  *
  78  * These bits enable the on-cpu GNU/Viking split I/D caches.  Note,
  79  * as mentioned above, these caches will snoop the bus in GNU/MBUS
  80  * configurations even when disabled to avoid data corruption.
  81  *
  82  * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
  83  * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
  84  *
  85  */
  86
  87 #define VIKING_MMUENABLE    0x00000001
  88 #define VIKING_NOFAULT      0x00000002
  89 #define VIKING_PSO          0x00000080
  90 #define VIKING_DCENABLE     0x00000100   /* Enable data cache */
  91 #define VIKING_ICENABLE     0x00000200   /* Enable instruction cache */
  92 #define VIKING_SBENABLE     0x00000400   /* Enable store buffer */
  93 #define VIKING_MMODE        0x00000800   /* MBUS mode */
  94 #define VIKING_PCENABLE     0x00001000   /* Enable parity checking */
  95 #define VIKING_BMODE        0x00002000
  96 #define VIKING_SPENABLE     0x00004000   /* Enable bus cache snooping */
  97 #define VIKING_ACENABLE     0x00008000   /* Enable alternate caching */
  98 #define VIKING_TCENABLE     0x00010000   /* Enable table-walks to be cached */
  99 #define VIKING_DPENABLE     0x00040000   /* Enable the data prefetcher */
 100
 101 /*
 102  * GNU/Viking Breakpoint Action Register fields.
 103  */
 104 #define VIKING_ACTION_MIX   0x00001000   /* Enable multiple instructions */
 105
 106 /*
 107  * GNU/Viking Cache Tags.
 108  */
 109 #define VIKING_PTAG_VALID   0x01000000   /* Cache block is valid */
 110 #define VIKING_PTAG_DIRTY   0x00010000   /* Block has been modified */
 111 #define VIKING_PTAG_SHARED  0x00000100   /* Shared with some other cache */
 112
 113 #ifndef __ASSEMBLY__
 114
 115 static inline void viking_flush_icache(void)
 116 {
 117         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
 118                              : /* no outputs */
 119                              : "i" (ASI_M_IC_FLCLEAR)
 120                              : "memory");
 121 }
 122
 123 static inline void viking_flush_dcache(void)
 124 {
 125         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
 126                              : /* no outputs */
 127                              : "i" (ASI_M_DC_FLCLEAR)
 128                              : "memory");
 129 }
 130
 131 static inline void viking_unlock_icache(void)
 132 {
 133         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 134                              : /* no outputs */
 135                              : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
 136                              : "memory");
 137 }
 138
 139 static inline void viking_unlock_dcache(void)
 140 {
 141         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 142                              : /* no outputs */
 143                              : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
 144                              : "memory");
 145 }
 146
 147 static inline void viking_set_bpreg(unsigned long regval)
 148 {
 149         __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
 150                              : /* no outputs */
 151                              : "r" (regval), "i" (ASI_M_ACTION)
 152                              : "memory");
 153 }
 154
 155 static inline unsigned long viking_get_bpreg(void)
 156 {
 157         unsigned long regval;
 158
 159         __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
 160                              : "=r" (regval)
 161                              : "i" (ASI_M_ACTION));
 162         return regval;
 163 }
 164
 165 static inline void viking_get_dcache_ptag(int set, int block,
 166                                               unsigned long *data)
 167 {
 168         unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
 169                              0x80000000;
 170         unsigned long info, page;
 171
 172         __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
 173                               "or %%g0, %%g2, %0\n\t"
 174                               "or %%g0, %%g3, %1\n\t"
 175                               : "=r" (info), "=r" (page)
 176                               : "r" (ptag), "i" (ASI_M_DATAC_TAG)
 177                               : "g2", "g3");
 178         data[0] = info;
 179         data[1] = page;
 180 }
 181
 182 static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
 183                                                    unsigned long *mxcc_cregp)
 184 {
 185         unsigned long mreg = *mregp;
 186         unsigned long mxcc_creg = *mxcc_cregp;
 187
 188         mreg &= ~(VIKING_PCENABLE);
 189         mxcc_creg &= ~(MXCC_CTL_PARE);
 190
 191         __asm__ __volatile__ ("set 1f, %%g2\n\t"
 192                               "andcc %%g2, 4, %%g0\n\t"
 193                               "bne 2f\n\t"
 194                               " nop\n"
 195                               "1:\n\t"
 196                               "sta %0, [%%g0] %3\n\t"
 197                               "sta %1, [%2] %4\n\t"
 198                               "b 1f\n\t"
 199                               " nop\n\t"
 200                               "nop\n"
 201                               "2:\n\t"
 202                               "sta %0, [%%g0] %3\n\t"
 203                               "sta %1, [%2] %4\n"
 204                               "1:\n\t"
 205                               : /* no output */
 206                               : "r" (mreg), "r" (mxcc_creg),
 207                                 "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
 208                                 "i" (ASI_M_MXCC)
 209                               : "g2", "memory", "cc");
 210         *mregp = mreg;
 211         *mxcc_cregp = mxcc_creg;
 212 }
 213
 214 static inline unsigned long viking_hwprobe(unsigned long vaddr)
 215 {
 216         unsigned long val;
 217
 218         vaddr &= PAGE_MASK;
 219         /* Probe all MMU entries. */
 220         __asm__ __volatile__("lda [%1] %2, %0\n\t"
 221                              : "=r" (val)
 222                              : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
 223         if (!val)
 224                 return 0;
 225
 226         /* Probe region. */
 227         __asm__ __volatile__("lda [%1] %2, %0\n\t"
 228                              : "=r" (val)
 229                              : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
 230         if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
 231                 vaddr &= ~PGDIR_MASK;
 232                 vaddr >>= PAGE_SHIFT;
 233                 return val | (vaddr << 8);
 234         }
 235
 236         /* Probe segment. */
 237         __asm__ __volatile__("lda [%1] %2, %0\n\t"
 238                              : "=r" (val)
 239                              : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
 240         if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
 241                 vaddr &= ~PMD_MASK;
 242                 vaddr >>= PAGE_SHIFT;
 243                 return val | (vaddr << 8);
 244         }
 245
 246         /* Probe page. */
 247         __asm__ __volatile__("lda [%1] %2, %0\n\t"
 248                              : "=r" (val)
 249                              : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
 250         return val;
 251 }
 252
 253 #endif /* !__ASSEMBLY__ */
 254
 255 #endif /* !(_SPARC_VIKING_H) */