drm/rockchip: vop2: Fix the windows switch between different layers
[drm/drm-misc.git] / arch / sparc / kernel / entry.h
blobc746c0fd5d6bd1222b2cabac923742475443c3d7
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ENTRY_H
3 #define _ENTRY_H
5 #include <linux/kernel.h>
6 #include <linux/types.h>
7 #include <linux/init.h>
9 /* irq */
10 void handler_irq(int irq, struct pt_regs *regs);
12 #ifdef CONFIG_SPARC32
13 /* traps */
14 void do_hw_interrupt(struct pt_regs *regs, unsigned long type);
15 void do_illegal_instruction(struct pt_regs *regs, unsigned long pc,
16 unsigned long npc, unsigned long psr);
18 void do_priv_instruction(struct pt_regs *regs, unsigned long pc,
19 unsigned long npc, unsigned long psr);
20 void do_memaccess_unaligned(struct pt_regs *regs, unsigned long pc,
21 unsigned long npc, unsigned long psr);
22 void do_fpd_trap(struct pt_regs *regs, unsigned long pc,
23 unsigned long npc, unsigned long psr);
24 void do_fpe_trap(struct pt_regs *regs, unsigned long pc,
25 unsigned long npc, unsigned long psr);
26 void handle_tag_overflow(struct pt_regs *regs, unsigned long pc,
27 unsigned long npc, unsigned long psr);
28 void handle_watchpoint(struct pt_regs *regs, unsigned long pc,
29 unsigned long npc, unsigned long psr);
30 void handle_reg_access(struct pt_regs *regs, unsigned long pc,
31 unsigned long npc, unsigned long psr);
32 void handle_cp_disabled(struct pt_regs *regs, unsigned long pc,
33 unsigned long npc, unsigned long psr);
34 void handle_cp_exception(struct pt_regs *regs, unsigned long pc,
35 unsigned long npc, unsigned long psr);
39 /* entry.S */
40 void fpsave(unsigned long *fpregs, unsigned long *fsr,
41 void *fpqueue, unsigned long *fpqdepth);
42 void fpload(unsigned long *fpregs, unsigned long *fsr);
44 #else /* CONFIG_SPARC32 */
46 #include <asm/trap_block.h>
48 struct popc_3insn_patch_entry {
49 unsigned int addr;
50 unsigned int insns[3];
52 extern struct popc_3insn_patch_entry __popc_3insn_patch,
53 __popc_3insn_patch_end;
55 struct popc_6insn_patch_entry {
56 unsigned int addr;
57 unsigned int insns[6];
59 extern struct popc_6insn_patch_entry __popc_6insn_patch,
60 __popc_6insn_patch_end;
62 struct pause_patch_entry {
63 unsigned int addr;
64 unsigned int insns[3];
66 extern struct pause_patch_entry __pause_3insn_patch,
67 __pause_3insn_patch_end;
69 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *,
70 struct sun4v_1insn_patch_entry *);
71 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *,
72 struct sun4v_2insn_patch_entry *);
73 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *,
74 struct sun4v_2insn_patch_entry *);
75 extern unsigned int dcache_parity_tl1_occurred;
76 extern unsigned int icache_parity_tl1_occurred;
78 asmlinkage void sparc_breakpoint(struct pt_regs *regs);
79 void timer_interrupt(int irq, struct pt_regs *regs);
81 void do_notify_resume(struct pt_regs *regs,
82 unsigned long orig_i0,
83 unsigned long thread_info_flags);
85 asmlinkage int syscall_trace_enter(struct pt_regs *regs);
86 asmlinkage void syscall_trace_leave(struct pt_regs *regs);
88 void bad_trap_tl1(struct pt_regs *regs, long lvl);
90 void do_fpieee(struct pt_regs *regs);
91 void do_fpother(struct pt_regs *regs);
92 void do_tof(struct pt_regs *regs);
93 void do_div0(struct pt_regs *regs);
94 void do_illegal_instruction(struct pt_regs *regs);
95 void mem_address_unaligned(struct pt_regs *regs,
96 unsigned long sfar,
97 unsigned long sfsr);
98 void sun4v_do_mna(struct pt_regs *regs,
99 unsigned long addr,
100 unsigned long type_ctx);
101 void do_privop(struct pt_regs *regs);
102 void do_privact(struct pt_regs *regs);
103 void do_cee(struct pt_regs *regs);
104 void do_div0_tl1(struct pt_regs *regs);
105 void do_fpieee_tl1(struct pt_regs *regs);
106 void do_fpother_tl1(struct pt_regs *regs);
107 void do_ill_tl1(struct pt_regs *regs);
108 void do_irq_tl1(struct pt_regs *regs);
109 void do_lddfmna_tl1(struct pt_regs *regs);
110 void do_stdfmna_tl1(struct pt_regs *regs);
111 void do_paw(struct pt_regs *regs);
112 void do_paw_tl1(struct pt_regs *regs);
113 void do_vaw(struct pt_regs *regs);
114 void do_vaw_tl1(struct pt_regs *regs);
115 void do_tof_tl1(struct pt_regs *regs);
116 void do_getpsr(struct pt_regs *regs);
118 void spitfire_insn_access_exception(struct pt_regs *regs,
119 unsigned long sfsr,
120 unsigned long sfar);
121 void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
122 unsigned long sfsr,
123 unsigned long sfar);
124 void spitfire_data_access_exception(struct pt_regs *regs,
125 unsigned long sfsr,
126 unsigned long sfar);
127 void spitfire_data_access_exception_tl1(struct pt_regs *regs,
128 unsigned long sfsr,
129 unsigned long sfar);
130 void spitfire_access_error(struct pt_regs *regs,
131 unsigned long status_encoded,
132 unsigned long afar);
134 void cheetah_fecc_handler(struct pt_regs *regs,
135 unsigned long afsr,
136 unsigned long afar);
137 void cheetah_cee_handler(struct pt_regs *regs,
138 unsigned long afsr,
139 unsigned long afar);
140 void cheetah_deferred_handler(struct pt_regs *regs,
141 unsigned long afsr,
142 unsigned long afar);
143 void cheetah_plus_parity_error(int type, struct pt_regs *regs);
145 void sun4v_insn_access_exception(struct pt_regs *regs,
146 unsigned long addr,
147 unsigned long type_ctx);
148 void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
149 unsigned long addr,
150 unsigned long type_ctx);
151 void sun4v_data_access_exception(struct pt_regs *regs,
152 unsigned long addr,
153 unsigned long type_ctx);
154 void sun4v_data_access_exception_tl1(struct pt_regs *regs,
155 unsigned long addr,
156 unsigned long type_ctx);
157 void sun4v_resum_error(struct pt_regs *regs,
158 unsigned long offset);
159 void sun4v_resum_overflow(struct pt_regs *regs);
160 void sun4v_nonresum_error(struct pt_regs *regs,
161 unsigned long offset);
162 void sun4v_nonresum_overflow(struct pt_regs *regs);
163 void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs,
164 unsigned long addr,
165 unsigned long context);
167 extern unsigned long sun4v_err_itlb_vaddr;
168 extern unsigned long sun4v_err_itlb_ctx;
169 extern unsigned long sun4v_err_itlb_pte;
170 extern unsigned long sun4v_err_itlb_error;
172 void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
174 extern unsigned long sun4v_err_dtlb_vaddr;
175 extern unsigned long sun4v_err_dtlb_ctx;
176 extern unsigned long sun4v_err_dtlb_pte;
177 extern unsigned long sun4v_err_dtlb_error;
179 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
180 void hypervisor_tlbop_error(unsigned long err,
181 unsigned long op);
182 void hypervisor_tlbop_error_xcall(unsigned long err,
183 unsigned long op);
185 /* WARNING: The error trap handlers in assembly know the precise
186 * layout of the following structure.
188 * C-level handlers in traps.c use this information to log the
189 * error and then determine how to recover (if possible).
191 struct cheetah_err_info {
192 /*0x00*/u64 afsr;
193 /*0x08*/u64 afar;
195 /* D-cache state */
196 /*0x10*/u64 dcache_data[4]; /* The actual data */
197 /*0x30*/u64 dcache_index; /* D-cache index */
198 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
199 /*0x40*/u64 dcache_utag; /* D-cache microtag */
200 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
202 /* I-cache state */
203 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
204 /*0x90*/u64 icache_index; /* I-cache index */
205 /*0x98*/u64 icache_tag; /* I-cache phys tag */
206 /*0xa0*/u64 icache_utag; /* I-cache microtag */
207 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
208 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
209 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
211 /* E-cache state */
212 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
213 /*0xe0*/u64 ecache_index; /* E-cache index */
214 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
216 /*0xf0*/u64 __pad[32 - 30];
218 #define CHAFSR_INVALID ((u64)-1L)
220 /* This is allocated at boot time based upon the largest hardware
221 * cpu ID in the system. We allocate two entries per cpu, one for
222 * TL==0 logging and one for TL >= 1 logging.
224 extern struct cheetah_err_info *cheetah_error_log;
226 /* UPA nodes send interrupt packet to UltraSparc with first data reg
227 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
228 * delivered. We must translate this into a non-vector IRQ so we can
229 * set the softint on this cpu.
231 * To make processing these packets efficient and race free we use
232 * an array of irq buckets below. The interrupt vector handler in
233 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
235 * If you make changes to ino_bucket, please update hand coded assembler
236 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
238 struct ino_bucket {
239 /*0x00*/unsigned long __irq_chain_pa;
241 /* Interrupt number assigned to this INO. */
242 /*0x08*/unsigned int __irq;
243 /*0x0c*/unsigned int __pad;
246 extern struct ino_bucket *ivector_table;
247 extern unsigned long ivector_table_pa;
249 void init_irqwork_curcpu(void);
250 void sun4v_register_mondo_queues(int this_cpu);
252 #endif /* CONFIG_SPARC32 */
253 #endif /* _ENTRY_H */