drivers/accel/habanalabs/gaudi2/gaudi2P.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2020-2022 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef GAUDI2P_H_
   9 #define GAUDI2P_H_
  10
  11 #include <uapi/drm/habanalabs_accel.h>
  12 #include "../common/habanalabs.h"
  13 #include <linux/habanalabs/hl_boot_if.h>
  14 #include "../include/gaudi2/gaudi2.h"
  15 #include "../include/gaudi2/gaudi2_packets.h"
  16 #include "../include/gaudi2/gaudi2_fw_if.h"
  17 #include "../include/gaudi2/gaudi2_async_events.h"
  18
  19 #define GAUDI2_LINUX_FW_FILE    "habanalabs/gaudi2/gaudi2-fit.itb"
  20 #define GAUDI2_BOOT_FIT_FILE    "habanalabs/gaudi2/gaudi2-boot-fit.itb"
  21
  22 #define GAUDI2_CPU_TIMEOUT_USEC         30000000        /* 30s */
  23
  24 #define NUMBER_OF_PDMA_QUEUES           2
  25 #define NUMBER_OF_EDMA_QUEUES           8
  26 #define NUMBER_OF_MME_QUEUES            4
  27 #define NUMBER_OF_TPC_QUEUES            25
  28 #define NUMBER_OF_NIC_QUEUES            24
  29 #define NUMBER_OF_ROT_QUEUES            2
  30 #define NUMBER_OF_CPU_QUEUES            1
  31
  32 #define NUMBER_OF_HW_QUEUES             ((NUMBER_OF_PDMA_QUEUES + \
  33                                         NUMBER_OF_EDMA_QUEUES + \
  34                                         NUMBER_OF_MME_QUEUES + \
  35                                         NUMBER_OF_TPC_QUEUES + \
  36                                         NUMBER_OF_NIC_QUEUES + \
  37                                         NUMBER_OF_ROT_QUEUES + \
  38                                         NUMBER_OF_CPU_QUEUES) * \
  39                                         NUM_OF_PQ_PER_QMAN)
  40
  41 #define NUMBER_OF_QUEUES                (NUMBER_OF_CPU_QUEUES + NUMBER_OF_HW_QUEUES)
  42
  43 #define DCORE_NUM_OF_SOB                \
  44         (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
  45         mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
  46
  47 #define DCORE_NUM_OF_MONITORS           \
  48         (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
  49         mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
  50
  51 #define NUMBER_OF_DEC           ((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC)
  52
  53 /* Map all arcs dccm + arc schedulers acp blocks */
  54 #define NUM_OF_USER_ACP_BLOCKS          (NUM_OF_SCHEDULER_ARC + 2)
  55 #define NUM_OF_USER_NIC_UMR_BLOCKS      15
  56 #define NUM_OF_EXPOSED_SM_BLOCKS        ((NUM_OF_DCORES - 1) * 2)
  57 #define NUM_USER_MAPPED_BLOCKS \
  58         (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
  59         NUM_OF_EXPOSED_SM_BLOCKS + \
  60         (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
  61
  62 /* Within the user mapped array, decoder entries start post all the ARC related
  63  * entries
  64  */
  65 #define USR_MAPPED_BLK_DEC_START_IDX \
  66         (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \
  67         (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
  68
  69 #define USR_MAPPED_BLK_SM_START_IDX \
  70         (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
  71         (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
  72
  73 #define SM_OBJS_BLOCK_SIZE              (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
  74                                          mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0)
  75
  76 #define GAUDI2_MAX_PENDING_CS           64
  77
  78 #if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS)
  79 #error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1"
  80 #endif
  81
  82 #define CORESIGHT_TIMEOUT_USEC                  100000          /* 100 ms */
  83
  84 #define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC         25000000        /* 25s */
  85 #define GAUDI2_PREBOOT_EXTENDED_REQ_TIMEOUT_USEC 85000000       /* 85s */
  86
  87 #define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC        10000000        /* 10s */
  88
  89 #define GAUDI2_NIC_CLK_FREQ                     450000000ull    /* 450 MHz */
  90
  91 #define DC_POWER_DEFAULT                        60000           /* 60W */
  92
  93 #define GAUDI2_HBM_NUM                          6
  94
  95 #define DMA_MAX_TRANSFER_SIZE                   U32_MAX
  96
  97 #define GAUDI2_DEFAULT_CARD_NAME                "HL225"
  98
  99 #define QMAN_STREAMS                            4
 100
 101 #define NUM_OF_MME_SBTE_PORTS                   5
 102 #define NUM_OF_MME_WB_PORTS                     2
 103
 104 #define GAUDI2_ENGINE_ID_DCORE_OFFSET \
 105         (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
 106
 107 /* DRAM Memory Map */
 108
 109 #define CPU_FW_IMAGE_SIZE                       0x10000000      /* 256MB */
 110 #define CPU_FW_IMAGE_ADDR                       DRAM_PHYS_BASE
 111 #define PMMU_PAGE_TABLES_SIZE                   0x10000000      /* 256MB */
 112 #define EDMA_PQS_SIZE                           SZ_2M
 113 #define EDMA_SCRATCHPAD_SIZE                    SZ_1M
 114 #define HMMU_PAGE_TABLES_SIZE                   SZ_1M
 115
 116 #define NIC_NUMBER_OF_PORTS                     NIC_NUMBER_OF_ENGINES
 117
 118 #define NUMBER_OF_PCIE_DEC                      2
 119 #define PCIE_DEC_SHIFT                          8
 120
 121 #define SRAM_USER_BASE_OFFSET                   0
 122
 123 /* cluster binning */
 124 #define MAX_FAULTY_HBMS                         1
 125 #define GAUDI2_XBAR_EDGE_FULL_MASK              0xF
 126 #define GAUDI2_EDMA_FULL_MASK                   0xFF
 127 #define GAUDI2_DRAM_FULL_MASK                   0x3F
 128
 129 /* Host virtual address space. */
 130
 131 #define VA_HOST_SPACE_PAGE_START                0xFFF0000000000000ull
 132 #define VA_HOST_SPACE_PAGE_END                  0xFFF0800000000000ull /* 140TB */
 133
 134 #define VA_HOST_SPACE_HPAGE_START               0xFFF0800000000000ull
 135 #define VA_HOST_SPACE_HPAGE_END                 0xFFF1000000000000ull /* 140TB */
 136
 137 /* 140TB */
 138 #define VA_HOST_SPACE_PAGE_SIZE         (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
 139
 140 /* 140TB */
 141 #define VA_HOST_SPACE_HPAGE_SIZE        (VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START)
 142
 143 #define VA_HOST_SPACE_SIZE              (VA_HOST_SPACE_PAGE_SIZE + VA_HOST_SPACE_HPAGE_SIZE)
 144
 145 #define HOST_SPACE_INTERNAL_CB_SZ               SZ_2M
 146
 147 /*
 148  * HBM virtual address space
 149  * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most.
 150  * No core separation is supported so we can have one chunk of virtual address
 151  * space just above the physical ones.
 152  * The virtual address space starts immediately after the end of the physical
 153  * address space which is determined at run-time.
 154  */
 155 #define VA_HBM_SPACE_END                0x1002000000000000ull
 156
 157 #define HW_CAP_PLL                      BIT_ULL(0)
 158 #define HW_CAP_DRAM                     BIT_ULL(1)
 159 #define HW_CAP_PMMU                     BIT_ULL(2)
 160 #define HW_CAP_CPU                      BIT_ULL(3)
 161 #define HW_CAP_MSIX                     BIT_ULL(4)
 162
 163 #define HW_CAP_CPU_Q                    BIT_ULL(5)
 164 #define HW_CAP_CPU_Q_SHIFT              5
 165
 166 #define HW_CAP_CLK_GATE                 BIT_ULL(6)
 167 #define HW_CAP_KDMA                     BIT_ULL(7)
 168 #define HW_CAP_SRAM_SCRAMBLER           BIT_ULL(8)
 169
 170 #define HW_CAP_DCORE0_DMMU0             BIT_ULL(9)
 171 #define HW_CAP_DCORE0_DMMU1             BIT_ULL(10)
 172 #define HW_CAP_DCORE0_DMMU2             BIT_ULL(11)
 173 #define HW_CAP_DCORE0_DMMU3             BIT_ULL(12)
 174 #define HW_CAP_DCORE1_DMMU0             BIT_ULL(13)
 175 #define HW_CAP_DCORE1_DMMU1             BIT_ULL(14)
 176 #define HW_CAP_DCORE1_DMMU2             BIT_ULL(15)
 177 #define HW_CAP_DCORE1_DMMU3             BIT_ULL(16)
 178 #define HW_CAP_DCORE2_DMMU0             BIT_ULL(17)
 179 #define HW_CAP_DCORE2_DMMU1             BIT_ULL(18)
 180 #define HW_CAP_DCORE2_DMMU2             BIT_ULL(19)
 181 #define HW_CAP_DCORE2_DMMU3             BIT_ULL(20)
 182 #define HW_CAP_DCORE3_DMMU0             BIT_ULL(21)
 183 #define HW_CAP_DCORE3_DMMU1             BIT_ULL(22)
 184 #define HW_CAP_DCORE3_DMMU2             BIT_ULL(23)
 185 #define HW_CAP_DCORE3_DMMU3             BIT_ULL(24)
 186 #define HW_CAP_DMMU_MASK                GENMASK_ULL(24, 9)
 187 #define HW_CAP_DMMU_SHIFT               9
 188 #define HW_CAP_PDMA_MASK                BIT_ULL(26)
 189 #define HW_CAP_EDMA_MASK                GENMASK_ULL(34, 27)
 190 #define HW_CAP_EDMA_SHIFT               27
 191 #define HW_CAP_MME_MASK                 GENMASK_ULL(38, 35)
 192 #define HW_CAP_MME_SHIFT                35
 193 #define HW_CAP_ROT_MASK                 GENMASK_ULL(40, 39)
 194 #define HW_CAP_ROT_SHIFT                39
 195 #define HW_CAP_HBM_SCRAMBLER_HW_RESET   BIT_ULL(41)
 196 #define HW_CAP_HBM_SCRAMBLER_SW_RESET   BIT_ULL(42)
 197 #define HW_CAP_HBM_SCRAMBLER_MASK       (HW_CAP_HBM_SCRAMBLER_HW_RESET | \
 198                                                 HW_CAP_HBM_SCRAMBLER_SW_RESET)
 199 #define HW_CAP_HBM_SCRAMBLER_SHIFT      41
 200 #define HW_CAP_RESERVED                 BIT(43)
 201 #define HW_CAP_MMU_MASK                 (HW_CAP_PMMU | HW_CAP_DMMU_MASK)
 202
 203 /* Range Registers */
 204 #define RR_TYPE_SHORT                   0
 205 #define RR_TYPE_LONG                    1
 206 #define RR_TYPE_SHORT_PRIV              2
 207 #define RR_TYPE_LONG_PRIV               3
 208 #define NUM_SHORT_LBW_RR                14
 209 #define NUM_LONG_LBW_RR                 4
 210 #define NUM_SHORT_HBW_RR                6
 211 #define NUM_LONG_HBW_RR                 4
 212
 213 /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */
 214 #define RAZWI_INITIATOR_X_SHIFT         0
 215 #define RAZWI_INITIATOR_X_MASK          0x1F
 216 #define RAZWI_INITIATOR_Y_SHIFT         5
 217 #define RAZWI_INITIATOR_Y_MASK          0xF
 218
 219 #define RTR_ID_X_Y(x, y) \
 220         ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
 221                 (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
 222
 223 /* decoders have separate mask */
 224 #define HW_CAP_DEC_SHIFT                0
 225 #define HW_CAP_DEC_MASK                 GENMASK_ULL(9, 0)
 226
 227 /* TPCs have separate mask */
 228 #define HW_CAP_TPC_SHIFT                0
 229 #define HW_CAP_TPC_MASK                 GENMASK_ULL(24, 0)
 230
 231 /* nics have separate mask */
 232 #define HW_CAP_NIC_SHIFT                0
 233 #define HW_CAP_NIC_MASK                 GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)
 234
 235 #define GAUDI2_ARC_PCI_MSB_ADDR(addr)   (((addr) & GENMASK_ULL(49, 28)) >> 28)
 236
 237 #define GAUDI2_SOB_INCREMENT_BY_ONE     (FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \
 238                                         FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1))
 239
 240 #define GAUDI2_NUM_TESTED_QS            (GAUDI2_QUEUE_ID_CPU_PQ - GAUDI2_QUEUE_ID_PDMA_0_0)
 241
 242
 243 enum gaudi2_reserved_sob_id {
 244         GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
 245         GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST =
 246                         GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
 247         GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
 248         GAUDI2_RESERVED_SOB_DEC_NRM_FIRST,
 249         GAUDI2_RESERVED_SOB_DEC_NRM_LAST =
 250                         GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
 251         GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST,
 252         GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST =
 253                         GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
 254         GAUDI2_RESERVED_SOB_NUMBER
 255 };
 256
 257 enum gaudi2_reserved_mon_id {
 258         GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST,
 259         GAUDI2_RESERVED_MON_CS_COMPLETION_LAST =
 260                         GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
 261         GAUDI2_RESERVED_MON_KDMA_COMPLETION,
 262         GAUDI2_RESERVED_MON_DEC_NRM_FIRST,
 263         GAUDI2_RESERVED_MON_DEC_NRM_LAST =
 264                         GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
 265         GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST,
 266         GAUDI2_RESERVED_MON_DEC_ABNRM_LAST =
 267                         GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
 268         GAUDI2_RESERVED_MON_NUMBER
 269 };
 270
 271 enum gaudi2_reserved_cq_id {
 272         GAUDI2_RESERVED_CQ_CS_COMPLETION,
 273         GAUDI2_RESERVED_CQ_KDMA_COMPLETION,
 274         GAUDI2_RESERVED_CQ_NUMBER
 275 };
 276
 277 /*
 278  * Gaudi2 subtitute TPCs Numbering
 279  * At most- two faulty TPCs are allowed
 280  * First replacement to a faulty TPC will be TPC24, second- TPC23
 281  */
 282 enum substitude_tpc {
 283         FAULTY_TPC_SUBTS_1_TPC_24,
 284         FAULTY_TPC_SUBTS_2_TPC_23,
 285         MAX_FAULTY_TPCS
 286 };
 287
 288 enum gaudi2_dma_core_id {
 289         DMA_CORE_ID_PDMA0, /* Dcore 0 */
 290         DMA_CORE_ID_PDMA1, /* Dcore 0 */
 291         DMA_CORE_ID_EDMA0, /* Dcore 0 */
 292         DMA_CORE_ID_EDMA1, /* Dcore 0 */
 293         DMA_CORE_ID_EDMA2, /* Dcore 1 */
 294         DMA_CORE_ID_EDMA3, /* Dcore 1 */
 295         DMA_CORE_ID_EDMA4, /* Dcore 2 */
 296         DMA_CORE_ID_EDMA5, /* Dcore 2 */
 297         DMA_CORE_ID_EDMA6, /* Dcore 3 */
 298         DMA_CORE_ID_EDMA7, /* Dcore 3 */
 299         DMA_CORE_ID_KDMA, /* Dcore 0 */
 300         DMA_CORE_ID_SIZE
 301 };
 302
 303 enum gaudi2_rotator_id {
 304         ROTATOR_ID_0,
 305         ROTATOR_ID_1,
 306         ROTATOR_ID_SIZE,
 307 };
 308
 309 enum gaudi2_mme_id {
 310         MME_ID_DCORE0,
 311         MME_ID_DCORE1,
 312         MME_ID_DCORE2,
 313         MME_ID_DCORE3,
 314         MME_ID_SIZE,
 315 };
 316
 317 enum gaudi2_tpc_id {
 318         TPC_ID_DCORE0_TPC0,
 319         TPC_ID_DCORE0_TPC1,
 320         TPC_ID_DCORE0_TPC2,
 321         TPC_ID_DCORE0_TPC3,
 322         TPC_ID_DCORE0_TPC4,
 323         TPC_ID_DCORE0_TPC5,
 324         TPC_ID_DCORE1_TPC0,
 325         TPC_ID_DCORE1_TPC1,
 326         TPC_ID_DCORE1_TPC2,
 327         TPC_ID_DCORE1_TPC3,
 328         TPC_ID_DCORE1_TPC4,
 329         TPC_ID_DCORE1_TPC5,
 330         TPC_ID_DCORE2_TPC0,
 331         TPC_ID_DCORE2_TPC1,
 332         TPC_ID_DCORE2_TPC2,
 333         TPC_ID_DCORE2_TPC3,
 334         TPC_ID_DCORE2_TPC4,
 335         TPC_ID_DCORE2_TPC5,
 336         TPC_ID_DCORE3_TPC0,
 337         TPC_ID_DCORE3_TPC1,
 338         TPC_ID_DCORE3_TPC2,
 339         TPC_ID_DCORE3_TPC3,
 340         TPC_ID_DCORE3_TPC4,
 341         TPC_ID_DCORE3_TPC5,
 342         /* the PCI TPC is placed last (mapped liked HW) */
 343         TPC_ID_DCORE0_TPC6,
 344         TPC_ID_SIZE,
 345 };
 346
 347 enum gaudi2_dec_id {
 348         DEC_ID_DCORE0_DEC0,
 349         DEC_ID_DCORE0_DEC1,
 350         DEC_ID_DCORE1_DEC0,
 351         DEC_ID_DCORE1_DEC1,
 352         DEC_ID_DCORE2_DEC0,
 353         DEC_ID_DCORE2_DEC1,
 354         DEC_ID_DCORE3_DEC0,
 355         DEC_ID_DCORE3_DEC1,
 356         DEC_ID_PCIE_VDEC0,
 357         DEC_ID_PCIE_VDEC1,
 358         DEC_ID_SIZE,
 359 };
 360
 361 enum gaudi2_hbm_id {
 362         HBM_ID0,
 363         HBM_ID1,
 364         HBM_ID2,
 365         HBM_ID3,
 366         HBM_ID4,
 367         HBM_ID5,
 368         HBM_ID_SIZE,
 369 };
 370
 371 /* specific EDMA enumeration */
 372 enum gaudi2_edma_id {
 373         EDMA_ID_DCORE0_INSTANCE0,
 374         EDMA_ID_DCORE0_INSTANCE1,
 375         EDMA_ID_DCORE1_INSTANCE0,
 376         EDMA_ID_DCORE1_INSTANCE1,
 377         EDMA_ID_DCORE2_INSTANCE0,
 378         EDMA_ID_DCORE2_INSTANCE1,
 379         EDMA_ID_DCORE3_INSTANCE0,
 380         EDMA_ID_DCORE3_INSTANCE1,
 381         EDMA_ID_SIZE,
 382 };
 383
 384 /* User interrupt count is aligned with HW CQ count.
 385  * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode
 386  */
 387 #define GAUDI2_NUM_USER_INTERRUPTS 64
 388 #define GAUDI2_NUM_RESERVED_INTERRUPTS 1
 389 #define GAUDI2_TOTAL_USER_INTERRUPTS (GAUDI2_NUM_USER_INTERRUPTS + GAUDI2_NUM_RESERVED_INTERRUPTS)
 390
 391 enum gaudi2_irq_num {
 392         GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX,
 393         GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM,
 394         GAUDI2_IRQ_NUM_DCORE0_DEC0_ABNRM,
 395         GAUDI2_IRQ_NUM_DCORE0_DEC1_NRM,
 396         GAUDI2_IRQ_NUM_DCORE0_DEC1_ABNRM,
 397         GAUDI2_IRQ_NUM_DCORE1_DEC0_NRM,
 398         GAUDI2_IRQ_NUM_DCORE1_DEC0_ABNRM,
 399         GAUDI2_IRQ_NUM_DCORE1_DEC1_NRM,
 400         GAUDI2_IRQ_NUM_DCORE1_DEC1_ABNRM,
 401         GAUDI2_IRQ_NUM_DCORE2_DEC0_NRM,
 402         GAUDI2_IRQ_NUM_DCORE2_DEC0_ABNRM,
 403         GAUDI2_IRQ_NUM_DCORE2_DEC1_NRM,
 404         GAUDI2_IRQ_NUM_DCORE2_DEC1_ABNRM,
 405         GAUDI2_IRQ_NUM_DCORE3_DEC0_NRM,
 406         GAUDI2_IRQ_NUM_DCORE3_DEC0_ABNRM,
 407         GAUDI2_IRQ_NUM_DCORE3_DEC1_NRM,
 408         GAUDI2_IRQ_NUM_DCORE3_DEC1_ABNRM,
 409         GAUDI2_IRQ_NUM_SHARED_DEC0_NRM,
 410         GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM,
 411         GAUDI2_IRQ_NUM_SHARED_DEC1_NRM,
 412         GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM,
 413         GAUDI2_IRQ_NUM_DEC_LAST = GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM,
 414         GAUDI2_IRQ_NUM_COMPLETION,
 415         GAUDI2_IRQ_NUM_NIC_PORT_FIRST,
 416         GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
 417         GAUDI2_IRQ_NUM_TPC_ASSERT,
 418         GAUDI2_IRQ_NUM_EQ_ERROR,
 419         GAUDI2_IRQ_NUM_USER_FIRST,
 420         GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
 421         GAUDI2_IRQ_NUM_RESERVED_FIRST,
 422         GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_RESERVED_INTERRUPTS - 1),
 423         GAUDI2_IRQ_NUM_UNEXPECTED_ERROR = RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT,
 424         GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
 425 };
 426
 427 static_assert(GAUDI2_IRQ_NUM_USER_FIRST > GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM);
 428
 429 /**
 430  * struct dup_block_ctx - context to initialize unit instances across multiple
 431  *                        blocks where block can be either a dcore of duplicated
 432  *                        common module. this code relies on constant offsets
 433  *                        of blocks and unit instances in a block.
 434  * @instance_cfg_fn: instance specific configuration function.
 435  * @data: private configuration data.
 436  * @base: base address of the first instance in the first block.
 437  * @block_off: subsequent blocks address spacing.
 438  * @instance_off: subsequent block's instances address spacing.
 439  * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled).
 440  * @blocks: number of blocks.
 441  * @instances: unit instances per block.
 442  */
 443 struct dup_block_ctx {
 444         void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data);
 445         void *data;
 446         u64 base;
 447         u64 block_off;
 448         u64 instance_off;
 449         u64 enabled_mask;
 450         unsigned int blocks;
 451         unsigned int instances;
 452 };
 453
 454 /**
 455  * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the
 456  *                                  device queues.
 457  * @dma_addr: the address used by the HW for accessing the message.
 458  * @kern_addr: The address used by the driver for accessing the message.
 459  */
 460 struct gaudi2_queues_test_info {
 461         dma_addr_t dma_addr;
 462         void *kern_addr;
 463 };
 464
 465 /**
 466  * struct gaudi2_device - ASIC specific manage structure.
 467  * @cpucp_info_get: get information on device from CPU-CP
 468  * @mapped_blocks: array that holds the base address and size of all blocks
 469  *                 the user can map.
 470  * @lfsr_rand_seeds: array of MME ACC random seeds to set.
 471  * @hw_queues_lock: protects the H/W queues from concurrent access.
 472  * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory,
 473  *                             this memory region should be write-only.
 474  *                             currently used for HBW QMAN writes which is
 475  *                             redundant.
 476  * @scratchpad_bus_address: scratchpad bus address
 477  * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell.
 478  * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell.
 479  * @dram_bar_cur_addr: current address of DRAM PCI bar.
 480  * @hw_cap_initialized: This field contains a bit per H/W engine. When that
 481  *                      engine is initialized, that bit is set by the driver to
 482  *                      signal we can use this engine in later code paths.
 483  *                      Each bit is cleared upon reset of its corresponding H/W
 484  *                      engine.
 485  * @active_hw_arc: This field contains a bit per ARC of an H/W engine with
 486  *                 exception of TPC and NIC engines. Once an engine arc is
 487  *                 initialized, its respective bit is set. Driver can uniquely
 488  *                 identify each initialized ARC and use this information in
 489  *                 later code paths. Each respective bit is cleared upon reset
 490  *                 of its corresponding ARC of the H/W engine.
 491  * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine.
 492  *                      When that engine is initialized, that bit is set by
 493  *                      the driver to signal we can use this engine in later
 494  *                      code paths.
 495  *                      Each bit is cleared upon reset of its corresponding H/W
 496  *                      engine.
 497  * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine.
 498  *                      When that engine is initialized, that bit is set by
 499  *                      the driver to signal we can use this engine in later
 500  *                      code paths.
 501  *                      Each bit is cleared upon reset of its corresponding H/W
 502  *                      engine.
 503  * @active_tpc_arc: This field contains a bit per ARC of the TPC engines.
 504  *                  Once an engine arc is initialized, its respective bit is
 505  *                  set. Each respective bit is cleared upon reset of its
 506  *                  corresponding ARC of the TPC engine.
 507  * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine.
 508  * @active_nic_arc: This field contains a bit per ARC of the NIC engines.
 509  *                  Once an engine arc is initialized, its respective bit is
 510  *                  set. Each respective bit is cleared upon reset of its
 511  *                  corresponding ARC of the NIC engine.
 512  * @hw_events: array that holds all H/W events that are defined valid.
 513  * @events_stat: array that holds histogram of all received events.
 514  * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset.
 515  * @num_of_valid_hw_events: used to hold the number of valid H/W events.
 516  * @nic_ports: array that holds all NIC ports manage structures.
 517  * @nic_macros: array that holds all NIC macro manage structures.
 518  * @core_info: core info to be used by the Ethernet driver.
 519  * @aux_ops: functions for core <-> aux drivers communication.
 520  * @flush_db_fifo: flag to force flush DB FIFO after a write.
 521  * @hbm_cfg: HBM subsystem settings
 522  * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock.
 523  * @queues_test_info: information used by the driver when testing the HW queues.
 524  */
 525 struct gaudi2_device {
 526         int (*cpucp_info_get)(struct hl_device *hdev);
 527
 528         struct user_mapped_block        mapped_blocks[NUM_USER_MAPPED_BLOCKS];
 529         int                             lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS];
 530
 531         spinlock_t                      hw_queues_lock;
 532
 533         void                            *scratchpad_kernel_address;
 534         dma_addr_t                      scratchpad_bus_address;
 535
 536         void                            *virt_msix_db_cpu_addr;
 537         dma_addr_t                      virt_msix_db_dma_addr;
 538
 539         u64                             dram_bar_cur_addr;
 540         u64                             hw_cap_initialized;
 541         u64                             active_hw_arc;
 542         u64                             dec_hw_cap_initialized;
 543         u64                             tpc_hw_cap_initialized;
 544         u64                             active_tpc_arc;
 545         u64                             nic_hw_cap_initialized;
 546         u64                             active_nic_arc;
 547         u32                             hw_events[GAUDI2_EVENT_SIZE];
 548         u32                             events_stat[GAUDI2_EVENT_SIZE];
 549         u32                             events_stat_aggregate[GAUDI2_EVENT_SIZE];
 550         u32                             num_of_valid_hw_events;
 551
 552         /* Queue testing */
 553         struct gaudi2_queues_test_info  queues_test_info[GAUDI2_NUM_TESTED_QS];
 554 };
 555
 556 /*
 557  * Types of the Gaudi2 IP blocks, used by special blocks iterator.
 558  * Required for scenarios where only particular block types can be
 559  * addressed (e.g., special PLDM images).
 560  */
 561 enum gaudi2_block_types {
 562         GAUDI2_BLOCK_TYPE_PLL,
 563         GAUDI2_BLOCK_TYPE_RTR,
 564         GAUDI2_BLOCK_TYPE_CPU,
 565         GAUDI2_BLOCK_TYPE_HIF,
 566         GAUDI2_BLOCK_TYPE_HBM,
 567         GAUDI2_BLOCK_TYPE_NIC,
 568         GAUDI2_BLOCK_TYPE_PCIE,
 569         GAUDI2_BLOCK_TYPE_PCIE_PMA,
 570         GAUDI2_BLOCK_TYPE_PDMA,
 571         GAUDI2_BLOCK_TYPE_EDMA,
 572         GAUDI2_BLOCK_TYPE_PMMU,
 573         GAUDI2_BLOCK_TYPE_PSOC,
 574         GAUDI2_BLOCK_TYPE_ROT,
 575         GAUDI2_BLOCK_TYPE_ARC_FARM,
 576         GAUDI2_BLOCK_TYPE_DEC,
 577         GAUDI2_BLOCK_TYPE_MME,
 578         GAUDI2_BLOCK_TYPE_EU_BIST,
 579         GAUDI2_BLOCK_TYPE_SYNC_MNGR,
 580         GAUDI2_BLOCK_TYPE_STLB,
 581         GAUDI2_BLOCK_TYPE_TPC,
 582         GAUDI2_BLOCK_TYPE_HMMU,
 583         GAUDI2_BLOCK_TYPE_SRAM,
 584         GAUDI2_BLOCK_TYPE_XBAR,
 585         GAUDI2_BLOCK_TYPE_KDMA,
 586         GAUDI2_BLOCK_TYPE_XDMA,
 587         GAUDI2_BLOCK_TYPE_XFT,
 588         GAUDI2_BLOCK_TYPE_MAX
 589 };
 590
 591 extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE];
 592 extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE];
 593 extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE];
 594 extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE];
 595 extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES];
 596 extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE];
 597
 598 void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx);
 599 int gaudi2_coresight_init(struct hl_device *hdev);
 600 int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
 601 void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
 602 void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx);
 603 bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id);
 604 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
 605                                         u64 max_val);
 606 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
 607                                         u32 offended_addr);
 608 int gaudi2_init_security(struct hl_device *hdev);
 609 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev);
 610 int gaudi2_send_device_activity(struct hl_device *hdev, bool open);
 611
 612 #endif /* GAUDI2P_H_ */