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drm/nouveau: consume the return of large GSP message
[drm/drm-misc.git] / drivers / accel / habanalabs / gaudi2 / gaudi2_coresight.c
blob2423620ff358f1994c49d71898e99264e063e116
1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright 2019-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7 #include "gaudi2_coresight_regs.h"
8 #include <uapi/drm/habanalabs_accel.h>
9
10 #define GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 2000)
11 #define SPMU_MAX_COUNTERS 6
12
13 #define COMPONENT_ID_INVALID ((u32)(-1))
14 #define MAX_BMONS_PER_UNIT 8
15
16 enum gaudi2_hif_hmmu_id {
17 HMMU_ID_DCORE0_HMMU0,
18 HMMU_ID_DCORE0_HMMU1,
19 HMMU_ID_DCORE0_HMMU2,
20 HMMU_ID_DCORE0_HMMU3,
21 HMMU_ID_DCORE1_HMMU0,
22 HMMU_ID_DCORE1_HMMU1,
23 HMMU_ID_DCORE1_HMMU2,
24 HMMU_ID_DCORE1_HMMU3,
25 HMMU_ID_DCORE2_HMMU0,
26 HMMU_ID_DCORE2_HMMU1,
27 HMMU_ID_DCORE2_HMMU2,
28 HMMU_ID_DCORE2_HMMU3,
29 HMMU_ID_DCORE3_HMMU0,
30 HMMU_ID_DCORE3_HMMU1,
31 HMMU_ID_DCORE3_HMMU2,
32 HMMU_ID_DCORE3_HMMU3,
33 HMMU_ID_SIZE,
34 };
35
36 enum gaudi2_xbar_edge_id {
37 XBAR_EDGE_ID_DCORE0,
38 XBAR_EDGE_ID_DCORE1,
39 XBAR_EDGE_ID_DCORE2,
40 XBAR_EDGE_ID_DCORE3,
41 XBAR_EDGE_ID_SIZE
42 };
43
44 /**
45 * struct component_config_offsets - per cs_dbg unit - view off all related components indices
46 * @funnel_id: funnel id - index in debug_funnel_regs
47 * @etf_id: etf id - index in debug_etf_regs
48 * @stm_id: stm id - index in debug_stm_regs
49 * @spmu_id: spmu_id - index in debug_spmu_regs
50 * @bmon_count: number of bmons per unit
51 * @bmon_ids: array of bmon id (max size - MAX_BMONS_PER_UNIT) index in debug_bmon_regs
52 */
53 struct component_config_offsets {
54 u32 funnel_id;
55 u32 etf_id;
56 u32 stm_id;
57 u32 spmu_id;
58 u32 bmon_count;
59 u32 bmon_ids[MAX_BMONS_PER_UNIT];
60 };
61
62 static u64 debug_stm_regs[GAUDI2_STM_LAST + 1] = {
63 [GAUDI2_STM_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_STM_BASE,
64 [GAUDI2_STM_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_STM_BASE,
65 [GAUDI2_STM_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_STM_BASE,
66 [GAUDI2_STM_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_STM_BASE,
67 [GAUDI2_STM_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_STM_BASE,
68 [GAUDI2_STM_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_STM_BASE,
69 [GAUDI2_STM_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_STM_BASE,
70 [GAUDI2_STM_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_STM_BASE,
71 [GAUDI2_STM_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_STM_BASE,
72 [GAUDI2_STM_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_STM_BASE,
73 [GAUDI2_STM_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_STM_BASE,
74 [GAUDI2_STM_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_STM_BASE,
75 [GAUDI2_STM_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_STM_BASE,
76 [GAUDI2_STM_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_STM_BASE,
77 [GAUDI2_STM_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_STM_BASE,
78 [GAUDI2_STM_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_STM_BASE,
79 [GAUDI2_STM_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_STM_BASE,
80 [GAUDI2_STM_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_STM_BASE,
81 [GAUDI2_STM_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_STM_BASE,
82 [GAUDI2_STM_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_STM_BASE,
83 [GAUDI2_STM_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_STM_BASE,
84 [GAUDI2_STM_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_STM_BASE,
85 [GAUDI2_STM_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_STM_BASE,
86 [GAUDI2_STM_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_STM_BASE,
87 [GAUDI2_STM_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_STM_BASE,
88 [GAUDI2_STM_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_STM_BASE,
89 [GAUDI2_STM_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_STM_BASE,
90 [GAUDI2_STM_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_STM_BASE,
91 [GAUDI2_STM_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_STM_BASE,
92 [GAUDI2_STM_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_STM_BASE,
93 [GAUDI2_STM_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_STM_BASE,
94 [GAUDI2_STM_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_STM_BASE,
95 [GAUDI2_STM_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_STM_BASE,
96 [GAUDI2_STM_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_STM_BASE,
97 [GAUDI2_STM_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_STM_BASE,
98 [GAUDI2_STM_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_STM_BASE,
99 [GAUDI2_STM_DCORE0_SM] = mmDCORE0_SM_STM_BASE,
100 [GAUDI2_STM_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_STM_BASE,
101 [GAUDI2_STM_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_STM_BASE,
102 [GAUDI2_STM_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_STM_BASE,
103 [GAUDI2_STM_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_STM_BASE,
104 [GAUDI2_STM_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_STM_BASE,
105 [GAUDI2_STM_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_STM_BASE,
106 [GAUDI2_STM_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_STM_BASE,
107 [GAUDI2_STM_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_STM_BASE,
108 [GAUDI2_STM_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_STM_BASE,
109 [GAUDI2_STM_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_STM_BASE,
110 [GAUDI2_STM_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_STM_BASE,
111 [GAUDI2_STM_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_STM_BASE,
112 [GAUDI2_STM_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_STM_BASE,
113 [GAUDI2_STM_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_STM_BASE,
114 [GAUDI2_STM_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_STM_BASE,
115 [GAUDI2_STM_DCORE1_SM] = mmDCORE1_SM_STM_BASE,
116 [GAUDI2_STM_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_STM_BASE,
117 [GAUDI2_STM_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_STM_BASE,
118 [GAUDI2_STM_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_STM_BASE,
119 [GAUDI2_STM_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_STM_BASE,
120 [GAUDI2_STM_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_STM_BASE,
121 [GAUDI2_STM_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_STM_BASE,
122 [GAUDI2_STM_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_STM_BASE,
123 [GAUDI2_STM_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_STM_BASE,
124 [GAUDI2_STM_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_STM_BASE,
125 [GAUDI2_STM_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_STM_BASE,
126 [GAUDI2_STM_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_STM_BASE,
127 [GAUDI2_STM_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_STM_BASE,
128 [GAUDI2_STM_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_STM_BASE,
129 [GAUDI2_STM_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_STM_BASE,
130 [GAUDI2_STM_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_STM_BASE,
131 [GAUDI2_STM_DCORE2_SM] = mmDCORE2_SM_STM_BASE,
132 [GAUDI2_STM_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_STM_BASE,
133 [GAUDI2_STM_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_STM_BASE,
134 [GAUDI2_STM_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_STM_BASE,
135 [GAUDI2_STM_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_STM_BASE,
136 [GAUDI2_STM_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_STM_BASE,
137 [GAUDI2_STM_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_STM_BASE,
138 [GAUDI2_STM_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_STM_BASE,
139 [GAUDI2_STM_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_STM_BASE,
140 [GAUDI2_STM_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_STM_BASE,
141 [GAUDI2_STM_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_STM_BASE,
142 [GAUDI2_STM_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_STM_BASE,
143 [GAUDI2_STM_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_STM_BASE,
144 [GAUDI2_STM_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_STM_BASE,
145 [GAUDI2_STM_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_STM_BASE,
146 [GAUDI2_STM_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_STM_BASE,
147 [GAUDI2_STM_DCORE3_SM] = mmDCORE3_SM_STM_BASE,
148 [GAUDI2_STM_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_STM_BASE,
149 [GAUDI2_STM_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_STM_BASE,
150 [GAUDI2_STM_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_STM_BASE,
151 [GAUDI2_STM_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_STM_BASE,
152 [GAUDI2_STM_PCIE] = mmPCIE_STM_BASE,
153 [GAUDI2_STM_PSOC] = mmPSOC_STM_BASE,
154 [GAUDI2_STM_PSOC_ARC0_CS] = 0,
155 [GAUDI2_STM_PSOC_ARC1_CS] = 0,
156 [GAUDI2_STM_PDMA0_CS] = mmPDMA0_CS_STM_BASE,
157 [GAUDI2_STM_PDMA1_CS] = mmPDMA1_CS_STM_BASE,
158 [GAUDI2_STM_CPU] = mmCPU_STM_BASE,
159 [GAUDI2_STM_PMMU_CS] = mmPMMU_CS_STM_BASE,
160 [GAUDI2_STM_ROT0_CS] = mmROT0_CS_STM_BASE,
161 [GAUDI2_STM_ROT1_CS] = mmROT1_CS_STM_BASE,
162 [GAUDI2_STM_ARC_FARM_CS] = mmARC_FARM_CS_STM_BASE,
163 [GAUDI2_STM_KDMA_CS] = mmKDMA_CS_STM_BASE,
164 [GAUDI2_STM_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_STM_BASE,
165 [GAUDI2_STM_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_STM_BASE,
166 [GAUDI2_STM_HBM0_MC0_CS] = mmHBM0_MC0_CS_STM_BASE,
167 [GAUDI2_STM_HBM0_MC1_CS] = mmHBM0_MC1_CS_STM_BASE,
168 [GAUDI2_STM_HBM1_MC0_CS] = mmHBM1_MC0_CS_STM_BASE,
169 [GAUDI2_STM_HBM1_MC1_CS] = mmHBM1_MC1_CS_STM_BASE,
170 [GAUDI2_STM_HBM2_MC0_CS] = mmHBM2_MC0_CS_STM_BASE,
171 [GAUDI2_STM_HBM2_MC1_CS] = mmHBM2_MC1_CS_STM_BASE,
172 [GAUDI2_STM_HBM3_MC0_CS] = mmHBM3_MC0_CS_STM_BASE,
173 [GAUDI2_STM_HBM3_MC1_CS] = mmHBM3_MC1_CS_STM_BASE,
174 [GAUDI2_STM_HBM4_MC0_CS] = mmHBM4_MC0_CS_STM_BASE,
175 [GAUDI2_STM_HBM4_MC1_CS] = mmHBM4_MC1_CS_STM_BASE,
176 [GAUDI2_STM_HBM5_MC0_CS] = mmHBM5_MC0_CS_STM_BASE,
177 [GAUDI2_STM_HBM5_MC1_CS] = mmHBM5_MC1_CS_STM_BASE,
178 [GAUDI2_STM_NIC0_DBG_0] = mmNIC0_DBG_STM_0_BASE,
179 [GAUDI2_STM_NIC0_DBG_1] = mmNIC0_DBG_STM_1_BASE,
180 [GAUDI2_STM_NIC1_DBG_0] = mmNIC1_DBG_STM_0_BASE,
181 [GAUDI2_STM_NIC1_DBG_1] = mmNIC1_DBG_STM_1_BASE,
182 [GAUDI2_STM_NIC2_DBG_0] = mmNIC2_DBG_STM_0_BASE,
183 [GAUDI2_STM_NIC2_DBG_1] = mmNIC2_DBG_STM_1_BASE,
184 [GAUDI2_STM_NIC3_DBG_0] = mmNIC3_DBG_STM_0_BASE,
185 [GAUDI2_STM_NIC3_DBG_1] = mmNIC3_DBG_STM_1_BASE,
186 [GAUDI2_STM_NIC4_DBG_0] = mmNIC4_DBG_STM_0_BASE,
187 [GAUDI2_STM_NIC4_DBG_1] = mmNIC4_DBG_STM_1_BASE,
188 [GAUDI2_STM_NIC5_DBG_0] = mmNIC5_DBG_STM_0_BASE,
189 [GAUDI2_STM_NIC5_DBG_1] = mmNIC5_DBG_STM_1_BASE,
190 [GAUDI2_STM_NIC6_DBG_0] = mmNIC6_DBG_STM_0_BASE,
191 [GAUDI2_STM_NIC6_DBG_1] = mmNIC6_DBG_STM_1_BASE,
192 [GAUDI2_STM_NIC7_DBG_0] = mmNIC7_DBG_STM_0_BASE,
193 [GAUDI2_STM_NIC7_DBG_1] = mmNIC7_DBG_STM_1_BASE,
194 [GAUDI2_STM_NIC8_DBG_0] = mmNIC8_DBG_STM_0_BASE,
195 [GAUDI2_STM_NIC8_DBG_1] = mmNIC8_DBG_STM_1_BASE,
196 [GAUDI2_STM_NIC9_DBG_0] = mmNIC9_DBG_STM_0_BASE,
197 [GAUDI2_STM_NIC9_DBG_1] = mmNIC9_DBG_STM_1_BASE,
198 [GAUDI2_STM_NIC10_DBG_0] = mmNIC10_DBG_STM_0_BASE,
199 [GAUDI2_STM_NIC10_DBG_1] = mmNIC10_DBG_STM_1_BASE,
200 [GAUDI2_STM_NIC11_DBG_0] = mmNIC11_DBG_STM_0_BASE,
201 [GAUDI2_STM_NIC11_DBG_1] = mmNIC11_DBG_STM_1_BASE
202 };
203
204 static u64 debug_etf_regs[GAUDI2_ETF_LAST + 1] = {
205 [GAUDI2_ETF_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_ETF_BASE,
206 [GAUDI2_ETF_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_ETF_BASE,
207 [GAUDI2_ETF_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_ETF_BASE,
208 [GAUDI2_ETF_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_ETF_BASE,
209 [GAUDI2_ETF_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_ETF_BASE,
210 [GAUDI2_ETF_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_ETF_BASE,
211 [GAUDI2_ETF_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_ETF_BASE,
212 [GAUDI2_ETF_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_ETF_BASE,
213 [GAUDI2_ETF_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_ETF_BASE,
214 [GAUDI2_ETF_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_ETF_BASE,
215 [GAUDI2_ETF_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_ETF_BASE,
216 [GAUDI2_ETF_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_ETF_BASE,
217 [GAUDI2_ETF_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_ETF_BASE,
218 [GAUDI2_ETF_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_ETF_BASE,
219 [GAUDI2_ETF_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_ETF_BASE,
220 [GAUDI2_ETF_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_ETF_BASE,
221 [GAUDI2_ETF_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_ETF_BASE,
222 [GAUDI2_ETF_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_ETF_BASE,
223 [GAUDI2_ETF_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_ETF_BASE,
224 [GAUDI2_ETF_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_ETF_BASE,
225 [GAUDI2_ETF_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_ETF_BASE,
226 [GAUDI2_ETF_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_ETF_BASE,
227 [GAUDI2_ETF_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_ETF_BASE,
228 [GAUDI2_ETF_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_ETF_BASE,
229 [GAUDI2_ETF_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_ETF_BASE,
230 [GAUDI2_ETF_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_ETF_BASE,
231 [GAUDI2_ETF_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_ETF_BASE,
232 [GAUDI2_ETF_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_ETF_BASE,
233 [GAUDI2_ETF_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_ETF_BASE,
234 [GAUDI2_ETF_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_ETF_BASE,
235 [GAUDI2_ETF_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_ETF_BASE,
236 [GAUDI2_ETF_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_ETF_BASE,
237 [GAUDI2_ETF_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_ETF_BASE,
238 [GAUDI2_ETF_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_ETF_BASE,
239 [GAUDI2_ETF_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_ETF_BASE,
240 [GAUDI2_ETF_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_ETF_BASE,
241 [GAUDI2_ETF_DCORE0_SM] = mmDCORE0_SM_ETF_BASE,
242 [GAUDI2_ETF_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_ETF_BASE,
243 [GAUDI2_ETF_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_ETF_BASE,
244 [GAUDI2_ETF_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_ETF_BASE,
245 [GAUDI2_ETF_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_ETF_BASE,
246 [GAUDI2_ETF_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_ETF_BASE,
247 [GAUDI2_ETF_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_ETF_BASE,
248 [GAUDI2_ETF_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_ETF_BASE,
249 [GAUDI2_ETF_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_ETF_BASE,
250 [GAUDI2_ETF_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_ETF_BASE,
251 [GAUDI2_ETF_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_ETF_BASE,
252 [GAUDI2_ETF_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_ETF_BASE,
253 [GAUDI2_ETF_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_ETF_BASE,
254 [GAUDI2_ETF_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_ETF_BASE,
255 [GAUDI2_ETF_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_ETF_BASE,
256 [GAUDI2_ETF_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_ETF_BASE,
257 [GAUDI2_ETF_DCORE1_SM] = mmDCORE1_SM_ETF_BASE,
258 [GAUDI2_ETF_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_ETF_BASE,
259 [GAUDI2_ETF_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_ETF_BASE,
260 [GAUDI2_ETF_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_ETF_BASE,
261 [GAUDI2_ETF_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_ETF_BASE,
262 [GAUDI2_ETF_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_ETF_BASE,
263 [GAUDI2_ETF_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_ETF_BASE,
264 [GAUDI2_ETF_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_ETF_BASE,
265 [GAUDI2_ETF_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_ETF_BASE,
266 [GAUDI2_ETF_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_ETF_BASE,
267 [GAUDI2_ETF_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_ETF_BASE,
268 [GAUDI2_ETF_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_ETF_BASE,
269 [GAUDI2_ETF_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_ETF_BASE,
270 [GAUDI2_ETF_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_ETF_BASE,
271 [GAUDI2_ETF_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_ETF_BASE,
272 [GAUDI2_ETF_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_ETF_BASE,
273 [GAUDI2_ETF_DCORE2_SM] = mmDCORE2_SM_ETF_BASE,
274 [GAUDI2_ETF_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_ETF_BASE,
275 [GAUDI2_ETF_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_ETF_BASE,
276 [GAUDI2_ETF_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_ETF_BASE,
277 [GAUDI2_ETF_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_ETF_BASE,
278 [GAUDI2_ETF_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_ETF_BASE,
279 [GAUDI2_ETF_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_ETF_BASE,
280 [GAUDI2_ETF_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_ETF_BASE,
281 [GAUDI2_ETF_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_ETF_BASE,
282 [GAUDI2_ETF_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_ETF_BASE,
283 [GAUDI2_ETF_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_ETF_BASE,
284 [GAUDI2_ETF_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_ETF_BASE,
285 [GAUDI2_ETF_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_ETF_BASE,
286 [GAUDI2_ETF_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_ETF_BASE,
287 [GAUDI2_ETF_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_ETF_BASE,
288 [GAUDI2_ETF_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_ETF_BASE,
289 [GAUDI2_ETF_DCORE3_SM] = mmDCORE3_SM_ETF_BASE,
290 [GAUDI2_ETF_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_ETF_BASE,
291 [GAUDI2_ETF_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_ETF_BASE,
292 [GAUDI2_ETF_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_ETF_BASE,
293 [GAUDI2_ETF_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_ETF_BASE,
294 [GAUDI2_ETF_PCIE] = mmPCIE_ETF_BASE,
295 [GAUDI2_ETF_PSOC] = mmPSOC_ETF_BASE,
296 [GAUDI2_ETF_PSOC_ARC0_CS] = 0,
297 [GAUDI2_ETF_PSOC_ARC1_CS] = 0,
298 [GAUDI2_ETF_PDMA0_CS] = mmPDMA0_CS_ETF_BASE,
299 [GAUDI2_ETF_PDMA1_CS] = mmPDMA1_CS_ETF_BASE,
300 [GAUDI2_ETF_CPU_0] = mmCPU_ETF_0_BASE,
301 [GAUDI2_ETF_CPU_1] = mmCPU_ETF_1_BASE,
302 [GAUDI2_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
303 [GAUDI2_ETF_PMMU_CS] = mmPMMU_CS_ETF_BASE,
304 [GAUDI2_ETF_ROT0_CS] = mmROT0_CS_ETF_BASE,
305 [GAUDI2_ETF_ROT1_CS] = mmROT1_CS_ETF_BASE,
306 [GAUDI2_ETF_ARC_FARM_CS] = mmARC_FARM_CS_ETF_BASE,
307 [GAUDI2_ETF_KDMA_CS] = mmKDMA_CS_ETF_BASE,
308 [GAUDI2_ETF_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_ETF_BASE,
309 [GAUDI2_ETF_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_ETF_BASE,
310 [GAUDI2_ETF_HBM0_MC0_CS] = mmHBM0_MC0_CS_ETF_BASE,
311 [GAUDI2_ETF_HBM0_MC1_CS] = mmHBM0_MC1_CS_ETF_BASE,
312 [GAUDI2_ETF_HBM1_MC0_CS] = mmHBM1_MC0_CS_ETF_BASE,
313 [GAUDI2_ETF_HBM1_MC1_CS] = mmHBM1_MC1_CS_ETF_BASE,
314 [GAUDI2_ETF_HBM2_MC0_CS] = mmHBM2_MC0_CS_ETF_BASE,
315 [GAUDI2_ETF_HBM2_MC1_CS] = mmHBM2_MC1_CS_ETF_BASE,
316 [GAUDI2_ETF_HBM3_MC0_CS] = mmHBM3_MC0_CS_ETF_BASE,
317 [GAUDI2_ETF_HBM3_MC1_CS] = mmHBM3_MC1_CS_ETF_BASE,
318 [GAUDI2_ETF_HBM4_MC0_CS] = mmHBM4_MC0_CS_ETF_BASE,
319 [GAUDI2_ETF_HBM4_MC1_CS] = mmHBM4_MC1_CS_ETF_BASE,
320 [GAUDI2_ETF_HBM5_MC0_CS] = mmHBM5_MC0_CS_ETF_BASE,
321 [GAUDI2_ETF_HBM5_MC1_CS] = mmHBM5_MC1_CS_ETF_BASE,
322 [GAUDI2_ETF_NIC0_DBG_0] = mmNIC0_DBG_ETF_0_BASE,
323 [GAUDI2_ETF_NIC0_DBG_1] = mmNIC0_DBG_ETF_1_BASE,
324 [GAUDI2_ETF_NIC1_DBG_0] = mmNIC1_DBG_ETF_0_BASE,
325 [GAUDI2_ETF_NIC1_DBG_1] = mmNIC1_DBG_ETF_1_BASE,
326 [GAUDI2_ETF_NIC2_DBG_0] = mmNIC2_DBG_ETF_0_BASE,
327 [GAUDI2_ETF_NIC2_DBG_1] = mmNIC2_DBG_ETF_1_BASE,
328 [GAUDI2_ETF_NIC3_DBG_0] = mmNIC3_DBG_ETF_0_BASE,
329 [GAUDI2_ETF_NIC3_DBG_1] = mmNIC3_DBG_ETF_1_BASE,
330 [GAUDI2_ETF_NIC4_DBG_0] = mmNIC4_DBG_ETF_0_BASE,
331 [GAUDI2_ETF_NIC4_DBG_1] = mmNIC4_DBG_ETF_1_BASE,
332 [GAUDI2_ETF_NIC5_DBG_0] = mmNIC5_DBG_ETF_0_BASE,
333 [GAUDI2_ETF_NIC5_DBG_1] = mmNIC5_DBG_ETF_1_BASE,
334 [GAUDI2_ETF_NIC6_DBG_0] = mmNIC6_DBG_ETF_0_BASE,
335 [GAUDI2_ETF_NIC6_DBG_1] = mmNIC6_DBG_ETF_1_BASE,
336 [GAUDI2_ETF_NIC7_DBG_0] = mmNIC7_DBG_ETF_0_BASE,
337 [GAUDI2_ETF_NIC7_DBG_1] = mmNIC7_DBG_ETF_1_BASE,
338 [GAUDI2_ETF_NIC8_DBG_0] = mmNIC8_DBG_ETF_0_BASE,
339 [GAUDI2_ETF_NIC8_DBG_1] = mmNIC8_DBG_ETF_1_BASE,
340 [GAUDI2_ETF_NIC9_DBG_0] = mmNIC9_DBG_ETF_0_BASE,
341 [GAUDI2_ETF_NIC9_DBG_1] = mmNIC9_DBG_ETF_1_BASE,
342 [GAUDI2_ETF_NIC10_DBG_0] = mmNIC10_DBG_ETF_0_BASE,
343 [GAUDI2_ETF_NIC10_DBG_1] = mmNIC10_DBG_ETF_1_BASE,
344 [GAUDI2_ETF_NIC11_DBG_0] = mmNIC11_DBG_ETF_0_BASE,
345 [GAUDI2_ETF_NIC11_DBG_1] = mmNIC11_DBG_ETF_1_BASE
346 };
347
348 static u64 debug_funnel_regs[GAUDI2_FUNNEL_LAST + 1] = {
349 [GAUDI2_FUNNEL_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_FUNNEL_BASE,
350 [GAUDI2_FUNNEL_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_FUNNEL_BASE,
351 [GAUDI2_FUNNEL_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_FUNNEL_BASE,
352 [GAUDI2_FUNNEL_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_FUNNEL_BASE,
353 [GAUDI2_FUNNEL_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_FUNNEL_BASE,
354 [GAUDI2_FUNNEL_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_FUNNEL_BASE,
355 [GAUDI2_FUNNEL_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_FUNNEL_BASE,
356 [GAUDI2_FUNNEL_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_FUNNEL_BASE,
357 [GAUDI2_FUNNEL_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_FUNNEL_BASE,
358 [GAUDI2_FUNNEL_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_FUNNEL_BASE,
359 [GAUDI2_FUNNEL_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_FUNNEL_BASE,
360 [GAUDI2_FUNNEL_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_FUNNEL_BASE,
361 [GAUDI2_FUNNEL_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_FUNNEL_BASE,
362 [GAUDI2_FUNNEL_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_FUNNEL_BASE,
363 [GAUDI2_FUNNEL_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_FUNNEL_BASE,
364 [GAUDI2_FUNNEL_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_FUNNEL_BASE,
365 [GAUDI2_FUNNEL_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_FUNNEL_BASE,
366 [GAUDI2_FUNNEL_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_FUNNEL_BASE,
367 [GAUDI2_FUNNEL_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_FUNNEL_BASE,
368 [GAUDI2_FUNNEL_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_FUNNEL_BASE,
369 [GAUDI2_FUNNEL_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_FUNNEL_BASE,
370 [GAUDI2_FUNNEL_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_FUNNEL_BASE,
371 [GAUDI2_FUNNEL_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_FUNNEL_BASE,
372 [GAUDI2_FUNNEL_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_FUNNEL_BASE,
373 [GAUDI2_FUNNEL_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_FUNNEL_BASE,
374 [GAUDI2_FUNNEL_DCORE0_XFT] = mmDCORE0_XFT_FUNNEL_BASE,
375 [GAUDI2_FUNNEL_DCORE0_TFT0] = mmDCORE0_TFT0_FUNNEL_BASE,
376 [GAUDI2_FUNNEL_DCORE0_TFT1] = mmDCORE0_TFT1_FUNNEL_BASE,
377 [GAUDI2_FUNNEL_DCORE0_TFT2] = mmDCORE0_TFT2_FUNNEL_BASE,
378 [GAUDI2_FUNNEL_DCORE0_RTR0] = mmDCORE0_RTR0_FUNNEL_BASE,
379 [GAUDI2_FUNNEL_DCORE0_RTR1] = mmDCORE0_RTR1_FUNNEL_BASE,
380 [GAUDI2_FUNNEL_DCORE0_RTR2] = mmDCORE0_RTR2_FUNNEL_BASE,
381 [GAUDI2_FUNNEL_DCORE0_RTR3] = mmDCORE0_RTR3_FUNNEL_BASE,
382 [GAUDI2_FUNNEL_DCORE0_RTR4] = mmDCORE0_RTR4_FUNNEL_BASE,
383 [GAUDI2_FUNNEL_DCORE0_MIF0] = mmDCORE0_MIF0_FUNNEL_BASE,
384 [GAUDI2_FUNNEL_DCORE0_RTR5] = mmDCORE0_RTR5_FUNNEL_BASE,
385 [GAUDI2_FUNNEL_DCORE0_MIF1] = mmDCORE0_MIF1_FUNNEL_BASE,
386 [GAUDI2_FUNNEL_DCORE0_RTR6] = mmDCORE0_RTR6_FUNNEL_BASE,
387 [GAUDI2_FUNNEL_DCORE0_MIF2] = mmDCORE0_MIF2_FUNNEL_BASE,
388 [GAUDI2_FUNNEL_DCORE0_RTR7] = mmDCORE0_RTR7_FUNNEL_BASE,
389 [GAUDI2_FUNNEL_DCORE0_MIF3] = mmDCORE0_MIF3_FUNNEL_BASE,
390 [GAUDI2_FUNNEL_DCORE1_XFT] = mmDCORE1_XFT_FUNNEL_BASE,
391 [GAUDI2_FUNNEL_DCORE1_TFT0] = mmDCORE1_TFT0_FUNNEL_BASE,
392 [GAUDI2_FUNNEL_DCORE1_TFT1] = mmDCORE1_TFT1_FUNNEL_BASE,
393 [GAUDI2_FUNNEL_DCORE1_TFT2] = mmDCORE1_TFT2_FUNNEL_BASE,
394 [GAUDI2_FUNNEL_DCORE1_RTR0] = mmDCORE1_RTR0_FUNNEL_BASE,
395 [GAUDI2_FUNNEL_DCORE1_MIF0] = mmDCORE1_MIF0_FUNNEL_BASE,
396 [GAUDI2_FUNNEL_DCORE1_RTR1] = mmDCORE1_RTR1_FUNNEL_BASE,
397 [GAUDI2_FUNNEL_DCORE1_MIF1] = mmDCORE1_MIF1_FUNNEL_BASE,
398 [GAUDI2_FUNNEL_DCORE1_RTR2] = mmDCORE1_RTR2_FUNNEL_BASE,
399 [GAUDI2_FUNNEL_DCORE1_MIF2] = mmDCORE1_MIF2_FUNNEL_BASE,
400 [GAUDI2_FUNNEL_DCORE1_RTR3] = mmDCORE1_RTR3_FUNNEL_BASE,
401 [GAUDI2_FUNNEL_DCORE1_MIF3] = mmDCORE1_MIF3_FUNNEL_BASE,
402 [GAUDI2_FUNNEL_DCORE1_RTR4] = mmDCORE1_RTR4_FUNNEL_BASE,
403 [GAUDI2_FUNNEL_DCORE1_RTR5] = mmDCORE1_RTR5_FUNNEL_BASE,
404 [GAUDI2_FUNNEL_DCORE1_RTR6] = mmDCORE1_RTR6_FUNNEL_BASE,
405 [GAUDI2_FUNNEL_DCORE1_RTR7] = mmDCORE1_RTR7_FUNNEL_BASE,
406 [GAUDI2_FUNNEL_DCORE2_XFT] = mmDCORE2_XFT_FUNNEL_BASE,
407 [GAUDI2_FUNNEL_DCORE2_TFT0] = mmDCORE2_TFT0_FUNNEL_BASE,
408 [GAUDI2_FUNNEL_DCORE2_TFT1] = mmDCORE2_TFT1_FUNNEL_BASE,
409 [GAUDI2_FUNNEL_DCORE2_TFT2] = mmDCORE2_TFT2_FUNNEL_BASE,
410 [GAUDI2_FUNNEL_DCORE2_RTR0] = mmDCORE2_RTR0_FUNNEL_BASE,
411 [GAUDI2_FUNNEL_DCORE2_RTR1] = mmDCORE2_RTR1_FUNNEL_BASE,
412 [GAUDI2_FUNNEL_DCORE2_RTR2] = mmDCORE2_RTR2_FUNNEL_BASE,
413 [GAUDI2_FUNNEL_DCORE2_RTR3] = mmDCORE2_RTR3_FUNNEL_BASE,
414 [GAUDI2_FUNNEL_DCORE2_RTR4] = mmDCORE2_RTR4_FUNNEL_BASE,
415 [GAUDI2_FUNNEL_DCORE2_MIF0] = mmDCORE2_MIF0_FUNNEL_BASE,
416 [GAUDI2_FUNNEL_DCORE2_RTR5] = mmDCORE2_RTR5_FUNNEL_BASE,
417 [GAUDI2_FUNNEL_DCORE2_MIF1] = mmDCORE2_MIF1_FUNNEL_BASE,
418 [GAUDI2_FUNNEL_DCORE2_RTR6] = mmDCORE2_RTR6_FUNNEL_BASE,
419 [GAUDI2_FUNNEL_DCORE2_MIF2] = mmDCORE2_MIF2_FUNNEL_BASE,
420 [GAUDI2_FUNNEL_DCORE2_RTR7] = mmDCORE2_RTR7_FUNNEL_BASE,
421 [GAUDI2_FUNNEL_DCORE2_MIF3] = mmDCORE2_MIF3_FUNNEL_BASE,
422 [GAUDI2_FUNNEL_DCORE3_XFT] = mmDCORE3_XFT_FUNNEL_BASE,
423 [GAUDI2_FUNNEL_DCORE3_TFT0] = mmDCORE3_TFT0_FUNNEL_BASE,
424 [GAUDI2_FUNNEL_DCORE3_TFT1] = mmDCORE3_TFT1_FUNNEL_BASE,
425 [GAUDI2_FUNNEL_DCORE3_TFT2] = mmDCORE3_TFT2_FUNNEL_BASE,
426 [GAUDI2_FUNNEL_DCORE3_RTR0] = mmDCORE3_RTR0_FUNNEL_BASE,
427 [GAUDI2_FUNNEL_DCORE3_MIF0] = mmDCORE3_MIF0_FUNNEL_BASE,
428 [GAUDI2_FUNNEL_DCORE3_RTR1] = mmDCORE3_RTR1_FUNNEL_BASE,
429 [GAUDI2_FUNNEL_DCORE3_MIF1] = mmDCORE3_MIF1_FUNNEL_BASE,
430 [GAUDI2_FUNNEL_DCORE3_RTR2] = mmDCORE3_RTR2_FUNNEL_BASE,
431 [GAUDI2_FUNNEL_DCORE3_MIF2] = mmDCORE3_MIF2_FUNNEL_BASE,
432 [GAUDI2_FUNNEL_DCORE3_RTR3] = mmDCORE3_RTR3_FUNNEL_BASE,
433 [GAUDI2_FUNNEL_DCORE3_MIF3] = mmDCORE3_MIF3_FUNNEL_BASE,
434 [GAUDI2_FUNNEL_DCORE3_RTR4] = mmDCORE3_RTR4_FUNNEL_BASE,
435 [GAUDI2_FUNNEL_DCORE3_RTR5] = mmDCORE3_RTR5_FUNNEL_BASE,
436 [GAUDI2_FUNNEL_DCORE3_RTR6] = mmDCORE3_RTR6_FUNNEL_BASE,
437 [GAUDI2_FUNNEL_DCORE3_RTR7] = mmDCORE3_RTR7_FUNNEL_BASE,
438 [GAUDI2_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
439 [GAUDI2_FUNNEL_PSOC_ARC0] = 0,
440 [GAUDI2_FUNNEL_PSOC_ARC1] = 0,
441 [GAUDI2_FUNNEL_XDMA] = mmXDMA_FUNNEL_BASE,
442 [GAUDI2_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
443 [GAUDI2_FUNNEL_PMMU] = mmPMMU_FUNNEL_BASE,
444 [GAUDI2_FUNNEL_PMMU_DEC] = mmPMMU_FUNNEL_DEC_BASE,
445 [GAUDI2_FUNNEL_DCORE0_XBAR_MID] = mmDCORE0_XBAR_MID_FUNNEL_BASE,
446 [GAUDI2_FUNNEL_DCORE0_XBAR_EDGE] = mmDCORE0_XBAR_EDGE_FUNNEL_BASE,
447 [GAUDI2_FUNNEL_DCORE1_XBAR_MID] = mmDCORE1_XBAR_MID_FUNNEL_BASE,
448 [GAUDI2_FUNNEL_DCORE1_XBAR_EDGE] = mmDCORE1_XBAR_EDGE_FUNNEL_BASE,
449 [GAUDI2_FUNNEL_DCORE2_XBAR_MID] = mmDCORE2_XBAR_MID_FUNNEL_BASE,
450 [GAUDI2_FUNNEL_DCORE2_XBAR_EDGE] = mmDCORE2_XBAR_EDGE_FUNNEL_BASE,
451 [GAUDI2_FUNNEL_DCORE3_XBAR_MID] = mmDCORE3_XBAR_MID_FUNNEL_BASE,
452 [GAUDI2_FUNNEL_DCORE3_XBAR_EDGE] = mmDCORE3_XBAR_EDGE_FUNNEL_BASE,
453 [GAUDI2_FUNNEL_ARC_FARM] = mmARC_FARM_FUNNEL_BASE,
454 [GAUDI2_FUNNEL_HBM0_MC0] = mmHBM0_MC0_FUNNEL_BASE,
455 [GAUDI2_FUNNEL_HBM0_MC1] = mmHBM0_MC1_FUNNEL_BASE,
456 [GAUDI2_FUNNEL_HBM1_MC0] = mmHBM1_MC0_FUNNEL_BASE,
457 [GAUDI2_FUNNEL_HBM1_MC1] = mmHBM1_MC1_FUNNEL_BASE,
458 [GAUDI2_FUNNEL_HBM2_MC0] = mmHBM2_MC0_FUNNEL_BASE,
459 [GAUDI2_FUNNEL_HBM2_MC1] = mmHBM2_MC1_FUNNEL_BASE,
460 [GAUDI2_FUNNEL_HBM3_MC0] = mmHBM3_MC0_FUNNEL_BASE,
461 [GAUDI2_FUNNEL_HBM3_MC1] = mmHBM3_MC1_FUNNEL_BASE,
462 [GAUDI2_FUNNEL_HBM4_MC0] = mmHBM4_MC0_FUNNEL_BASE,
463 [GAUDI2_FUNNEL_HBM4_MC1] = mmHBM4_MC1_FUNNEL_BASE,
464 [GAUDI2_FUNNEL_HBM5_MC0] = mmHBM5_MC0_FUNNEL_BASE,
465 [GAUDI2_FUNNEL_HBM5_MC1] = mmHBM5_MC1_FUNNEL_BASE,
466 [GAUDI2_FUNNEL_NIC0_DBG_TX] = mmNIC0_DBG_FUNNEL_TX_BASE,
467 [GAUDI2_FUNNEL_NIC0_DBG_NCH] = mmNIC0_DBG_FUNNEL_NCH_BASE,
468 [GAUDI2_FUNNEL_NIC1_DBG_TX] = mmNIC1_DBG_FUNNEL_TX_BASE,
469 [GAUDI2_FUNNEL_NIC1_DBG_NCH] = mmNIC1_DBG_FUNNEL_NCH_BASE,
470 [GAUDI2_FUNNEL_NIC2_DBG_TX] = mmNIC2_DBG_FUNNEL_TX_BASE,
471 [GAUDI2_FUNNEL_NIC2_DBG_NCH] = mmNIC2_DBG_FUNNEL_NCH_BASE,
472 [GAUDI2_FUNNEL_NIC3_DBG_TX] = mmNIC3_DBG_FUNNEL_TX_BASE,
473 [GAUDI2_FUNNEL_NIC3_DBG_NCH] = mmNIC3_DBG_FUNNEL_NCH_BASE,
474 [GAUDI2_FUNNEL_NIC4_DBG_TX] = mmNIC4_DBG_FUNNEL_TX_BASE,
475 [GAUDI2_FUNNEL_NIC4_DBG_NCH] = mmNIC4_DBG_FUNNEL_NCH_BASE,
476 [GAUDI2_FUNNEL_NIC5_DBG_TX] = mmNIC5_DBG_FUNNEL_TX_BASE,
477 [GAUDI2_FUNNEL_NIC5_DBG_NCH] = mmNIC5_DBG_FUNNEL_NCH_BASE,
478 [GAUDI2_FUNNEL_NIC6_DBG_TX] = mmNIC6_DBG_FUNNEL_TX_BASE,
479 [GAUDI2_FUNNEL_NIC6_DBG_NCH] = mmNIC6_DBG_FUNNEL_NCH_BASE,
480 [GAUDI2_FUNNEL_NIC7_DBG_TX] = mmNIC7_DBG_FUNNEL_TX_BASE,
481 [GAUDI2_FUNNEL_NIC7_DBG_NCH] = mmNIC7_DBG_FUNNEL_NCH_BASE,
482 [GAUDI2_FUNNEL_NIC8_DBG_TX] = mmNIC8_DBG_FUNNEL_TX_BASE,
483 [GAUDI2_FUNNEL_NIC8_DBG_NCH] = mmNIC8_DBG_FUNNEL_NCH_BASE,
484 [GAUDI2_FUNNEL_NIC9_DBG_TX] = mmNIC9_DBG_FUNNEL_TX_BASE,
485 [GAUDI2_FUNNEL_NIC9_DBG_NCH] = mmNIC9_DBG_FUNNEL_NCH_BASE,
486 [GAUDI2_FUNNEL_NIC10_DBG_TX] = mmNIC10_DBG_FUNNEL_TX_BASE,
487 [GAUDI2_FUNNEL_NIC10_DBG_NCH] = mmNIC10_DBG_FUNNEL_NCH_BASE,
488 [GAUDI2_FUNNEL_NIC11_DBG_TX] = mmNIC11_DBG_FUNNEL_TX_BASE,
489 [GAUDI2_FUNNEL_NIC11_DBG_NCH] = mmNIC11_DBG_FUNNEL_NCH_BASE
490 };
491
492 static u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = {
493 [GAUDI2_BMON_DCORE0_TPC0_EML_0] = mmDCORE0_TPC0_EML_BUSMON_0_BASE,
494 [GAUDI2_BMON_DCORE0_TPC0_EML_1] = mmDCORE0_TPC0_EML_BUSMON_1_BASE,
495 [GAUDI2_BMON_DCORE0_TPC0_EML_2] = mmDCORE0_TPC0_EML_BUSMON_2_BASE,
496 [GAUDI2_BMON_DCORE0_TPC0_EML_3] = mmDCORE0_TPC0_EML_BUSMON_3_BASE,
497 [GAUDI2_BMON_DCORE0_TPC1_EML_0] = mmDCORE0_TPC1_EML_BUSMON_0_BASE,
498 [GAUDI2_BMON_DCORE0_TPC1_EML_1] = mmDCORE0_TPC1_EML_BUSMON_1_BASE,
499 [GAUDI2_BMON_DCORE0_TPC1_EML_2] = mmDCORE0_TPC1_EML_BUSMON_2_BASE,
500 [GAUDI2_BMON_DCORE0_TPC1_EML_3] = mmDCORE0_TPC1_EML_BUSMON_3_BASE,
501 [GAUDI2_BMON_DCORE0_TPC2_EML_0] = mmDCORE0_TPC2_EML_BUSMON_0_BASE,
502 [GAUDI2_BMON_DCORE0_TPC2_EML_1] = mmDCORE0_TPC2_EML_BUSMON_1_BASE,
503 [GAUDI2_BMON_DCORE0_TPC2_EML_2] = mmDCORE0_TPC2_EML_BUSMON_2_BASE,
504 [GAUDI2_BMON_DCORE0_TPC2_EML_3] = mmDCORE0_TPC2_EML_BUSMON_3_BASE,
505 [GAUDI2_BMON_DCORE0_TPC3_EML_0] = mmDCORE0_TPC3_EML_BUSMON_0_BASE,
506 [GAUDI2_BMON_DCORE0_TPC3_EML_1] = mmDCORE0_TPC3_EML_BUSMON_1_BASE,
507 [GAUDI2_BMON_DCORE0_TPC3_EML_2] = mmDCORE0_TPC3_EML_BUSMON_2_BASE,
508 [GAUDI2_BMON_DCORE0_TPC3_EML_3] = mmDCORE0_TPC3_EML_BUSMON_3_BASE,
509 [GAUDI2_BMON_DCORE0_TPC4_EML_0] = mmDCORE0_TPC4_EML_BUSMON_0_BASE,
510 [GAUDI2_BMON_DCORE0_TPC4_EML_1] = mmDCORE0_TPC4_EML_BUSMON_1_BASE,
511 [GAUDI2_BMON_DCORE0_TPC4_EML_2] = mmDCORE0_TPC4_EML_BUSMON_2_BASE,
512 [GAUDI2_BMON_DCORE0_TPC4_EML_3] = mmDCORE0_TPC4_EML_BUSMON_3_BASE,
513 [GAUDI2_BMON_DCORE0_TPC5_EML_0] = mmDCORE0_TPC5_EML_BUSMON_0_BASE,
514 [GAUDI2_BMON_DCORE0_TPC5_EML_1] = mmDCORE0_TPC5_EML_BUSMON_1_BASE,
515 [GAUDI2_BMON_DCORE0_TPC5_EML_2] = mmDCORE0_TPC5_EML_BUSMON_2_BASE,
516 [GAUDI2_BMON_DCORE0_TPC5_EML_3] = mmDCORE0_TPC5_EML_BUSMON_3_BASE,
517 [GAUDI2_BMON_DCORE0_TPC6_EML_0] = mmDCORE0_TPC6_EML_BUSMON_0_BASE,
518 [GAUDI2_BMON_DCORE0_TPC6_EML_1] = mmDCORE0_TPC6_EML_BUSMON_1_BASE,
519 [GAUDI2_BMON_DCORE0_TPC6_EML_2] = mmDCORE0_TPC6_EML_BUSMON_2_BASE,
520 [GAUDI2_BMON_DCORE0_TPC6_EML_3] = mmDCORE0_TPC6_EML_BUSMON_3_BASE,
521 [GAUDI2_BMON_DCORE1_TPC0_EML_0] = mmDCORE1_TPC0_EML_BUSMON_0_BASE,
522 [GAUDI2_BMON_DCORE1_TPC0_EML_1] = mmDCORE1_TPC0_EML_BUSMON_1_BASE,
523 [GAUDI2_BMON_DCORE1_TPC0_EML_2] = mmDCORE1_TPC0_EML_BUSMON_2_BASE,
524 [GAUDI2_BMON_DCORE1_TPC0_EML_3] = mmDCORE1_TPC0_EML_BUSMON_3_BASE,
525 [GAUDI2_BMON_DCORE1_TPC1_EML_0] = mmDCORE1_TPC1_EML_BUSMON_0_BASE,
526 [GAUDI2_BMON_DCORE1_TPC1_EML_1] = mmDCORE1_TPC1_EML_BUSMON_1_BASE,
527 [GAUDI2_BMON_DCORE1_TPC1_EML_2] = mmDCORE1_TPC1_EML_BUSMON_2_BASE,
528 [GAUDI2_BMON_DCORE1_TPC1_EML_3] = mmDCORE1_TPC1_EML_BUSMON_3_BASE,
529 [GAUDI2_BMON_DCORE1_TPC2_EML_0] = mmDCORE1_TPC2_EML_BUSMON_0_BASE,
530 [GAUDI2_BMON_DCORE1_TPC2_EML_1] = mmDCORE1_TPC2_EML_BUSMON_1_BASE,
531 [GAUDI2_BMON_DCORE1_TPC2_EML_2] = mmDCORE1_TPC2_EML_BUSMON_2_BASE,
532 [GAUDI2_BMON_DCORE1_TPC2_EML_3] = mmDCORE1_TPC2_EML_BUSMON_3_BASE,
533 [GAUDI2_BMON_DCORE1_TPC3_EML_0] = mmDCORE1_TPC3_EML_BUSMON_0_BASE,
534 [GAUDI2_BMON_DCORE1_TPC3_EML_1] = mmDCORE1_TPC3_EML_BUSMON_1_BASE,
535 [GAUDI2_BMON_DCORE1_TPC3_EML_2] = mmDCORE1_TPC3_EML_BUSMON_2_BASE,
536 [GAUDI2_BMON_DCORE1_TPC3_EML_3] = mmDCORE1_TPC3_EML_BUSMON_3_BASE,
537 [GAUDI2_BMON_DCORE1_TPC4_EML_0] = mmDCORE1_TPC4_EML_BUSMON_0_BASE,
538 [GAUDI2_BMON_DCORE1_TPC4_EML_1] = mmDCORE1_TPC4_EML_BUSMON_1_BASE,
539 [GAUDI2_BMON_DCORE1_TPC4_EML_2] = mmDCORE1_TPC4_EML_BUSMON_2_BASE,
540 [GAUDI2_BMON_DCORE1_TPC4_EML_3] = mmDCORE1_TPC4_EML_BUSMON_3_BASE,
541 [GAUDI2_BMON_DCORE1_TPC5_EML_0] = mmDCORE1_TPC5_EML_BUSMON_0_BASE,
542 [GAUDI2_BMON_DCORE1_TPC5_EML_1] = mmDCORE1_TPC5_EML_BUSMON_1_BASE,
543 [GAUDI2_BMON_DCORE1_TPC5_EML_2] = mmDCORE1_TPC5_EML_BUSMON_2_BASE,
544 [GAUDI2_BMON_DCORE1_TPC5_EML_3] = mmDCORE1_TPC5_EML_BUSMON_3_BASE,
545 [GAUDI2_BMON_DCORE2_TPC0_EML_0] = mmDCORE2_TPC0_EML_BUSMON_0_BASE,
546 [GAUDI2_BMON_DCORE2_TPC0_EML_1] = mmDCORE2_TPC0_EML_BUSMON_1_BASE,
547 [GAUDI2_BMON_DCORE2_TPC0_EML_2] = mmDCORE2_TPC0_EML_BUSMON_2_BASE,
548 [GAUDI2_BMON_DCORE2_TPC0_EML_3] = mmDCORE2_TPC0_EML_BUSMON_3_BASE,
549 [GAUDI2_BMON_DCORE2_TPC1_EML_0] = mmDCORE2_TPC1_EML_BUSMON_0_BASE,
550 [GAUDI2_BMON_DCORE2_TPC1_EML_1] = mmDCORE2_TPC1_EML_BUSMON_1_BASE,
551 [GAUDI2_BMON_DCORE2_TPC1_EML_2] = mmDCORE2_TPC1_EML_BUSMON_2_BASE,
552 [GAUDI2_BMON_DCORE2_TPC1_EML_3] = mmDCORE2_TPC1_EML_BUSMON_3_BASE,
553 [GAUDI2_BMON_DCORE2_TPC2_EML_0] = mmDCORE2_TPC2_EML_BUSMON_0_BASE,
554 [GAUDI2_BMON_DCORE2_TPC2_EML_1] = mmDCORE2_TPC2_EML_BUSMON_1_BASE,
555 [GAUDI2_BMON_DCORE2_TPC2_EML_2] = mmDCORE2_TPC2_EML_BUSMON_2_BASE,
556 [GAUDI2_BMON_DCORE2_TPC2_EML_3] = mmDCORE2_TPC2_EML_BUSMON_3_BASE,
557 [GAUDI2_BMON_DCORE2_TPC3_EML_0] = mmDCORE2_TPC3_EML_BUSMON_0_BASE,
558 [GAUDI2_BMON_DCORE2_TPC3_EML_1] = mmDCORE2_TPC3_EML_BUSMON_1_BASE,
559 [GAUDI2_BMON_DCORE2_TPC3_EML_2] = mmDCORE2_TPC3_EML_BUSMON_2_BASE,
560 [GAUDI2_BMON_DCORE2_TPC3_EML_3] = mmDCORE2_TPC3_EML_BUSMON_3_BASE,
561 [GAUDI2_BMON_DCORE2_TPC4_EML_0] = mmDCORE2_TPC4_EML_BUSMON_0_BASE,
562 [GAUDI2_BMON_DCORE2_TPC4_EML_1] = mmDCORE2_TPC4_EML_BUSMON_1_BASE,
563 [GAUDI2_BMON_DCORE2_TPC4_EML_2] = mmDCORE2_TPC4_EML_BUSMON_2_BASE,
564 [GAUDI2_BMON_DCORE2_TPC4_EML_3] = mmDCORE2_TPC4_EML_BUSMON_3_BASE,
565 [GAUDI2_BMON_DCORE2_TPC5_EML_0] = mmDCORE2_TPC5_EML_BUSMON_0_BASE,
566 [GAUDI2_BMON_DCORE2_TPC5_EML_1] = mmDCORE2_TPC5_EML_BUSMON_1_BASE,
567 [GAUDI2_BMON_DCORE2_TPC5_EML_2] = mmDCORE2_TPC5_EML_BUSMON_2_BASE,
568 [GAUDI2_BMON_DCORE2_TPC5_EML_3] = mmDCORE2_TPC5_EML_BUSMON_3_BASE,
569 [GAUDI2_BMON_DCORE3_TPC0_EML_0] = mmDCORE3_TPC0_EML_BUSMON_0_BASE,
570 [GAUDI2_BMON_DCORE3_TPC0_EML_1] = mmDCORE3_TPC0_EML_BUSMON_1_BASE,
571 [GAUDI2_BMON_DCORE3_TPC0_EML_2] = mmDCORE3_TPC0_EML_BUSMON_2_BASE,
572 [GAUDI2_BMON_DCORE3_TPC0_EML_3] = mmDCORE3_TPC0_EML_BUSMON_3_BASE,
573 [GAUDI2_BMON_DCORE3_TPC1_EML_0] = mmDCORE3_TPC1_EML_BUSMON_0_BASE,
574 [GAUDI2_BMON_DCORE3_TPC1_EML_1] = mmDCORE3_TPC1_EML_BUSMON_1_BASE,
575 [GAUDI2_BMON_DCORE3_TPC1_EML_2] = mmDCORE3_TPC1_EML_BUSMON_2_BASE,
576 [GAUDI2_BMON_DCORE3_TPC1_EML_3] = mmDCORE3_TPC1_EML_BUSMON_3_BASE,
577 [GAUDI2_BMON_DCORE3_TPC2_EML_0] = mmDCORE3_TPC2_EML_BUSMON_0_BASE,
578 [GAUDI2_BMON_DCORE3_TPC2_EML_1] = mmDCORE3_TPC2_EML_BUSMON_1_BASE,
579 [GAUDI2_BMON_DCORE3_TPC2_EML_2] = mmDCORE3_TPC2_EML_BUSMON_2_BASE,
580 [GAUDI2_BMON_DCORE3_TPC2_EML_3] = mmDCORE3_TPC2_EML_BUSMON_3_BASE,
581 [GAUDI2_BMON_DCORE3_TPC3_EML_0] = mmDCORE3_TPC3_EML_BUSMON_0_BASE,
582 [GAUDI2_BMON_DCORE3_TPC3_EML_1] = mmDCORE3_TPC3_EML_BUSMON_1_BASE,
583 [GAUDI2_BMON_DCORE3_TPC3_EML_2] = mmDCORE3_TPC3_EML_BUSMON_2_BASE,
584 [GAUDI2_BMON_DCORE3_TPC3_EML_3] = mmDCORE3_TPC3_EML_BUSMON_3_BASE,
585 [GAUDI2_BMON_DCORE3_TPC4_EML_0] = mmDCORE3_TPC4_EML_BUSMON_0_BASE,
586 [GAUDI2_BMON_DCORE3_TPC4_EML_1] = mmDCORE3_TPC4_EML_BUSMON_1_BASE,
587 [GAUDI2_BMON_DCORE3_TPC4_EML_2] = mmDCORE3_TPC4_EML_BUSMON_2_BASE,
588 [GAUDI2_BMON_DCORE3_TPC4_EML_3] = mmDCORE3_TPC4_EML_BUSMON_3_BASE,
589 [GAUDI2_BMON_DCORE3_TPC5_EML_0] = mmDCORE3_TPC5_EML_BUSMON_0_BASE,
590 [GAUDI2_BMON_DCORE3_TPC5_EML_1] = mmDCORE3_TPC5_EML_BUSMON_1_BASE,
591 [GAUDI2_BMON_DCORE3_TPC5_EML_2] = mmDCORE3_TPC5_EML_BUSMON_2_BASE,
592 [GAUDI2_BMON_DCORE3_TPC5_EML_3] = mmDCORE3_TPC5_EML_BUSMON_3_BASE,
593 [GAUDI2_BMON_DCORE0_HMMU0_0] = mmDCORE0_HMMU0_BMON_0_BASE,
594 [GAUDI2_BMON_DCORE0_HMMU0_1] = mmDCORE0_HMMU0_BMON_1_BASE,
595 [GAUDI2_BMON_DCORE0_HMMU0_3] = mmDCORE0_HMMU0_BMON_3_BASE,
596 [GAUDI2_BMON_DCORE0_HMMU0_2] = mmDCORE0_HMMU0_BMON_2_BASE,
597 [GAUDI2_BMON_DCORE0_HMMU0_4] = mmDCORE0_HMMU0_BMON_4_BASE,
598 [GAUDI2_BMON_DCORE0_HMMU1_0] = mmDCORE0_HMMU1_BMON_0_BASE,
599 [GAUDI2_BMON_DCORE0_HMMU1_1] = mmDCORE0_HMMU1_BMON_1_BASE,
600 [GAUDI2_BMON_DCORE0_HMMU1_3] = mmDCORE0_HMMU1_BMON_3_BASE,
601 [GAUDI2_BMON_DCORE0_HMMU1_2] = mmDCORE0_HMMU1_BMON_2_BASE,
602 [GAUDI2_BMON_DCORE0_HMMU1_4] = mmDCORE0_HMMU1_BMON_4_BASE,
603 [GAUDI2_BMON_DCORE0_HMMU2_0] = mmDCORE0_HMMU2_BMON_0_BASE,
604 [GAUDI2_BMON_DCORE0_HMMU2_1] = mmDCORE0_HMMU2_BMON_1_BASE,
605 [GAUDI2_BMON_DCORE0_HMMU2_3] = mmDCORE0_HMMU2_BMON_3_BASE,
606 [GAUDI2_BMON_DCORE0_HMMU2_2] = mmDCORE0_HMMU2_BMON_2_BASE,
607 [GAUDI2_BMON_DCORE0_HMMU2_4] = mmDCORE0_HMMU2_BMON_4_BASE,
608 [GAUDI2_BMON_DCORE0_HMMU3_0] = mmDCORE0_HMMU3_BMON_0_BASE,
609 [GAUDI2_BMON_DCORE0_HMMU3_1] = mmDCORE0_HMMU3_BMON_1_BASE,
610 [GAUDI2_BMON_DCORE0_HMMU3_3] = mmDCORE0_HMMU3_BMON_3_BASE,
611 [GAUDI2_BMON_DCORE0_HMMU3_2] = mmDCORE0_HMMU3_BMON_2_BASE,
612 [GAUDI2_BMON_DCORE0_HMMU3_4] = mmDCORE0_HMMU3_BMON_4_BASE,
613 [GAUDI2_BMON_DCORE0_MME_CTRL_0] = mmDCORE0_MME_CTRL_BMON0_BASE,
614 [GAUDI2_BMON_DCORE0_MME_CTRL_1] = mmDCORE0_MME_CTRL_BMON1_BASE,
615 [GAUDI2_BMON_DCORE0_MME_CTRL_2] = mmDCORE0_MME_CTRL_BMON2_BASE,
616 [GAUDI2_BMON_DCORE0_MME_CTRL_3] = mmDCORE0_MME_CTRL_BMON3_BASE,
617 [GAUDI2_BMON_DCORE0_MME_SBTE0_0] = mmDCORE0_MME_SBTE0_BMON0_BASE,
618 [GAUDI2_BMON_DCORE0_MME_SBTE1_0] = mmDCORE0_MME_SBTE1_BMON0_BASE,
619 [GAUDI2_BMON_DCORE0_MME_SBTE2_0] = mmDCORE0_MME_SBTE2_BMON0_BASE,
620 [GAUDI2_BMON_DCORE0_MME_SBTE3_0] = mmDCORE0_MME_SBTE3_BMON0_BASE,
621 [GAUDI2_BMON_DCORE0_MME_SBTE4_0] = mmDCORE0_MME_SBTE4_BMON0_BASE,
622 [GAUDI2_BMON_DCORE0_MME_ACC_0] = mmDCORE0_MME_ACC_BMON0_BASE,
623 [GAUDI2_BMON_DCORE0_MME_ACC_1] = mmDCORE0_MME_ACC_BMON1_BASE,
624 [GAUDI2_BMON_DCORE0_SM] = mmDCORE0_SM_BMON_BASE,
625 [GAUDI2_BMON_DCORE0_SM_1] = mmDCORE0_SM_BMON1_BASE,
626 [GAUDI2_BMON_DCORE0_EDMA0_0] = mmDCORE0_EDMA0_BMON_0_BASE,
627 [GAUDI2_BMON_DCORE0_EDMA0_1] = mmDCORE0_EDMA0_BMON_1_BASE,
628 [GAUDI2_BMON_DCORE0_EDMA1_0] = mmDCORE0_EDMA1_BMON_0_BASE,
629 [GAUDI2_BMON_DCORE0_EDMA1_1] = mmDCORE0_EDMA1_BMON_1_BASE,
630 [GAUDI2_BMON_DCORE0_VDEC0_0] = mmDCORE0_VDEC0_BMON_0_BASE,
631 [GAUDI2_BMON_DCORE0_VDEC0_1] = mmDCORE0_VDEC0_BMON_1_BASE,
632 [GAUDI2_BMON_DCORE0_VDEC0_2] = mmDCORE0_VDEC0_BMON_2_BASE,
633 [GAUDI2_BMON_DCORE0_VDEC1_0] = mmDCORE0_VDEC1_BMON_0_BASE,
634 [GAUDI2_BMON_DCORE0_VDEC1_1] = mmDCORE0_VDEC1_BMON_1_BASE,
635 [GAUDI2_BMON_DCORE0_VDEC1_2] = mmDCORE0_VDEC1_BMON_2_BASE,
636 [GAUDI2_BMON_DCORE1_HMMU0_0] = mmDCORE1_HMMU0_BMON_0_BASE,
637 [GAUDI2_BMON_DCORE1_HMMU0_1] = mmDCORE1_HMMU0_BMON_1_BASE,
638 [GAUDI2_BMON_DCORE1_HMMU0_3] = mmDCORE1_HMMU0_BMON_3_BASE,
639 [GAUDI2_BMON_DCORE1_HMMU0_2] = mmDCORE1_HMMU0_BMON_2_BASE,
640 [GAUDI2_BMON_DCORE1_HMMU0_4] = mmDCORE1_HMMU0_BMON_4_BASE,
641 [GAUDI2_BMON_DCORE1_HMMU1_0] = mmDCORE1_HMMU1_BMON_0_BASE,
642 [GAUDI2_BMON_DCORE1_HMMU1_1] = mmDCORE1_HMMU1_BMON_1_BASE,
643 [GAUDI2_BMON_DCORE1_HMMU1_3] = mmDCORE1_HMMU1_BMON_3_BASE,
644 [GAUDI2_BMON_DCORE1_HMMU1_2] = mmDCORE1_HMMU1_BMON_2_BASE,
645 [GAUDI2_BMON_DCORE1_HMMU1_4] = mmDCORE1_HMMU1_BMON_4_BASE,
646 [GAUDI2_BMON_DCORE1_HMMU2_0] = mmDCORE1_HMMU2_BMON_0_BASE,
647 [GAUDI2_BMON_DCORE1_HMMU2_1] = mmDCORE1_HMMU2_BMON_1_BASE,
648 [GAUDI2_BMON_DCORE1_HMMU2_3] = mmDCORE1_HMMU2_BMON_3_BASE,
649 [GAUDI2_BMON_DCORE1_HMMU2_2] = mmDCORE1_HMMU2_BMON_2_BASE,
650 [GAUDI2_BMON_DCORE1_HMMU2_4] = mmDCORE1_HMMU2_BMON_4_BASE,
651 [GAUDI2_BMON_DCORE1_HMMU3_0] = mmDCORE1_HMMU3_BMON_0_BASE,
652 [GAUDI2_BMON_DCORE1_HMMU3_1] = mmDCORE1_HMMU3_BMON_1_BASE,
653 [GAUDI2_BMON_DCORE1_HMMU3_3] = mmDCORE1_HMMU3_BMON_3_BASE,
654 [GAUDI2_BMON_DCORE1_HMMU3_2] = mmDCORE1_HMMU3_BMON_2_BASE,
655 [GAUDI2_BMON_DCORE1_HMMU3_4] = mmDCORE1_HMMU3_BMON_4_BASE,
656 [GAUDI2_BMON_DCORE1_MME_CTRL_0] = mmDCORE1_MME_CTRL_BMON0_BASE,
657 [GAUDI2_BMON_DCORE1_MME_CTRL_1] = mmDCORE1_MME_CTRL_BMON1_BASE,
658 [GAUDI2_BMON_DCORE1_MME_CTRL_2] = mmDCORE1_MME_CTRL_BMON2_BASE,
659 [GAUDI2_BMON_DCORE1_MME_CTRL_3] = mmDCORE1_MME_CTRL_BMON3_BASE,
660 [GAUDI2_BMON_DCORE1_MME_SBTE0_0] = mmDCORE1_MME_SBTE0_BMON0_BASE,
661 [GAUDI2_BMON_DCORE1_MME_SBTE1_0] = mmDCORE1_MME_SBTE1_BMON0_BASE,
662 [GAUDI2_BMON_DCORE1_MME_SBTE2_0] = mmDCORE1_MME_SBTE2_BMON0_BASE,
663 [GAUDI2_BMON_DCORE1_MME_SBTE3_0] = mmDCORE1_MME_SBTE3_BMON0_BASE,
664 [GAUDI2_BMON_DCORE1_MME_SBTE4_0] = mmDCORE1_MME_SBTE4_BMON0_BASE,
665 [GAUDI2_BMON_DCORE1_MME_ACC_0] = mmDCORE1_MME_ACC_BMON0_BASE,
666 [GAUDI2_BMON_DCORE1_MME_ACC_1] = mmDCORE1_MME_ACC_BMON1_BASE,
667 [GAUDI2_BMON_DCORE1_SM] = mmDCORE1_SM_BMON_BASE,
668 [GAUDI2_BMON_DCORE1_SM_1] = mmDCORE1_SM_BMON1_BASE,
669 [GAUDI2_BMON_DCORE1_EDMA0_0] = mmDCORE1_EDMA0_BMON_0_BASE,
670 [GAUDI2_BMON_DCORE1_EDMA0_1] = mmDCORE1_EDMA0_BMON_1_BASE,
671 [GAUDI2_BMON_DCORE1_EDMA1_0] = mmDCORE1_EDMA1_BMON_0_BASE,
672 [GAUDI2_BMON_DCORE1_EDMA1_1] = mmDCORE1_EDMA1_BMON_1_BASE,
673 [GAUDI2_BMON_DCORE1_VDEC0_0] = mmDCORE1_VDEC0_BMON_0_BASE,
674 [GAUDI2_BMON_DCORE1_VDEC0_1] = mmDCORE1_VDEC0_BMON_1_BASE,
675 [GAUDI2_BMON_DCORE1_VDEC0_2] = mmDCORE1_VDEC0_BMON_2_BASE,
676 [GAUDI2_BMON_DCORE1_VDEC1_0] = mmDCORE1_VDEC1_BMON_0_BASE,
677 [GAUDI2_BMON_DCORE1_VDEC1_1] = mmDCORE1_VDEC1_BMON_1_BASE,
678 [GAUDI2_BMON_DCORE1_VDEC1_2] = mmDCORE1_VDEC1_BMON_2_BASE,
679 [GAUDI2_BMON_DCORE2_HMMU0_0] = mmDCORE2_HMMU0_BMON_0_BASE,
680 [GAUDI2_BMON_DCORE2_HMMU0_1] = mmDCORE2_HMMU0_BMON_1_BASE,
681 [GAUDI2_BMON_DCORE2_HMMU0_3] = mmDCORE2_HMMU0_BMON_3_BASE,
682 [GAUDI2_BMON_DCORE2_HMMU0_2] = mmDCORE2_HMMU0_BMON_2_BASE,
683 [GAUDI2_BMON_DCORE2_HMMU0_4] = mmDCORE2_HMMU0_BMON_4_BASE,
684 [GAUDI2_BMON_DCORE2_HMMU1_0] = mmDCORE2_HMMU1_BMON_0_BASE,
685 [GAUDI2_BMON_DCORE2_HMMU1_1] = mmDCORE2_HMMU1_BMON_1_BASE,
686 [GAUDI2_BMON_DCORE2_HMMU1_3] = mmDCORE2_HMMU1_BMON_3_BASE,
687 [GAUDI2_BMON_DCORE2_HMMU1_2] = mmDCORE2_HMMU1_BMON_2_BASE,
688 [GAUDI2_BMON_DCORE2_HMMU1_4] = mmDCORE2_HMMU1_BMON_4_BASE,
689 [GAUDI2_BMON_DCORE2_HMMU2_0] = mmDCORE2_HMMU2_BMON_0_BASE,
690 [GAUDI2_BMON_DCORE2_HMMU2_1] = mmDCORE2_HMMU2_BMON_1_BASE,
691 [GAUDI2_BMON_DCORE2_HMMU2_3] = mmDCORE2_HMMU2_BMON_3_BASE,
692 [GAUDI2_BMON_DCORE2_HMMU2_2] = mmDCORE2_HMMU2_BMON_2_BASE,
693 [GAUDI2_BMON_DCORE2_HMMU2_4] = mmDCORE2_HMMU2_BMON_4_BASE,
694 [GAUDI2_BMON_DCORE2_HMMU3_0] = mmDCORE2_HMMU3_BMON_0_BASE,
695 [GAUDI2_BMON_DCORE2_HMMU3_1] = mmDCORE2_HMMU3_BMON_1_BASE,
696 [GAUDI2_BMON_DCORE2_HMMU3_3] = mmDCORE2_HMMU3_BMON_3_BASE,
697 [GAUDI2_BMON_DCORE2_HMMU3_2] = mmDCORE2_HMMU3_BMON_2_BASE,
698 [GAUDI2_BMON_DCORE2_HMMU3_4] = mmDCORE2_HMMU3_BMON_4_BASE,
699 [GAUDI2_BMON_DCORE2_MME_CTRL_0] = mmDCORE2_MME_CTRL_BMON0_BASE,
700 [GAUDI2_BMON_DCORE2_MME_CTRL_1] = mmDCORE2_MME_CTRL_BMON1_BASE,
701 [GAUDI2_BMON_DCORE2_MME_CTRL_2] = mmDCORE2_MME_CTRL_BMON2_BASE,
702 [GAUDI2_BMON_DCORE2_MME_CTRL_3] = mmDCORE2_MME_CTRL_BMON3_BASE,
703 [GAUDI2_BMON_DCORE2_MME_SBTE0_0] = mmDCORE2_MME_SBTE0_BMON0_BASE,
704 [GAUDI2_BMON_DCORE2_MME_SBTE1_0] = mmDCORE2_MME_SBTE1_BMON0_BASE,
705 [GAUDI2_BMON_DCORE2_MME_SBTE2_0] = mmDCORE2_MME_SBTE2_BMON0_BASE,
706 [GAUDI2_BMON_DCORE2_MME_SBTE3_0] = mmDCORE2_MME_SBTE3_BMON0_BASE,
707 [GAUDI2_BMON_DCORE2_MME_SBTE4_0] = mmDCORE2_MME_SBTE4_BMON0_BASE,
708 [GAUDI2_BMON_DCORE2_MME_ACC_0] = mmDCORE2_MME_ACC_BMON0_BASE,
709 [GAUDI2_BMON_DCORE2_MME_ACC_1] = mmDCORE2_MME_ACC_BMON1_BASE,
710 [GAUDI2_BMON_DCORE2_SM] = mmDCORE2_SM_BMON_BASE,
711 [GAUDI2_BMON_DCORE2_SM_1] = mmDCORE2_SM_BMON1_BASE,
712 [GAUDI2_BMON_DCORE2_EDMA0_0] = mmDCORE2_EDMA0_BMON_0_BASE,
713 [GAUDI2_BMON_DCORE2_EDMA0_1] = mmDCORE2_EDMA0_BMON_1_BASE,
714 [GAUDI2_BMON_DCORE2_EDMA1_0] = mmDCORE2_EDMA1_BMON_0_BASE,
715 [GAUDI2_BMON_DCORE2_EDMA1_1] = mmDCORE2_EDMA1_BMON_1_BASE,
716 [GAUDI2_BMON_DCORE2_VDEC0_0] = mmDCORE2_VDEC0_BMON_0_BASE,
717 [GAUDI2_BMON_DCORE2_VDEC0_1] = mmDCORE2_VDEC0_BMON_1_BASE,
718 [GAUDI2_BMON_DCORE2_VDEC0_2] = mmDCORE2_VDEC0_BMON_2_BASE,
719 [GAUDI2_BMON_DCORE2_VDEC1_0] = mmDCORE2_VDEC1_BMON_0_BASE,
720 [GAUDI2_BMON_DCORE2_VDEC1_1] = mmDCORE2_VDEC1_BMON_1_BASE,
721 [GAUDI2_BMON_DCORE2_VDEC1_2] = mmDCORE2_VDEC1_BMON_2_BASE,
722 [GAUDI2_BMON_DCORE3_HMMU0_0] = mmDCORE3_HMMU0_BMON_0_BASE,
723 [GAUDI2_BMON_DCORE3_HMMU0_1] = mmDCORE3_HMMU0_BMON_1_BASE,
724 [GAUDI2_BMON_DCORE3_HMMU0_3] = mmDCORE3_HMMU0_BMON_3_BASE,
725 [GAUDI2_BMON_DCORE3_HMMU0_2] = mmDCORE3_HMMU0_BMON_2_BASE,
726 [GAUDI2_BMON_DCORE3_HMMU0_4] = mmDCORE3_HMMU0_BMON_4_BASE,
727 [GAUDI2_BMON_DCORE3_HMMU1_0] = mmDCORE3_HMMU1_BMON_0_BASE,
728 [GAUDI2_BMON_DCORE3_HMMU1_1] = mmDCORE3_HMMU1_BMON_1_BASE,
729 [GAUDI2_BMON_DCORE3_HMMU1_3] = mmDCORE3_HMMU1_BMON_3_BASE,
730 [GAUDI2_BMON_DCORE3_HMMU1_2] = mmDCORE3_HMMU1_BMON_2_BASE,
731 [GAUDI2_BMON_DCORE3_HMMU1_4] = mmDCORE3_HMMU1_BMON_4_BASE,
732 [GAUDI2_BMON_DCORE3_HMMU2_0] = mmDCORE3_HMMU2_BMON_0_BASE,
733 [GAUDI2_BMON_DCORE3_HMMU2_1] = mmDCORE3_HMMU2_BMON_1_BASE,
734 [GAUDI2_BMON_DCORE3_HMMU2_3] = mmDCORE3_HMMU2_BMON_3_BASE,
735 [GAUDI2_BMON_DCORE3_HMMU2_2] = mmDCORE3_HMMU2_BMON_2_BASE,
736 [GAUDI2_BMON_DCORE3_HMMU2_4] = mmDCORE3_HMMU2_BMON_4_BASE,
737 [GAUDI2_BMON_DCORE3_HMMU3_0] = mmDCORE3_HMMU3_BMON_0_BASE,
738 [GAUDI2_BMON_DCORE3_HMMU3_1] = mmDCORE3_HMMU3_BMON_1_BASE,
739 [GAUDI2_BMON_DCORE3_HMMU3_3] = mmDCORE3_HMMU3_BMON_3_BASE,
740 [GAUDI2_BMON_DCORE3_HMMU3_2] = mmDCORE3_HMMU3_BMON_2_BASE,
741 [GAUDI2_BMON_DCORE3_HMMU3_4] = mmDCORE3_HMMU3_BMON_4_BASE,
742 [GAUDI2_BMON_DCORE3_MME_CTRL_0] = mmDCORE3_MME_CTRL_BMON0_BASE,
743 [GAUDI2_BMON_DCORE3_MME_CTRL_1] = mmDCORE3_MME_CTRL_BMON1_BASE,
744 [GAUDI2_BMON_DCORE3_MME_CTRL_2] = mmDCORE3_MME_CTRL_BMON2_BASE,
745 [GAUDI2_BMON_DCORE3_MME_CTRL_3] = mmDCORE3_MME_CTRL_BMON3_BASE,
746 [GAUDI2_BMON_DCORE3_MME_SBTE0_0] = mmDCORE3_MME_SBTE0_BMON0_BASE,
747 [GAUDI2_BMON_DCORE3_MME_SBTE1_0] = mmDCORE3_MME_SBTE1_BMON0_BASE,
748 [GAUDI2_BMON_DCORE3_MME_SBTE2_0] = mmDCORE3_MME_SBTE2_BMON0_BASE,
749 [GAUDI2_BMON_DCORE3_MME_SBTE3_0] = mmDCORE3_MME_SBTE3_BMON0_BASE,
750 [GAUDI2_BMON_DCORE3_MME_SBTE4_0] = mmDCORE3_MME_SBTE4_BMON0_BASE,
751 [GAUDI2_BMON_DCORE3_MME_ACC_0] = mmDCORE3_MME_ACC_BMON0_BASE,
752 [GAUDI2_BMON_DCORE3_MME_ACC_1] = mmDCORE3_MME_ACC_BMON1_BASE,
753 [GAUDI2_BMON_DCORE3_SM] = mmDCORE3_SM_BMON_BASE,
754 [GAUDI2_BMON_DCORE3_SM_1] = mmDCORE3_SM_BMON1_BASE,
755 [GAUDI2_BMON_DCORE3_EDMA0_0] = mmDCORE3_EDMA0_BMON_0_BASE,
756 [GAUDI2_BMON_DCORE3_EDMA0_1] = mmDCORE3_EDMA0_BMON_1_BASE,
757 [GAUDI2_BMON_DCORE3_EDMA1_0] = mmDCORE3_EDMA1_BMON_0_BASE,
758 [GAUDI2_BMON_DCORE3_EDMA1_1] = mmDCORE3_EDMA1_BMON_1_BASE,
759 [GAUDI2_BMON_DCORE3_VDEC0_0] = mmDCORE3_VDEC0_BMON_0_BASE,
760 [GAUDI2_BMON_DCORE3_VDEC0_1] = mmDCORE3_VDEC0_BMON_1_BASE,
761 [GAUDI2_BMON_DCORE3_VDEC0_2] = mmDCORE3_VDEC0_BMON_2_BASE,
762 [GAUDI2_BMON_DCORE3_VDEC1_0] = mmDCORE3_VDEC1_BMON_0_BASE,
763 [GAUDI2_BMON_DCORE3_VDEC1_1] = mmDCORE3_VDEC1_BMON_1_BASE,
764 [GAUDI2_BMON_DCORE3_VDEC1_2] = mmDCORE3_VDEC1_BMON_2_BASE,
765 [GAUDI2_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
766 [GAUDI2_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
767 [GAUDI2_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
768 [GAUDI2_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
769 [GAUDI2_BMON_PSOC_ARC0_0] = 0,
770 [GAUDI2_BMON_PSOC_ARC0_1] = 0,
771 [GAUDI2_BMON_PSOC_ARC1_0] = 0,
772 [GAUDI2_BMON_PSOC_ARC1_1] = 0,
773 [GAUDI2_BMON_PDMA0_0] = mmPDMA0_BMON_0_BASE,
774 [GAUDI2_BMON_PDMA0_1] = mmPDMA0_BMON_1_BASE,
775 [GAUDI2_BMON_PDMA1_0] = mmPDMA1_BMON_0_BASE,
776 [GAUDI2_BMON_PDMA1_1] = mmPDMA1_BMON_1_BASE,
777 [GAUDI2_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
778 [GAUDI2_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
779 [GAUDI2_BMON_PMMU_0] = mmPMMU_BMON_0_BASE,
780 [GAUDI2_BMON_PMMU_1] = mmPMMU_BMON_1_BASE,
781 [GAUDI2_BMON_PMMU_2] = mmPMMU_BMON_2_BASE,
782 [GAUDI2_BMON_PMMU_3] = mmPMMU_BMON_3_BASE,
783 [GAUDI2_BMON_PMMU_4] = mmPMMU_BMON_4_BASE,
784 [GAUDI2_BMON_ROT0_0] = mmROT0_BMON_0_BASE,
785 [GAUDI2_BMON_ROT0_1] = mmROT0_BMON_1_BASE,
786 [GAUDI2_BMON_ROT0_2] = mmROT0_BMON_2_BASE,
787 [GAUDI2_BMON_ROT0_3] = mmROT0_BMON_3_BASE,
788 [GAUDI2_BMON_ROT1_0] = mmROT1_BMON_0_BASE,
789 [GAUDI2_BMON_ROT1_1] = mmROT1_BMON_1_BASE,
790 [GAUDI2_BMON_ROT1_2] = mmROT1_BMON_2_BASE,
791 [GAUDI2_BMON_ROT1_3] = mmROT1_BMON_3_BASE,
792 [GAUDI2_BMON_ARC_FARM_0] = mmARC_FARM_BMON_0_BASE,
793 [GAUDI2_BMON_ARC_FARM_1] = mmARC_FARM_BMON_1_BASE,
794 [GAUDI2_BMON_ARC_FARM_2] = mmARC_FARM_BMON_2_BASE,
795 [GAUDI2_BMON_ARC_FARM_3] = mmARC_FARM_BMON_3_BASE,
796 [GAUDI2_BMON_KDMA_0] = mmKDMA_BMON_0_BASE,
797 [GAUDI2_BMON_KDMA_1] = mmKDMA_BMON_1_BASE,
798 [GAUDI2_BMON_KDMA_2] = mmKDMA_BMON_2_BASE,
799 [GAUDI2_BMON_KDMA_3] = mmKDMA_BMON_3_BASE,
800 [GAUDI2_BMON_PCIE_VDEC0_0] = mmPCIE_VDEC0_BMON_0_BASE,
801 [GAUDI2_BMON_PCIE_VDEC0_1] = mmPCIE_VDEC0_BMON_1_BASE,
802 [GAUDI2_BMON_PCIE_VDEC0_2] = mmPCIE_VDEC0_BMON_2_BASE,
803 [GAUDI2_BMON_PCIE_VDEC1_0] = mmPCIE_VDEC1_BMON_0_BASE,
804 [GAUDI2_BMON_PCIE_VDEC1_1] = mmPCIE_VDEC1_BMON_1_BASE,
805 [GAUDI2_BMON_PCIE_VDEC1_2] = mmPCIE_VDEC1_BMON_2_BASE,
806 [GAUDI2_BMON_NIC0_DBG_0_0] = mmNIC0_DBG_BMON0_0_BASE,
807 [GAUDI2_BMON_NIC0_DBG_1_0] = mmNIC0_DBG_BMON1_0_BASE,
808 [GAUDI2_BMON_NIC0_DBG_2_0] = mmNIC0_DBG_BMON2_0_BASE,
809 [GAUDI2_BMON_NIC0_DBG_0_1] = mmNIC0_DBG_BMON0_1_BASE,
810 [GAUDI2_BMON_NIC0_DBG_1_1] = mmNIC0_DBG_BMON1_1_BASE,
811 [GAUDI2_BMON_NIC0_DBG_2_1] = mmNIC0_DBG_BMON2_1_BASE,
812 [GAUDI2_BMON_NIC1_DBG_0_0] = mmNIC1_DBG_BMON0_0_BASE,
813 [GAUDI2_BMON_NIC1_DBG_1_0] = mmNIC1_DBG_BMON1_0_BASE,
814 [GAUDI2_BMON_NIC1_DBG_2_0] = mmNIC1_DBG_BMON2_0_BASE,
815 [GAUDI2_BMON_NIC1_DBG_0_1] = mmNIC1_DBG_BMON0_1_BASE,
816 [GAUDI2_BMON_NIC1_DBG_1_1] = mmNIC1_DBG_BMON1_1_BASE,
817 [GAUDI2_BMON_NIC1_DBG_2_1] = mmNIC1_DBG_BMON2_1_BASE,
818 [GAUDI2_BMON_NIC2_DBG_0_0] = mmNIC2_DBG_BMON0_0_BASE,
819 [GAUDI2_BMON_NIC2_DBG_1_0] = mmNIC2_DBG_BMON1_0_BASE,
820 [GAUDI2_BMON_NIC2_DBG_2_0] = mmNIC2_DBG_BMON2_0_BASE,
821 [GAUDI2_BMON_NIC2_DBG_0_1] = mmNIC2_DBG_BMON0_1_BASE,
822 [GAUDI2_BMON_NIC2_DBG_1_1] = mmNIC2_DBG_BMON1_1_BASE,
823 [GAUDI2_BMON_NIC2_DBG_2_1] = mmNIC2_DBG_BMON2_1_BASE,
824 [GAUDI2_BMON_NIC3_DBG_0_0] = mmNIC3_DBG_BMON0_0_BASE,
825 [GAUDI2_BMON_NIC3_DBG_1_0] = mmNIC3_DBG_BMON1_0_BASE,
826 [GAUDI2_BMON_NIC3_DBG_2_0] = mmNIC3_DBG_BMON2_0_BASE,
827 [GAUDI2_BMON_NIC3_DBG_0_1] = mmNIC3_DBG_BMON0_1_BASE,
828 [GAUDI2_BMON_NIC3_DBG_1_1] = mmNIC3_DBG_BMON1_1_BASE,
829 [GAUDI2_BMON_NIC3_DBG_2_1] = mmNIC3_DBG_BMON2_1_BASE,
830 [GAUDI2_BMON_NIC4_DBG_0_0] = mmNIC4_DBG_BMON0_0_BASE,
831 [GAUDI2_BMON_NIC4_DBG_1_0] = mmNIC4_DBG_BMON1_0_BASE,
832 [GAUDI2_BMON_NIC4_DBG_2_0] = mmNIC4_DBG_BMON2_0_BASE,
833 [GAUDI2_BMON_NIC4_DBG_0_1] = mmNIC4_DBG_BMON0_1_BASE,
834 [GAUDI2_BMON_NIC4_DBG_1_1] = mmNIC4_DBG_BMON1_1_BASE,
835 [GAUDI2_BMON_NIC4_DBG_2_1] = mmNIC4_DBG_BMON2_1_BASE,
836 [GAUDI2_BMON_NIC5_DBG_0_0] = mmNIC5_DBG_BMON0_0_BASE,
837 [GAUDI2_BMON_NIC5_DBG_1_0] = mmNIC5_DBG_BMON1_0_BASE,
838 [GAUDI2_BMON_NIC5_DBG_2_0] = mmNIC5_DBG_BMON2_0_BASE,
839 [GAUDI2_BMON_NIC5_DBG_0_1] = mmNIC5_DBG_BMON0_1_BASE,
840 [GAUDI2_BMON_NIC5_DBG_1_1] = mmNIC5_DBG_BMON1_1_BASE,
841 [GAUDI2_BMON_NIC5_DBG_2_1] = mmNIC5_DBG_BMON2_1_BASE,
842 [GAUDI2_BMON_NIC6_DBG_0_0] = mmNIC6_DBG_BMON0_0_BASE,
843 [GAUDI2_BMON_NIC6_DBG_1_0] = mmNIC6_DBG_BMON1_0_BASE,
844 [GAUDI2_BMON_NIC6_DBG_2_0] = mmNIC6_DBG_BMON2_0_BASE,
845 [GAUDI2_BMON_NIC6_DBG_0_1] = mmNIC6_DBG_BMON0_1_BASE,
846 [GAUDI2_BMON_NIC6_DBG_1_1] = mmNIC6_DBG_BMON1_1_BASE,
847 [GAUDI2_BMON_NIC6_DBG_2_1] = mmNIC6_DBG_BMON2_1_BASE,
848 [GAUDI2_BMON_NIC7_DBG_0_0] = mmNIC7_DBG_BMON0_0_BASE,
849 [GAUDI2_BMON_NIC7_DBG_1_0] = mmNIC7_DBG_BMON1_0_BASE,
850 [GAUDI2_BMON_NIC7_DBG_2_0] = mmNIC7_DBG_BMON2_0_BASE,
851 [GAUDI2_BMON_NIC7_DBG_0_1] = mmNIC7_DBG_BMON0_1_BASE,
852 [GAUDI2_BMON_NIC7_DBG_1_1] = mmNIC7_DBG_BMON1_1_BASE,
853 [GAUDI2_BMON_NIC7_DBG_2_1] = mmNIC7_DBG_BMON2_1_BASE,
854 [GAUDI2_BMON_NIC8_DBG_0_0] = mmNIC8_DBG_BMON0_0_BASE,
855 [GAUDI2_BMON_NIC8_DBG_1_0] = mmNIC8_DBG_BMON1_0_BASE,
856 [GAUDI2_BMON_NIC8_DBG_2_0] = mmNIC8_DBG_BMON2_0_BASE,
857 [GAUDI2_BMON_NIC8_DBG_0_1] = mmNIC8_DBG_BMON0_1_BASE,
858 [GAUDI2_BMON_NIC8_DBG_1_1] = mmNIC8_DBG_BMON1_1_BASE,
859 [GAUDI2_BMON_NIC8_DBG_2_1] = mmNIC8_DBG_BMON2_1_BASE,
860 [GAUDI2_BMON_NIC9_DBG_0_0] = mmNIC9_DBG_BMON0_0_BASE,
861 [GAUDI2_BMON_NIC9_DBG_1_0] = mmNIC9_DBG_BMON1_0_BASE,
862 [GAUDI2_BMON_NIC9_DBG_2_0] = mmNIC9_DBG_BMON2_0_BASE,
863 [GAUDI2_BMON_NIC9_DBG_0_1] = mmNIC9_DBG_BMON0_1_BASE,
864 [GAUDI2_BMON_NIC9_DBG_1_1] = mmNIC9_DBG_BMON1_1_BASE,
865 [GAUDI2_BMON_NIC9_DBG_2_1] = mmNIC9_DBG_BMON2_1_BASE,
866 [GAUDI2_BMON_NIC10_DBG_0_0] = mmNIC10_DBG_BMON0_0_BASE,
867 [GAUDI2_BMON_NIC10_DBG_1_0] = mmNIC10_DBG_BMON1_0_BASE,
868 [GAUDI2_BMON_NIC10_DBG_2_0] = mmNIC10_DBG_BMON2_0_BASE,
869 [GAUDI2_BMON_NIC10_DBG_0_1] = mmNIC10_DBG_BMON0_1_BASE,
870 [GAUDI2_BMON_NIC10_DBG_1_1] = mmNIC10_DBG_BMON1_1_BASE,
871 [GAUDI2_BMON_NIC10_DBG_2_1] = mmNIC10_DBG_BMON2_1_BASE,
872 [GAUDI2_BMON_NIC11_DBG_0_0] = mmNIC11_DBG_BMON0_0_BASE,
873 [GAUDI2_BMON_NIC11_DBG_1_0] = mmNIC11_DBG_BMON1_0_BASE,
874 [GAUDI2_BMON_NIC11_DBG_2_0] = mmNIC11_DBG_BMON2_0_BASE,
875 [GAUDI2_BMON_NIC11_DBG_0_1] = mmNIC11_DBG_BMON0_1_BASE,
876 [GAUDI2_BMON_NIC11_DBG_1_1] = mmNIC11_DBG_BMON1_1_BASE,
877 [GAUDI2_BMON_NIC11_DBG_2_1] = mmNIC11_DBG_BMON2_1_BASE
878 };
879
880 static u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1] = {
881 [GAUDI2_SPMU_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_SPMU_BASE,
882 [GAUDI2_SPMU_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_SPMU_BASE,
883 [GAUDI2_SPMU_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_SPMU_BASE,
884 [GAUDI2_SPMU_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_SPMU_BASE,
885 [GAUDI2_SPMU_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_SPMU_BASE,
886 [GAUDI2_SPMU_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_SPMU_BASE,
887 [GAUDI2_SPMU_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_SPMU_BASE,
888 [GAUDI2_SPMU_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_SPMU_BASE,
889 [GAUDI2_SPMU_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_SPMU_BASE,
890 [GAUDI2_SPMU_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_SPMU_BASE,
891 [GAUDI2_SPMU_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_SPMU_BASE,
892 [GAUDI2_SPMU_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_SPMU_BASE,
893 [GAUDI2_SPMU_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_SPMU_BASE,
894 [GAUDI2_SPMU_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_SPMU_BASE,
895 [GAUDI2_SPMU_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_SPMU_BASE,
896 [GAUDI2_SPMU_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_SPMU_BASE,
897 [GAUDI2_SPMU_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_SPMU_BASE,
898 [GAUDI2_SPMU_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_SPMU_BASE,
899 [GAUDI2_SPMU_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_SPMU_BASE,
900 [GAUDI2_SPMU_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_SPMU_BASE,
901 [GAUDI2_SPMU_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_SPMU_BASE,
902 [GAUDI2_SPMU_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_SPMU_BASE,
903 [GAUDI2_SPMU_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_SPMU_BASE,
904 [GAUDI2_SPMU_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_SPMU_BASE,
905 [GAUDI2_SPMU_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_SPMU_BASE,
906 [GAUDI2_SPMU_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_SPMU_BASE,
907 [GAUDI2_SPMU_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_SPMU_BASE,
908 [GAUDI2_SPMU_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_SPMU_BASE,
909 [GAUDI2_SPMU_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_SPMU_BASE,
910 [GAUDI2_SPMU_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_SPMU_BASE,
911 [GAUDI2_SPMU_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_SPMU_BASE,
912 [GAUDI2_SPMU_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_SPMU_BASE,
913 [GAUDI2_SPMU_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_SPMU_BASE,
914 [GAUDI2_SPMU_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_SPMU_BASE,
915 [GAUDI2_SPMU_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_SPMU_BASE,
916 [GAUDI2_SPMU_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_SPMU_BASE,
917 [GAUDI2_SPMU_DCORE0_SM] = mmDCORE0_SM_SPMU_BASE,
918 [GAUDI2_SPMU_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_SPMU_BASE,
919 [GAUDI2_SPMU_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_SPMU_BASE,
920 [GAUDI2_SPMU_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_SPMU_BASE,
921 [GAUDI2_SPMU_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_SPMU_BASE,
922 [GAUDI2_SPMU_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_SPMU_BASE,
923 [GAUDI2_SPMU_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_SPMU_BASE,
924 [GAUDI2_SPMU_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_SPMU_BASE,
925 [GAUDI2_SPMU_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_SPMU_BASE,
926 [GAUDI2_SPMU_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_SPMU_BASE,
927 [GAUDI2_SPMU_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_SPMU_BASE,
928 [GAUDI2_SPMU_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_SPMU_BASE,
929 [GAUDI2_SPMU_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_SPMU_BASE,
930 [GAUDI2_SPMU_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_SPMU_BASE,
931 [GAUDI2_SPMU_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_SPMU_BASE,
932 [GAUDI2_SPMU_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_SPMU_BASE,
933 [GAUDI2_SPMU_DCORE1_SM] = mmDCORE1_SM_SPMU_BASE,
934 [GAUDI2_SPMU_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_SPMU_BASE,
935 [GAUDI2_SPMU_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_SPMU_BASE,
936 [GAUDI2_SPMU_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_SPMU_BASE,
937 [GAUDI2_SPMU_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_SPMU_BASE,
938 [GAUDI2_SPMU_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_SPMU_BASE,
939 [GAUDI2_SPMU_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_SPMU_BASE,
940 [GAUDI2_SPMU_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_SPMU_BASE,
941 [GAUDI2_SPMU_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_SPMU_BASE,
942 [GAUDI2_SPMU_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_SPMU_BASE,
943 [GAUDI2_SPMU_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_SPMU_BASE,
944 [GAUDI2_SPMU_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_SPMU_BASE,
945 [GAUDI2_SPMU_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_SPMU_BASE,
946 [GAUDI2_SPMU_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_SPMU_BASE,
947 [GAUDI2_SPMU_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_SPMU_BASE,
948 [GAUDI2_SPMU_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_SPMU_BASE,
949 [GAUDI2_SPMU_DCORE2_SM] = mmDCORE2_SM_SPMU_BASE,
950 [GAUDI2_SPMU_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_SPMU_BASE,
951 [GAUDI2_SPMU_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_SPMU_BASE,
952 [GAUDI2_SPMU_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_SPMU_BASE,
953 [GAUDI2_SPMU_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_SPMU_BASE,
954 [GAUDI2_SPMU_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_SPMU_BASE,
955 [GAUDI2_SPMU_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_SPMU_BASE,
956 [GAUDI2_SPMU_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_SPMU_BASE,
957 [GAUDI2_SPMU_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_SPMU_BASE,
958 [GAUDI2_SPMU_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_SPMU_BASE,
959 [GAUDI2_SPMU_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_SPMU_BASE,
960 [GAUDI2_SPMU_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_SPMU_BASE,
961 [GAUDI2_SPMU_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_SPMU_BASE,
962 [GAUDI2_SPMU_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_SPMU_BASE,
963 [GAUDI2_SPMU_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_SPMU_BASE,
964 [GAUDI2_SPMU_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_SPMU_BASE,
965 [GAUDI2_SPMU_DCORE3_SM] = mmDCORE3_SM_SPMU_BASE,
966 [GAUDI2_SPMU_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_SPMU_BASE,
967 [GAUDI2_SPMU_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_SPMU_BASE,
968 [GAUDI2_SPMU_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_SPMU_BASE,
969 [GAUDI2_SPMU_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_SPMU_BASE,
970 [GAUDI2_SPMU_PCIE] = mmPCIE_SPMU_BASE,
971 [GAUDI2_SPMU_PSOC_ARC0_CS] = 0,
972 [GAUDI2_SPMU_PSOC_ARC1_CS] = 0,
973 [GAUDI2_SPMU_PDMA0_CS] = mmPDMA0_CS_SPMU_BASE,
974 [GAUDI2_SPMU_PDMA1_CS] = mmPDMA1_CS_SPMU_BASE,
975 [GAUDI2_SPMU_PMMU_CS] = mmPMMU_CS_SPMU_BASE,
976 [GAUDI2_SPMU_ROT0_CS] = mmROT0_CS_SPMU_BASE,
977 [GAUDI2_SPMU_ROT1_CS] = mmROT1_CS_SPMU_BASE,
978 [GAUDI2_SPMU_ARC_FARM_CS] = mmARC_FARM_CS_SPMU_BASE,
979 [GAUDI2_SPMU_KDMA_CS] = mmKDMA_CS_SPMU_BASE,
980 [GAUDI2_SPMU_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_SPMU_BASE,
981 [GAUDI2_SPMU_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_SPMU_BASE,
982 [GAUDI2_SPMU_HBM0_MC0_CS] = mmHBM0_MC0_CS_SPMU_BASE,
983 [GAUDI2_SPMU_HBM0_MC1_CS] = mmHBM0_MC1_CS_SPMU_BASE,
984 [GAUDI2_SPMU_HBM1_MC0_CS] = mmHBM1_MC0_CS_SPMU_BASE,
985 [GAUDI2_SPMU_HBM1_MC1_CS] = mmHBM1_MC1_CS_SPMU_BASE,
986 [GAUDI2_SPMU_HBM2_MC0_CS] = mmHBM2_MC0_CS_SPMU_BASE,
987 [GAUDI2_SPMU_HBM2_MC1_CS] = mmHBM2_MC1_CS_SPMU_BASE,
988 [GAUDI2_SPMU_HBM3_MC0_CS] = mmHBM3_MC0_CS_SPMU_BASE,
989 [GAUDI2_SPMU_HBM3_MC1_CS] = mmHBM3_MC1_CS_SPMU_BASE,
990 [GAUDI2_SPMU_HBM4_MC0_CS] = mmHBM4_MC0_CS_SPMU_BASE,
991 [GAUDI2_SPMU_HBM4_MC1_CS] = mmHBM4_MC1_CS_SPMU_BASE,
992 [GAUDI2_SPMU_HBM5_MC0_CS] = mmHBM5_MC0_CS_SPMU_BASE,
993 [GAUDI2_SPMU_HBM5_MC1_CS] = mmHBM5_MC1_CS_SPMU_BASE,
994 [GAUDI2_SPMU_NIC0_DBG_0] = mmNIC0_DBG_SPMU_0_BASE,
995 [GAUDI2_SPMU_NIC0_DBG_1] = mmNIC0_DBG_SPMU_1_BASE,
996 [GAUDI2_SPMU_NIC1_DBG_0] = mmNIC1_DBG_SPMU_0_BASE,
997 [GAUDI2_SPMU_NIC1_DBG_1] = mmNIC1_DBG_SPMU_1_BASE,
998 [GAUDI2_SPMU_NIC2_DBG_0] = mmNIC2_DBG_SPMU_0_BASE,
999 [GAUDI2_SPMU_NIC2_DBG_1] = mmNIC2_DBG_SPMU_1_BASE,
1000 [GAUDI2_SPMU_NIC3_DBG_0] = mmNIC3_DBG_SPMU_0_BASE,
1001 [GAUDI2_SPMU_NIC3_DBG_1] = mmNIC3_DBG_SPMU_1_BASE,
1002 [GAUDI2_SPMU_NIC4_DBG_0] = mmNIC4_DBG_SPMU_0_BASE,
1003 [GAUDI2_SPMU_NIC4_DBG_1] = mmNIC4_DBG_SPMU_1_BASE,
1004 [GAUDI2_SPMU_NIC5_DBG_0] = mmNIC5_DBG_SPMU_0_BASE,
1005 [GAUDI2_SPMU_NIC5_DBG_1] = mmNIC5_DBG_SPMU_1_BASE,
1006 [GAUDI2_SPMU_NIC6_DBG_0] = mmNIC6_DBG_SPMU_0_BASE,
1007 [GAUDI2_SPMU_NIC6_DBG_1] = mmNIC6_DBG_SPMU_1_BASE,
1008 [GAUDI2_SPMU_NIC7_DBG_0] = mmNIC7_DBG_SPMU_0_BASE,
1009 [GAUDI2_SPMU_NIC7_DBG_1] = mmNIC7_DBG_SPMU_1_BASE,
1010 [GAUDI2_SPMU_NIC8_DBG_0] = mmNIC8_DBG_SPMU_0_BASE,
1011 [GAUDI2_SPMU_NIC8_DBG_1] = mmNIC8_DBG_SPMU_1_BASE,
1012 [GAUDI2_SPMU_NIC9_DBG_0] = mmNIC9_DBG_SPMU_0_BASE,
1013 [GAUDI2_SPMU_NIC9_DBG_1] = mmNIC9_DBG_SPMU_1_BASE,
1014 [GAUDI2_SPMU_NIC10_DBG_0] = mmNIC10_DBG_SPMU_0_BASE,
1015 [GAUDI2_SPMU_NIC10_DBG_1] = mmNIC10_DBG_SPMU_1_BASE,
1016 [GAUDI2_SPMU_NIC11_DBG_0] = mmNIC11_DBG_SPMU_0_BASE,
1017 [GAUDI2_SPMU_NIC11_DBG_1] = mmNIC11_DBG_SPMU_1_BASE
1018 };
1019
1020 static struct component_config_offsets xbar_edge_binning_cfg_table[XBAR_EDGE_ID_SIZE] = {
1021 [XBAR_EDGE_ID_DCORE0] = {
1022 .funnel_id = GAUDI2_FUNNEL_DCORE0_XBAR_EDGE,
1023 .etf_id = COMPONENT_ID_INVALID,
1024 .stm_id = COMPONENT_ID_INVALID,
1025 .spmu_id = COMPONENT_ID_INVALID,
1026 .bmon_count = 0,
1027 .bmon_ids = {COMPONENT_ID_INVALID}
1028 },
1029 [XBAR_EDGE_ID_DCORE1] = {
1030 .funnel_id = GAUDI2_FUNNEL_DCORE1_XBAR_EDGE,
1031 .etf_id = COMPONENT_ID_INVALID,
1032 .stm_id = COMPONENT_ID_INVALID,
1033 .spmu_id = COMPONENT_ID_INVALID,
1034 .bmon_count = 0,
1035 .bmon_ids = {COMPONENT_ID_INVALID}
1036 },
1037 [XBAR_EDGE_ID_DCORE2] = {
1038 .funnel_id = GAUDI2_FUNNEL_DCORE2_XBAR_EDGE,
1039 .etf_id = COMPONENT_ID_INVALID,
1040 .stm_id = COMPONENT_ID_INVALID,
1041 .spmu_id = COMPONENT_ID_INVALID,
1042 .bmon_count = 0,
1043 .bmon_ids = {COMPONENT_ID_INVALID}
1044 },
1045 [XBAR_EDGE_ID_DCORE3] = {
1046 .funnel_id = GAUDI2_FUNNEL_DCORE3_XBAR_EDGE,
1047 .etf_id = COMPONENT_ID_INVALID,
1048 .stm_id = COMPONENT_ID_INVALID,
1049 .spmu_id = COMPONENT_ID_INVALID,
1050 .bmon_count = 0,
1051 .bmon_ids = {COMPONENT_ID_INVALID}
1052 },
1053 };
1054
1055
1056 static struct component_config_offsets hmmu_binning_cfg_table[HMMU_ID_SIZE] = {
1057 [HMMU_ID_DCORE0_HMMU0] = {
1058 .funnel_id = COMPONENT_ID_INVALID,
1059 .etf_id = GAUDI2_ETF_DCORE0_HMMU0_CS,
1060 .stm_id = GAUDI2_STM_DCORE0_HMMU0_CS,
1061 .spmu_id = GAUDI2_SPMU_DCORE0_HMMU0_CS,
1062 .bmon_count = 5,
1063 .bmon_ids = {
1064 GAUDI2_BMON_DCORE0_HMMU0_0,
1065 GAUDI2_BMON_DCORE0_HMMU0_1,
1066 GAUDI2_BMON_DCORE0_HMMU0_2,
1067 GAUDI2_BMON_DCORE0_HMMU0_3,
1068 GAUDI2_BMON_DCORE0_HMMU0_4,
1069 }
1070 },
1071 [HMMU_ID_DCORE0_HMMU1] = {
1072 .funnel_id = COMPONENT_ID_INVALID,
1073 .etf_id = GAUDI2_ETF_DCORE0_HMMU1_CS,
1074 .stm_id = GAUDI2_STM_DCORE0_HMMU1_CS,
1075 .spmu_id = GAUDI2_SPMU_DCORE0_HMMU1_CS,
1076 .bmon_count = 5,
1077 .bmon_ids = {
1078 GAUDI2_BMON_DCORE0_HMMU1_0,
1079 GAUDI2_BMON_DCORE0_HMMU1_1,
1080 GAUDI2_BMON_DCORE0_HMMU1_2,
1081 GAUDI2_BMON_DCORE0_HMMU1_3,
1082 GAUDI2_BMON_DCORE0_HMMU1_4,
1083 }
1084 },
1085 [HMMU_ID_DCORE0_HMMU2] = {
1086 .funnel_id = COMPONENT_ID_INVALID,
1087 .etf_id = GAUDI2_ETF_DCORE0_HMMU2_CS,
1088 .stm_id = GAUDI2_STM_DCORE0_HMMU2_CS,
1089 .spmu_id = GAUDI2_SPMU_DCORE0_HMMU2_CS,
1090 .bmon_count = 5,
1091 .bmon_ids = {
1092 GAUDI2_BMON_DCORE0_HMMU2_0,
1093 GAUDI2_BMON_DCORE0_HMMU2_1,
1094 GAUDI2_BMON_DCORE0_HMMU2_2,
1095 GAUDI2_BMON_DCORE0_HMMU2_3,
1096 GAUDI2_BMON_DCORE0_HMMU2_4,
1097 }
1098 },
1099 [HMMU_ID_DCORE0_HMMU3] = {
1100 .funnel_id = COMPONENT_ID_INVALID,
1101 .etf_id = GAUDI2_ETF_DCORE0_HMMU3_CS,
1102 .stm_id = GAUDI2_STM_DCORE0_HMMU3_CS,
1103 .spmu_id = GAUDI2_SPMU_DCORE0_HMMU3_CS,
1104 .bmon_count = 5,
1105 .bmon_ids = {
1106 GAUDI2_BMON_DCORE0_HMMU3_0,
1107 GAUDI2_BMON_DCORE0_HMMU3_1,
1108 GAUDI2_BMON_DCORE0_HMMU3_2,
1109 GAUDI2_BMON_DCORE0_HMMU3_3,
1110 GAUDI2_BMON_DCORE0_HMMU3_4,
1111 }
1112 },
1113 [HMMU_ID_DCORE1_HMMU0] = {
1114 .funnel_id = COMPONENT_ID_INVALID,
1115 .etf_id = GAUDI2_ETF_DCORE1_HMMU0_CS,
1116 .stm_id = GAUDI2_STM_DCORE1_HMMU0_CS,
1117 .spmu_id = GAUDI2_SPMU_DCORE1_HMMU0_CS,
1118 .bmon_count = 5,
1119 .bmon_ids = {
1120 GAUDI2_BMON_DCORE1_HMMU0_0,
1121 GAUDI2_BMON_DCORE1_HMMU0_1,
1122 GAUDI2_BMON_DCORE1_HMMU0_2,
1123 GAUDI2_BMON_DCORE1_HMMU0_3,
1124 GAUDI2_BMON_DCORE1_HMMU0_4,
1125 }
1126 },
1127 [HMMU_ID_DCORE1_HMMU1] = {
1128 .funnel_id = COMPONENT_ID_INVALID,
1129 .etf_id = GAUDI2_ETF_DCORE1_HMMU1_CS,
1130 .stm_id = GAUDI2_STM_DCORE1_HMMU1_CS,
1131 .spmu_id = GAUDI2_SPMU_DCORE1_HMMU1_CS,
1132 .bmon_count = 5,
1133 .bmon_ids = {
1134 GAUDI2_BMON_DCORE1_HMMU1_0,
1135 GAUDI2_BMON_DCORE1_HMMU1_1,
1136 GAUDI2_BMON_DCORE1_HMMU1_2,
1137 GAUDI2_BMON_DCORE1_HMMU1_3,
1138 GAUDI2_BMON_DCORE1_HMMU1_4,
1139 }
1140 },
1141 [HMMU_ID_DCORE1_HMMU2] = {
1142 .funnel_id = COMPONENT_ID_INVALID,
1143 .etf_id = GAUDI2_ETF_DCORE1_HMMU2_CS,
1144 .stm_id = GAUDI2_STM_DCORE1_HMMU2_CS,
1145 .spmu_id = GAUDI2_SPMU_DCORE1_HMMU2_CS,
1146 .bmon_count = 5,
1147 .bmon_ids = {
1148 GAUDI2_BMON_DCORE1_HMMU2_0,
1149 GAUDI2_BMON_DCORE1_HMMU2_1,
1150 GAUDI2_BMON_DCORE1_HMMU2_2,
1151 GAUDI2_BMON_DCORE1_HMMU2_3,
1152 GAUDI2_BMON_DCORE1_HMMU2_4,
1153 }
1154 },
1155 [HMMU_ID_DCORE1_HMMU3] = {
1156 .funnel_id = COMPONENT_ID_INVALID,
1157 .etf_id = GAUDI2_ETF_DCORE1_HMMU3_CS,
1158 .stm_id = GAUDI2_STM_DCORE1_HMMU3_CS,
1159 .spmu_id = GAUDI2_SPMU_DCORE1_HMMU3_CS,
1160 .bmon_count = 5,
1161 .bmon_ids = {
1162 GAUDI2_BMON_DCORE1_HMMU3_0,
1163 GAUDI2_BMON_DCORE1_HMMU3_1,
1164 GAUDI2_BMON_DCORE1_HMMU3_2,
1165 GAUDI2_BMON_DCORE1_HMMU3_3,
1166 GAUDI2_BMON_DCORE1_HMMU3_4,
1167 }
1168 },
1169 [HMMU_ID_DCORE2_HMMU0] = {
1170 .funnel_id = COMPONENT_ID_INVALID,
1171 .etf_id = GAUDI2_ETF_DCORE2_HMMU0_CS,
1172 .stm_id = GAUDI2_STM_DCORE2_HMMU0_CS,
1173 .spmu_id = GAUDI2_SPMU_DCORE2_HMMU0_CS,
1174 .bmon_count = 5,
1175 .bmon_ids = {
1176 GAUDI2_BMON_DCORE2_HMMU0_0,
1177 GAUDI2_BMON_DCORE2_HMMU0_1,
1178 GAUDI2_BMON_DCORE2_HMMU0_2,
1179 GAUDI2_BMON_DCORE2_HMMU0_3,
1180 GAUDI2_BMON_DCORE2_HMMU0_4,
1181 }
1182 },
1183 [HMMU_ID_DCORE2_HMMU1] = {
1184 .funnel_id = COMPONENT_ID_INVALID,
1185 .etf_id = GAUDI2_ETF_DCORE2_HMMU1_CS,
1186 .stm_id = GAUDI2_STM_DCORE2_HMMU1_CS,
1187 .spmu_id = GAUDI2_SPMU_DCORE2_HMMU1_CS,
1188 .bmon_count = 5,
1189 .bmon_ids = {
1190 GAUDI2_BMON_DCORE2_HMMU1_0,
1191 GAUDI2_BMON_DCORE2_HMMU1_1,
1192 GAUDI2_BMON_DCORE2_HMMU1_2,
1193 GAUDI2_BMON_DCORE2_HMMU1_3,
1194 GAUDI2_BMON_DCORE2_HMMU1_4,
1195 }
1196 },
1197 [HMMU_ID_DCORE2_HMMU2] = {
1198 .funnel_id = COMPONENT_ID_INVALID,
1199 .etf_id = GAUDI2_ETF_DCORE2_HMMU2_CS,
1200 .stm_id = GAUDI2_STM_DCORE2_HMMU2_CS,
1201 .spmu_id = GAUDI2_SPMU_DCORE2_HMMU2_CS,
1202 .bmon_count = 5,
1203 .bmon_ids = {
1204 GAUDI2_BMON_DCORE2_HMMU2_0,
1205 GAUDI2_BMON_DCORE2_HMMU2_1,
1206 GAUDI2_BMON_DCORE2_HMMU2_2,
1207 GAUDI2_BMON_DCORE2_HMMU2_3,
1208 GAUDI2_BMON_DCORE2_HMMU2_4,
1209 }
1210 },
1211 [HMMU_ID_DCORE2_HMMU3] = {
1212 .funnel_id = COMPONENT_ID_INVALID,
1213 .etf_id = GAUDI2_ETF_DCORE2_HMMU3_CS,
1214 .stm_id = GAUDI2_STM_DCORE2_HMMU3_CS,
1215 .spmu_id = GAUDI2_SPMU_DCORE2_HMMU3_CS,
1216 .bmon_count = 5,
1217 .bmon_ids = {
1218 GAUDI2_BMON_DCORE2_HMMU3_0,
1219 GAUDI2_BMON_DCORE2_HMMU3_1,
1220 GAUDI2_BMON_DCORE2_HMMU3_2,
1221 GAUDI2_BMON_DCORE2_HMMU3_3,
1222 GAUDI2_BMON_DCORE2_HMMU3_4,
1223 }
1224 },
1225 [HMMU_ID_DCORE3_HMMU0] = {
1226 .funnel_id = COMPONENT_ID_INVALID,
1227 .etf_id = GAUDI2_ETF_DCORE3_HMMU0_CS,
1228 .stm_id = GAUDI2_STM_DCORE3_HMMU0_CS,
1229 .spmu_id = GAUDI2_SPMU_DCORE3_HMMU0_CS,
1230 .bmon_count = 5,
1231 .bmon_ids = {
1232 GAUDI2_BMON_DCORE3_HMMU0_0,
1233 GAUDI2_BMON_DCORE3_HMMU0_1,
1234 GAUDI2_BMON_DCORE3_HMMU0_2,
1235 GAUDI2_BMON_DCORE3_HMMU0_3,
1236 GAUDI2_BMON_DCORE3_HMMU0_4,
1237 }
1238 },
1239 [HMMU_ID_DCORE3_HMMU1] = {
1240 .funnel_id = COMPONENT_ID_INVALID,
1241 .etf_id = GAUDI2_ETF_DCORE3_HMMU1_CS,
1242 .stm_id = GAUDI2_STM_DCORE3_HMMU1_CS,
1243 .spmu_id = GAUDI2_SPMU_DCORE3_HMMU1_CS,
1244 .bmon_count = 5,
1245 .bmon_ids = {
1246 GAUDI2_BMON_DCORE3_HMMU1_0,
1247 GAUDI2_BMON_DCORE3_HMMU1_1,
1248 GAUDI2_BMON_DCORE3_HMMU1_2,
1249 GAUDI2_BMON_DCORE3_HMMU1_3,
1250 GAUDI2_BMON_DCORE3_HMMU1_4,
1251 }
1252 },
1253 [HMMU_ID_DCORE3_HMMU2] = {
1254 .funnel_id = COMPONENT_ID_INVALID,
1255 .etf_id = GAUDI2_ETF_DCORE3_HMMU2_CS,
1256 .stm_id = GAUDI2_STM_DCORE3_HMMU2_CS,
1257 .spmu_id = GAUDI2_SPMU_DCORE3_HMMU2_CS,
1258 .bmon_count = 5,
1259 .bmon_ids = {
1260 GAUDI2_BMON_DCORE3_HMMU2_0,
1261 GAUDI2_BMON_DCORE3_HMMU2_1,
1262 GAUDI2_BMON_DCORE3_HMMU2_2,
1263 GAUDI2_BMON_DCORE3_HMMU2_3,
1264 GAUDI2_BMON_DCORE3_HMMU2_4,
1265 }
1266 },
1267 [HMMU_ID_DCORE3_HMMU3] = {
1268 .funnel_id = COMPONENT_ID_INVALID,
1269 .etf_id = GAUDI2_ETF_DCORE3_HMMU3_CS,
1270 .stm_id = GAUDI2_STM_DCORE3_HMMU3_CS,
1271 .spmu_id = GAUDI2_SPMU_DCORE3_HMMU3_CS,
1272 .bmon_count = 5,
1273 .bmon_ids = {
1274 GAUDI2_BMON_DCORE3_HMMU3_0,
1275 GAUDI2_BMON_DCORE3_HMMU3_1,
1276 GAUDI2_BMON_DCORE3_HMMU3_2,
1277 GAUDI2_BMON_DCORE3_HMMU3_3,
1278 GAUDI2_BMON_DCORE3_HMMU3_4,
1279 }
1280 },
1281 };
1282
1283 static struct component_config_offsets hbm_mc0_binning_cfg_table[HBM_ID_SIZE] = {
1284 [HBM_ID0] = {
1285 .funnel_id = GAUDI2_FUNNEL_HBM0_MC0,
1286 .etf_id = GAUDI2_ETF_HBM0_MC0_CS,
1287 .stm_id = GAUDI2_STM_HBM0_MC0_CS,
1288 .spmu_id = GAUDI2_SPMU_HBM0_MC0_CS,
1289 .bmon_count = 0,
1290 .bmon_ids = {COMPONENT_ID_INVALID}
1291 },
1292 [HBM_ID1] = {
1293 .funnel_id = GAUDI2_FUNNEL_HBM1_MC0,
1294 .etf_id = GAUDI2_ETF_HBM1_MC0_CS,
1295 .stm_id = GAUDI2_STM_HBM1_MC0_CS,
1296 .spmu_id = GAUDI2_SPMU_HBM1_MC0_CS,
1297 .bmon_count = 0,
1298 .bmon_ids = {COMPONENT_ID_INVALID}
1299 },
1300 [HBM_ID2] = {
1301 .funnel_id = GAUDI2_FUNNEL_HBM2_MC0,
1302 .etf_id = GAUDI2_ETF_HBM2_MC0_CS,
1303 .stm_id = GAUDI2_STM_HBM2_MC0_CS,
1304 .spmu_id = GAUDI2_SPMU_HBM2_MC0_CS,
1305 .bmon_count = 0,
1306 .bmon_ids = {COMPONENT_ID_INVALID}
1307 },
1308 [HBM_ID3] = {
1309 .funnel_id = GAUDI2_FUNNEL_HBM3_MC0,
1310 .etf_id = GAUDI2_ETF_HBM3_MC0_CS,
1311 .stm_id = GAUDI2_STM_HBM3_MC0_CS,
1312 .spmu_id = GAUDI2_SPMU_HBM3_MC0_CS,
1313 .bmon_count = 0,
1314 .bmon_ids = {COMPONENT_ID_INVALID}
1315 },
1316 [HBM_ID4] = {
1317 .funnel_id = GAUDI2_FUNNEL_HBM4_MC0,
1318 .etf_id = GAUDI2_ETF_HBM4_MC0_CS,
1319 .stm_id = GAUDI2_STM_HBM4_MC0_CS,
1320 .spmu_id = GAUDI2_SPMU_HBM4_MC0_CS,
1321 .bmon_count = 0,
1322 .bmon_ids = {COMPONENT_ID_INVALID}
1323 },
1324 [HBM_ID5] = {
1325 .funnel_id = GAUDI2_FUNNEL_HBM5_MC0,
1326 .etf_id = GAUDI2_ETF_HBM5_MC0_CS,
1327 .stm_id = GAUDI2_STM_HBM5_MC0_CS,
1328 .spmu_id = GAUDI2_SPMU_HBM5_MC0_CS,
1329 .bmon_count = 0,
1330 .bmon_ids = {COMPONENT_ID_INVALID}
1331 },
1332 };
1333
1334 static struct component_config_offsets hbm_mc1_binning_cfg_table[HBM_ID_SIZE] = {
1335 [HBM_ID0] = {
1336 .funnel_id = GAUDI2_FUNNEL_HBM0_MC1,
1337 .etf_id = GAUDI2_ETF_HBM0_MC1_CS,
1338 .stm_id = GAUDI2_STM_HBM0_MC1_CS,
1339 .spmu_id = GAUDI2_SPMU_HBM0_MC1_CS,
1340 .bmon_count = 0,
1341 .bmon_ids = {COMPONENT_ID_INVALID}
1342 },
1343 [HBM_ID1] = {
1344 .funnel_id = GAUDI2_FUNNEL_HBM1_MC1,
1345 .etf_id = GAUDI2_ETF_HBM1_MC1_CS,
1346 .stm_id = GAUDI2_STM_HBM1_MC1_CS,
1347 .spmu_id = GAUDI2_SPMU_HBM1_MC1_CS,
1348 .bmon_count = 0,
1349 .bmon_ids = {COMPONENT_ID_INVALID}
1350 },
1351 [HBM_ID2] = {
1352 .funnel_id = GAUDI2_FUNNEL_HBM2_MC1,
1353 .etf_id = GAUDI2_ETF_HBM2_MC1_CS,
1354 .stm_id = GAUDI2_STM_HBM2_MC1_CS,
1355 .spmu_id = GAUDI2_SPMU_HBM2_MC1_CS,
1356 .bmon_count = 0,
1357 .bmon_ids = {COMPONENT_ID_INVALID}
1358 },
1359 [HBM_ID3] = {
1360 .funnel_id = GAUDI2_FUNNEL_HBM3_MC1,
1361 .etf_id = GAUDI2_ETF_HBM3_MC1_CS,
1362 .stm_id = GAUDI2_STM_HBM3_MC1_CS,
1363 .spmu_id = GAUDI2_SPMU_HBM3_MC1_CS,
1364 .bmon_count = 0,
1365 .bmon_ids = {COMPONENT_ID_INVALID}
1366 },
1367 [HBM_ID4] = {
1368 .funnel_id = GAUDI2_FUNNEL_HBM4_MC1,
1369 .etf_id = GAUDI2_ETF_HBM4_MC1_CS,
1370 .stm_id = GAUDI2_STM_HBM4_MC1_CS,
1371 .spmu_id = GAUDI2_SPMU_HBM4_MC1_CS,
1372 .bmon_count = 0,
1373 .bmon_ids = {COMPONENT_ID_INVALID}
1374 },
1375 [HBM_ID5] = {
1376 .funnel_id = GAUDI2_FUNNEL_HBM5_MC1,
1377 .etf_id = GAUDI2_ETF_HBM5_MC1_CS,
1378 .stm_id = GAUDI2_STM_HBM5_MC1_CS,
1379 .spmu_id = GAUDI2_SPMU_HBM5_MC1_CS,
1380 .bmon_count = 0,
1381 .bmon_ids = {COMPONENT_ID_INVALID}
1382 },
1383 };
1384
1385 static struct component_config_offsets decoder_binning_cfg_table[DEC_ID_SIZE] = {
1386 [DEC_ID_DCORE0_DEC0] = {
1387 .funnel_id = COMPONENT_ID_INVALID,
1388 .etf_id = GAUDI2_ETF_DCORE0_VDEC0_CS,
1389 .stm_id = GAUDI2_STM_DCORE0_VDEC0_CS,
1390 .spmu_id = GAUDI2_SPMU_DCORE0_VDEC0_CS,
1391 .bmon_count = 3,
1392 .bmon_ids = {
1393 GAUDI2_BMON_DCORE0_VDEC0_0,
1394 GAUDI2_BMON_DCORE0_VDEC0_1,
1395 GAUDI2_BMON_DCORE0_VDEC0_2,
1396 }
1397 },
1398 [DEC_ID_DCORE0_DEC1] = {
1399 .funnel_id = COMPONENT_ID_INVALID,
1400 .etf_id = GAUDI2_ETF_DCORE0_VDEC1_CS,
1401 .stm_id = GAUDI2_STM_DCORE0_VDEC1_CS,
1402 .spmu_id = GAUDI2_SPMU_DCORE0_VDEC1_CS,
1403 .bmon_count = 3,
1404 .bmon_ids = {
1405 GAUDI2_BMON_DCORE0_VDEC1_0,
1406 GAUDI2_BMON_DCORE0_VDEC1_1,
1407 GAUDI2_BMON_DCORE0_VDEC1_2,
1408 }
1409 },
1410 [DEC_ID_DCORE1_DEC0] = {
1411 .funnel_id = COMPONENT_ID_INVALID,
1412 .etf_id = GAUDI2_ETF_DCORE1_VDEC0_CS,
1413 .stm_id = GAUDI2_STM_DCORE1_VDEC0_CS,
1414 .spmu_id = GAUDI2_SPMU_DCORE1_VDEC0_CS,
1415 .bmon_count = 3,
1416 .bmon_ids = {
1417 GAUDI2_BMON_DCORE1_VDEC0_0,
1418 GAUDI2_BMON_DCORE1_VDEC0_1,
1419 GAUDI2_BMON_DCORE1_VDEC0_2,
1420 }
1421 },
1422 [DEC_ID_DCORE1_DEC1] = {
1423 .funnel_id = COMPONENT_ID_INVALID,
1424 .etf_id = GAUDI2_ETF_DCORE1_VDEC1_CS,
1425 .stm_id = GAUDI2_STM_DCORE1_VDEC1_CS,
1426 .spmu_id = GAUDI2_SPMU_DCORE1_VDEC1_CS,
1427 .bmon_count = 3,
1428 .bmon_ids = {
1429 GAUDI2_BMON_DCORE1_VDEC1_0,
1430 GAUDI2_BMON_DCORE1_VDEC1_1,
1431 GAUDI2_BMON_DCORE1_VDEC1_2,
1432 }
1433 },
1434 [DEC_ID_DCORE2_DEC0] = {
1435 .funnel_id = COMPONENT_ID_INVALID,
1436 .etf_id = GAUDI2_ETF_DCORE2_VDEC0_CS,
1437 .stm_id = GAUDI2_STM_DCORE2_VDEC0_CS,
1438 .spmu_id = GAUDI2_SPMU_DCORE2_VDEC0_CS,
1439 .bmon_count = 3,
1440 .bmon_ids = {
1441 GAUDI2_BMON_DCORE2_VDEC0_0,
1442 GAUDI2_BMON_DCORE2_VDEC0_1,
1443 GAUDI2_BMON_DCORE2_VDEC0_2,
1444 }
1445 },
1446 [DEC_ID_DCORE2_DEC1] = {
1447 .funnel_id = COMPONENT_ID_INVALID,
1448 .etf_id = GAUDI2_ETF_DCORE2_VDEC1_CS,
1449 .stm_id = GAUDI2_STM_DCORE2_VDEC1_CS,
1450 .spmu_id = GAUDI2_SPMU_DCORE2_VDEC1_CS,
1451 .bmon_count = 3,
1452 .bmon_ids = {
1453 GAUDI2_BMON_DCORE2_VDEC1_0,
1454 GAUDI2_BMON_DCORE2_VDEC1_1,
1455 GAUDI2_BMON_DCORE2_VDEC1_2,
1456 }
1457 },
1458 [DEC_ID_DCORE3_DEC0] = {
1459 .funnel_id = COMPONENT_ID_INVALID,
1460 .etf_id = GAUDI2_ETF_DCORE3_VDEC0_CS,
1461 .stm_id = GAUDI2_STM_DCORE3_VDEC0_CS,
1462 .spmu_id = GAUDI2_SPMU_DCORE3_VDEC0_CS,
1463 .bmon_count = 3,
1464 .bmon_ids = {
1465 GAUDI2_BMON_DCORE3_VDEC0_0,
1466 GAUDI2_BMON_DCORE3_VDEC0_1,
1467 GAUDI2_BMON_DCORE3_VDEC0_2,
1468 }
1469 },
1470 [DEC_ID_DCORE3_DEC1] = {
1471 .funnel_id = COMPONENT_ID_INVALID,
1472 .etf_id = GAUDI2_ETF_DCORE3_VDEC1_CS,
1473 .stm_id = GAUDI2_STM_DCORE3_VDEC1_CS,
1474 .spmu_id = GAUDI2_SPMU_DCORE3_VDEC1_CS,
1475 .bmon_count = 3,
1476 .bmon_ids = {
1477 GAUDI2_BMON_DCORE3_VDEC1_0,
1478 GAUDI2_BMON_DCORE3_VDEC1_1,
1479 GAUDI2_BMON_DCORE3_VDEC1_2,
1480 }
1481 },
1482 [DEC_ID_PCIE_VDEC0] = {
1483 .funnel_id = COMPONENT_ID_INVALID,
1484 .etf_id = GAUDI2_ETF_PCIE_VDEC0_CS,
1485 .stm_id = GAUDI2_STM_PCIE_VDEC0_CS,
1486 .spmu_id = GAUDI2_SPMU_PCIE_VDEC0_CS,
1487 .bmon_count = 3,
1488 .bmon_ids = {
1489 GAUDI2_BMON_PCIE_VDEC0_0,
1490 GAUDI2_BMON_PCIE_VDEC0_1,
1491 GAUDI2_BMON_PCIE_VDEC0_2,
1492 }
1493 },
1494 [DEC_ID_PCIE_VDEC1] = {
1495 .funnel_id = COMPONENT_ID_INVALID,
1496 .etf_id = GAUDI2_ETF_PCIE_VDEC1_CS,
1497 .stm_id = GAUDI2_STM_PCIE_VDEC1_CS,
1498 .spmu_id = GAUDI2_SPMU_PCIE_VDEC1_CS,
1499 .bmon_count = 3,
1500 .bmon_ids = {
1501 GAUDI2_BMON_PCIE_VDEC1_0,
1502 GAUDI2_BMON_PCIE_VDEC1_1,
1503 GAUDI2_BMON_PCIE_VDEC1_2,
1504 }
1505 },
1506 };
1507
1508 static struct component_config_offsets edma_binning_cfg_table[EDMA_ID_SIZE] = {
1509 [EDMA_ID_DCORE0_INSTANCE0] = {
1510 .funnel_id = COMPONENT_ID_INVALID,
1511 .etf_id = GAUDI2_ETF_DCORE0_EDMA0_CS,
1512 .stm_id = GAUDI2_STM_DCORE0_EDMA0_CS,
1513 .spmu_id = GAUDI2_SPMU_DCORE0_EDMA0_CS,
1514 .bmon_count = 2,
1515 .bmon_ids = {
1516 GAUDI2_BMON_DCORE0_EDMA0_0,
1517 GAUDI2_BMON_DCORE0_EDMA0_1,
1518 }
1519 },
1520 [EDMA_ID_DCORE0_INSTANCE1] = {
1521 .funnel_id = COMPONENT_ID_INVALID,
1522 .etf_id = GAUDI2_ETF_DCORE0_EDMA1_CS,
1523 .stm_id = GAUDI2_STM_DCORE0_EDMA1_CS,
1524 .spmu_id = GAUDI2_SPMU_DCORE0_EDMA1_CS,
1525 .bmon_count = 2,
1526 .bmon_ids = {
1527 GAUDI2_BMON_DCORE0_EDMA1_0,
1528 GAUDI2_BMON_DCORE0_EDMA1_1,
1529 }
1530 },
1531 [EDMA_ID_DCORE1_INSTANCE0] = {
1532 .funnel_id = COMPONENT_ID_INVALID,
1533 .etf_id = GAUDI2_ETF_DCORE1_EDMA0_CS,
1534 .stm_id = GAUDI2_STM_DCORE1_EDMA0_CS,
1535 .spmu_id = GAUDI2_SPMU_DCORE1_EDMA0_CS,
1536 .bmon_count = 2,
1537 .bmon_ids = {
1538 GAUDI2_BMON_DCORE1_EDMA0_0,
1539 GAUDI2_BMON_DCORE1_EDMA0_1,
1540 }
1541 },
1542 [EDMA_ID_DCORE1_INSTANCE1] = {
1543 .funnel_id = COMPONENT_ID_INVALID,
1544 .etf_id = GAUDI2_ETF_DCORE1_EDMA1_CS,
1545 .stm_id = GAUDI2_STM_DCORE1_EDMA1_CS,
1546 .spmu_id = GAUDI2_SPMU_DCORE1_EDMA1_CS,
1547 .bmon_count = 2,
1548 .bmon_ids = {
1549 GAUDI2_BMON_DCORE1_EDMA1_0,
1550 GAUDI2_BMON_DCORE1_EDMA1_1,
1551 }
1552 },
1553 [EDMA_ID_DCORE2_INSTANCE0] = {
1554 .funnel_id = COMPONENT_ID_INVALID,
1555 .etf_id = GAUDI2_ETF_DCORE2_EDMA0_CS,
1556 .stm_id = GAUDI2_STM_DCORE2_EDMA0_CS,
1557 .spmu_id = GAUDI2_SPMU_DCORE2_EDMA0_CS,
1558 .bmon_count = 2,
1559 .bmon_ids = {
1560 GAUDI2_BMON_DCORE2_EDMA0_0,
1561 GAUDI2_BMON_DCORE2_EDMA0_1,
1562 }
1563 },
1564 [EDMA_ID_DCORE2_INSTANCE1] = {
1565 .funnel_id = COMPONENT_ID_INVALID,
1566 .etf_id = GAUDI2_ETF_DCORE2_EDMA1_CS,
1567 .stm_id = GAUDI2_STM_DCORE2_EDMA1_CS,
1568 .spmu_id = GAUDI2_SPMU_DCORE2_EDMA1_CS,
1569 .bmon_count = 2,
1570 .bmon_ids = {
1571 GAUDI2_BMON_DCORE2_EDMA1_0,
1572 GAUDI2_BMON_DCORE2_EDMA1_1,
1573 }
1574 },
1575 [EDMA_ID_DCORE3_INSTANCE0] = {
1576 .funnel_id = COMPONENT_ID_INVALID,
1577 .etf_id = GAUDI2_ETF_DCORE3_EDMA0_CS,
1578 .stm_id = GAUDI2_STM_DCORE3_EDMA0_CS,
1579 .spmu_id = GAUDI2_SPMU_DCORE3_EDMA0_CS,
1580 .bmon_count = 2,
1581 .bmon_ids = {
1582 GAUDI2_BMON_DCORE3_EDMA0_0,
1583 GAUDI2_BMON_DCORE3_EDMA0_1,
1584 }
1585 },
1586 [EDMA_ID_DCORE3_INSTANCE1] = {
1587 .funnel_id = COMPONENT_ID_INVALID,
1588 .etf_id = GAUDI2_ETF_DCORE3_EDMA1_CS,
1589 .stm_id = GAUDI2_STM_DCORE3_EDMA1_CS,
1590 .spmu_id = GAUDI2_SPMU_DCORE3_EDMA1_CS,
1591 .bmon_count = 2,
1592 .bmon_ids = {
1593 GAUDI2_BMON_DCORE3_EDMA1_0,
1594 GAUDI2_BMON_DCORE3_EDMA1_1,
1595 }
1596 },
1597 };
1598
1599 static struct component_config_offsets tpc_binning_cfg_table[TPC_ID_SIZE] = {
1600 [TPC_ID_DCORE0_TPC0] = {
1601 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC0_EML,
1602 .etf_id = GAUDI2_ETF_DCORE0_TPC0_EML,
1603 .stm_id = GAUDI2_STM_DCORE0_TPC0_EML,
1604 .spmu_id = GAUDI2_SPMU_DCORE0_TPC0_EML,
1605 .bmon_count = 4,
1606 .bmon_ids = {
1607 GAUDI2_BMON_DCORE0_TPC0_EML_0,
1608 GAUDI2_BMON_DCORE0_TPC0_EML_1,
1609 GAUDI2_BMON_DCORE0_TPC0_EML_2,
1610 GAUDI2_BMON_DCORE0_TPC0_EML_3,
1611 }
1612 },
1613 [TPC_ID_DCORE0_TPC1] = {
1614 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC1_EML,
1615 .etf_id = GAUDI2_ETF_DCORE0_TPC1_EML,
1616 .stm_id = GAUDI2_STM_DCORE0_TPC1_EML,
1617 .spmu_id = GAUDI2_SPMU_DCORE0_TPC1_EML,
1618 .bmon_count = 4,
1619 .bmon_ids = {
1620 GAUDI2_BMON_DCORE0_TPC1_EML_0,
1621 GAUDI2_BMON_DCORE0_TPC1_EML_1,
1622 GAUDI2_BMON_DCORE0_TPC1_EML_2,
1623 GAUDI2_BMON_DCORE0_TPC1_EML_3,
1624 }
1625 },
1626 [TPC_ID_DCORE0_TPC2] = {
1627 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC2_EML,
1628 .etf_id = GAUDI2_ETF_DCORE0_TPC2_EML,
1629 .stm_id = GAUDI2_STM_DCORE0_TPC2_EML,
1630 .spmu_id = GAUDI2_SPMU_DCORE0_TPC2_EML,
1631 .bmon_count = 4,
1632 .bmon_ids = {
1633 GAUDI2_BMON_DCORE0_TPC2_EML_0,
1634 GAUDI2_BMON_DCORE0_TPC2_EML_1,
1635 GAUDI2_BMON_DCORE0_TPC2_EML_2,
1636 GAUDI2_BMON_DCORE0_TPC2_EML_3,
1637 }
1638 },
1639 [TPC_ID_DCORE0_TPC3] = {
1640 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC3_EML,
1641 .etf_id = GAUDI2_ETF_DCORE0_TPC3_EML,
1642 .stm_id = GAUDI2_STM_DCORE0_TPC3_EML,
1643 .spmu_id = GAUDI2_SPMU_DCORE0_TPC3_EML,
1644 .bmon_count = 4,
1645 .bmon_ids = {
1646 GAUDI2_BMON_DCORE0_TPC3_EML_0,
1647 GAUDI2_BMON_DCORE0_TPC3_EML_1,
1648 GAUDI2_BMON_DCORE0_TPC3_EML_2,
1649 GAUDI2_BMON_DCORE0_TPC3_EML_3,
1650 }
1651 },
1652 [TPC_ID_DCORE0_TPC4] = {
1653 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC4_EML,
1654 .etf_id = GAUDI2_ETF_DCORE0_TPC4_EML,
1655 .stm_id = GAUDI2_STM_DCORE0_TPC4_EML,
1656 .spmu_id = GAUDI2_SPMU_DCORE0_TPC4_EML,
1657 .bmon_count = 4,
1658 .bmon_ids = {
1659 GAUDI2_BMON_DCORE0_TPC4_EML_0,
1660 GAUDI2_BMON_DCORE0_TPC4_EML_1,
1661 GAUDI2_BMON_DCORE0_TPC4_EML_2,
1662 GAUDI2_BMON_DCORE0_TPC4_EML_3,
1663 }
1664 },
1665 [TPC_ID_DCORE0_TPC5] = {
1666 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC5_EML,
1667 .etf_id = GAUDI2_ETF_DCORE0_TPC5_EML,
1668 .stm_id = GAUDI2_STM_DCORE0_TPC5_EML,
1669 .spmu_id = GAUDI2_SPMU_DCORE0_TPC5_EML,
1670 .bmon_count = 4,
1671 .bmon_ids = {
1672 GAUDI2_BMON_DCORE0_TPC5_EML_0,
1673 GAUDI2_BMON_DCORE0_TPC5_EML_1,
1674 GAUDI2_BMON_DCORE0_TPC5_EML_2,
1675 GAUDI2_BMON_DCORE0_TPC5_EML_3,
1676 }
1677 },
1678 [TPC_ID_DCORE1_TPC0] = {
1679 .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC0_EML,
1680 .etf_id = GAUDI2_ETF_DCORE1_TPC0_EML,
1681 .stm_id = GAUDI2_STM_DCORE1_TPC0_EML,
1682 .spmu_id = GAUDI2_SPMU_DCORE1_TPC0_EML,
1683 .bmon_count = 4,
1684 .bmon_ids = {
1685 GAUDI2_BMON_DCORE1_TPC0_EML_0,
1686 GAUDI2_BMON_DCORE1_TPC0_EML_1,
1687 GAUDI2_BMON_DCORE1_TPC0_EML_2,
1688 GAUDI2_BMON_DCORE1_TPC0_EML_3,
1689 }
1690 },
1691 [TPC_ID_DCORE1_TPC1] = {
1692 .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC1_EML,
1693 .etf_id = GAUDI2_ETF_DCORE1_TPC1_EML,
1694 .stm_id = GAUDI2_STM_DCORE1_TPC1_EML,
1695 .spmu_id = GAUDI2_SPMU_DCORE1_TPC1_EML,
1696 .bmon_count = 4,
1697 .bmon_ids = {
1698 GAUDI2_BMON_DCORE1_TPC1_EML_0,
1699 GAUDI2_BMON_DCORE1_TPC1_EML_1,
1700 GAUDI2_BMON_DCORE1_TPC1_EML_2,
1701 GAUDI2_BMON_DCORE1_TPC1_EML_3,
1702 }
1703 },
1704 [TPC_ID_DCORE1_TPC2] = {
1705 .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC2_EML,
1706 .etf_id = GAUDI2_ETF_DCORE1_TPC2_EML,
1707 .stm_id = GAUDI2_STM_DCORE1_TPC2_EML,
1708 .spmu_id = GAUDI2_SPMU_DCORE1_TPC2_EML,
1709 .bmon_count = 4,
1710 .bmon_ids = {
1711 GAUDI2_BMON_DCORE1_TPC2_EML_0,
1712 GAUDI2_BMON_DCORE1_TPC2_EML_1,
1713 GAUDI2_BMON_DCORE1_TPC2_EML_2,
1714 GAUDI2_BMON_DCORE1_TPC2_EML_3,
1715 }
1716 },
1717 [TPC_ID_DCORE1_TPC3] = {
1718 .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC3_EML,
1719 .etf_id = GAUDI2_ETF_DCORE1_TPC3_EML,
1720 .stm_id = GAUDI2_STM_DCORE1_TPC3_EML,
1721 .spmu_id = GAUDI2_SPMU_DCORE1_TPC3_EML,
1722 .bmon_count = 4,
1723 .bmon_ids = {
1724 GAUDI2_BMON_DCORE1_TPC3_EML_0,
1725 GAUDI2_BMON_DCORE1_TPC3_EML_1,
1726 GAUDI2_BMON_DCORE1_TPC3_EML_2,
1727 GAUDI2_BMON_DCORE1_TPC3_EML_3,
1728 }
1729 },
1730 [TPC_ID_DCORE1_TPC4] = {
1731 .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC4_EML,
1732 .etf_id = GAUDI2_ETF_DCORE1_TPC4_EML,
1733 .stm_id = GAUDI2_STM_DCORE1_TPC4_EML,
1734 .spmu_id = GAUDI2_SPMU_DCORE1_TPC4_EML,
1735 .bmon_count = 4,
1736 .bmon_ids = {
1737 GAUDI2_BMON_DCORE1_TPC4_EML_0,
1738 GAUDI2_BMON_DCORE1_TPC4_EML_1,
1739 GAUDI2_BMON_DCORE1_TPC4_EML_2,
1740 GAUDI2_BMON_DCORE1_TPC4_EML_3,
1741 }
1742 },
1743 [TPC_ID_DCORE1_TPC5] = {
1744 .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC5_EML,
1745 .etf_id = GAUDI2_ETF_DCORE1_TPC5_EML,
1746 .stm_id = GAUDI2_STM_DCORE1_TPC5_EML,
1747 .spmu_id = GAUDI2_SPMU_DCORE1_TPC5_EML,
1748 .bmon_count = 4,
1749 .bmon_ids = {
1750 GAUDI2_BMON_DCORE1_TPC5_EML_0,
1751 GAUDI2_BMON_DCORE1_TPC5_EML_1,
1752 GAUDI2_BMON_DCORE1_TPC5_EML_2,
1753 GAUDI2_BMON_DCORE1_TPC5_EML_3,
1754 }
1755 },
1756 [TPC_ID_DCORE2_TPC0] = {
1757 .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC0_EML,
1758 .etf_id = GAUDI2_ETF_DCORE2_TPC0_EML,
1759 .stm_id = GAUDI2_STM_DCORE2_TPC0_EML,
1760 .spmu_id = GAUDI2_SPMU_DCORE2_TPC0_EML,
1761 .bmon_count = 4,
1762 .bmon_ids = {
1763 GAUDI2_BMON_DCORE2_TPC0_EML_0,
1764 GAUDI2_BMON_DCORE2_TPC0_EML_1,
1765 GAUDI2_BMON_DCORE2_TPC0_EML_2,
1766 GAUDI2_BMON_DCORE2_TPC0_EML_3,
1767 }
1768 },
1769 [TPC_ID_DCORE2_TPC1] = {
1770 .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC1_EML,
1771 .etf_id = GAUDI2_ETF_DCORE2_TPC1_EML,
1772 .stm_id = GAUDI2_STM_DCORE2_TPC1_EML,
1773 .spmu_id = GAUDI2_SPMU_DCORE2_TPC1_EML,
1774 .bmon_count = 4,
1775 .bmon_ids = {
1776 GAUDI2_BMON_DCORE2_TPC1_EML_0,
1777 GAUDI2_BMON_DCORE2_TPC1_EML_1,
1778 GAUDI2_BMON_DCORE2_TPC1_EML_2,
1779 GAUDI2_BMON_DCORE2_TPC1_EML_3,
1780 }
1781 },
1782 [TPC_ID_DCORE2_TPC2] = {
1783 .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC2_EML,
1784 .etf_id = GAUDI2_ETF_DCORE2_TPC2_EML,
1785 .stm_id = GAUDI2_STM_DCORE2_TPC2_EML,
1786 .spmu_id = GAUDI2_SPMU_DCORE2_TPC2_EML,
1787 .bmon_count = 4,
1788 .bmon_ids = {
1789 GAUDI2_BMON_DCORE2_TPC2_EML_0,
1790 GAUDI2_BMON_DCORE2_TPC2_EML_1,
1791 GAUDI2_BMON_DCORE2_TPC2_EML_2,
1792 GAUDI2_BMON_DCORE2_TPC2_EML_3,
1793 }
1794 },
1795 [TPC_ID_DCORE2_TPC3] = {
1796 .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC3_EML,
1797 .etf_id = GAUDI2_ETF_DCORE2_TPC3_EML,
1798 .stm_id = GAUDI2_STM_DCORE2_TPC3_EML,
1799 .spmu_id = GAUDI2_SPMU_DCORE2_TPC3_EML,
1800 .bmon_count = 4,
1801 .bmon_ids = {
1802 GAUDI2_BMON_DCORE2_TPC3_EML_0,
1803 GAUDI2_BMON_DCORE2_TPC3_EML_1,
1804 GAUDI2_BMON_DCORE2_TPC3_EML_2,
1805 GAUDI2_BMON_DCORE2_TPC3_EML_3,
1806 }
1807 },
1808 [TPC_ID_DCORE2_TPC4] = {
1809 .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC4_EML,
1810 .etf_id = GAUDI2_ETF_DCORE2_TPC4_EML,
1811 .stm_id = GAUDI2_STM_DCORE2_TPC4_EML,
1812 .spmu_id = GAUDI2_SPMU_DCORE2_TPC4_EML,
1813 .bmon_count = 4,
1814 .bmon_ids = {
1815 GAUDI2_BMON_DCORE2_TPC4_EML_0,
1816 GAUDI2_BMON_DCORE2_TPC4_EML_1,
1817 GAUDI2_BMON_DCORE2_TPC4_EML_2,
1818 GAUDI2_BMON_DCORE2_TPC4_EML_3,
1819 }
1820 },
1821 [TPC_ID_DCORE2_TPC5] = {
1822 .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC5_EML,
1823 .etf_id = GAUDI2_ETF_DCORE2_TPC5_EML,
1824 .stm_id = GAUDI2_STM_DCORE2_TPC5_EML,
1825 .spmu_id = GAUDI2_SPMU_DCORE2_TPC5_EML,
1826 .bmon_count = 4,
1827 .bmon_ids = {
1828 GAUDI2_BMON_DCORE2_TPC5_EML_0,
1829 GAUDI2_BMON_DCORE2_TPC5_EML_1,
1830 GAUDI2_BMON_DCORE2_TPC5_EML_2,
1831 GAUDI2_BMON_DCORE2_TPC5_EML_3,
1832 }
1833 },
1834 [TPC_ID_DCORE3_TPC0] = {
1835 .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC0_EML,
1836 .etf_id = GAUDI2_ETF_DCORE3_TPC0_EML,
1837 .stm_id = GAUDI2_STM_DCORE3_TPC0_EML,
1838 .spmu_id = GAUDI2_SPMU_DCORE3_TPC0_EML,
1839 .bmon_count = 4,
1840 .bmon_ids = {
1841 GAUDI2_BMON_DCORE3_TPC0_EML_0,
1842 GAUDI2_BMON_DCORE3_TPC0_EML_1,
1843 GAUDI2_BMON_DCORE3_TPC0_EML_2,
1844 GAUDI2_BMON_DCORE3_TPC0_EML_3,
1845 }
1846 },
1847 [TPC_ID_DCORE3_TPC1] = {
1848 .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC1_EML,
1849 .etf_id = GAUDI2_ETF_DCORE3_TPC1_EML,
1850 .stm_id = GAUDI2_STM_DCORE3_TPC1_EML,
1851 .spmu_id = GAUDI2_SPMU_DCORE3_TPC1_EML,
1852 .bmon_count = 4,
1853 .bmon_ids = {
1854 GAUDI2_BMON_DCORE3_TPC1_EML_0,
1855 GAUDI2_BMON_DCORE3_TPC1_EML_1,
1856 GAUDI2_BMON_DCORE3_TPC1_EML_2,
1857 GAUDI2_BMON_DCORE3_TPC1_EML_3,
1858 }
1859 },
1860 [TPC_ID_DCORE3_TPC2] = {
1861 .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC2_EML,
1862 .etf_id = GAUDI2_ETF_DCORE3_TPC2_EML,
1863 .stm_id = GAUDI2_STM_DCORE3_TPC2_EML,
1864 .spmu_id = GAUDI2_SPMU_DCORE3_TPC2_EML,
1865 .bmon_count = 4,
1866 .bmon_ids = {
1867 GAUDI2_BMON_DCORE3_TPC2_EML_0,
1868 GAUDI2_BMON_DCORE3_TPC2_EML_1,
1869 GAUDI2_BMON_DCORE3_TPC2_EML_2,
1870 GAUDI2_BMON_DCORE3_TPC2_EML_3,
1871 }
1872 },
1873 [TPC_ID_DCORE3_TPC3] = {
1874 .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC3_EML,
1875 .etf_id = GAUDI2_ETF_DCORE3_TPC3_EML,
1876 .stm_id = GAUDI2_STM_DCORE3_TPC3_EML,
1877 .spmu_id = GAUDI2_SPMU_DCORE3_TPC3_EML,
1878 .bmon_count = 4,
1879 .bmon_ids = {
1880 GAUDI2_BMON_DCORE3_TPC3_EML_0,
1881 GAUDI2_BMON_DCORE3_TPC3_EML_1,
1882 GAUDI2_BMON_DCORE3_TPC3_EML_2,
1883 GAUDI2_BMON_DCORE3_TPC3_EML_3,
1884 }
1885 },
1886 [TPC_ID_DCORE3_TPC4] = {
1887 .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC4_EML,
1888 .etf_id = GAUDI2_ETF_DCORE3_TPC4_EML,
1889 .stm_id = GAUDI2_STM_DCORE3_TPC4_EML,
1890 .spmu_id = GAUDI2_SPMU_DCORE3_TPC4_EML,
1891 .bmon_count = 4,
1892 .bmon_ids = {
1893 GAUDI2_BMON_DCORE3_TPC4_EML_0,
1894 GAUDI2_BMON_DCORE3_TPC4_EML_1,
1895 GAUDI2_BMON_DCORE3_TPC4_EML_2,
1896 GAUDI2_BMON_DCORE3_TPC4_EML_3,
1897 }
1898 },
1899 [TPC_ID_DCORE3_TPC5] = {
1900 .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC5_EML,
1901 .etf_id = GAUDI2_ETF_DCORE3_TPC5_EML,
1902 .stm_id = GAUDI2_STM_DCORE3_TPC5_EML,
1903 .spmu_id = GAUDI2_SPMU_DCORE3_TPC5_EML,
1904 .bmon_count = 4,
1905 .bmon_ids = {
1906 GAUDI2_BMON_DCORE3_TPC5_EML_0,
1907 GAUDI2_BMON_DCORE3_TPC5_EML_1,
1908 GAUDI2_BMON_DCORE3_TPC5_EML_2,
1909 GAUDI2_BMON_DCORE3_TPC5_EML_3,
1910 }
1911 },
1912 [TPC_ID_DCORE0_TPC6] = {
1913 .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC6_EML,
1914 .etf_id = GAUDI2_ETF_DCORE0_TPC6_EML,
1915 .stm_id = GAUDI2_STM_DCORE0_TPC6_EML,
1916 .spmu_id = GAUDI2_SPMU_DCORE0_TPC6_EML,
1917 .bmon_count = 4,
1918 .bmon_ids = {
1919 GAUDI2_BMON_DCORE0_TPC6_EML_0,
1920 GAUDI2_BMON_DCORE0_TPC6_EML_1,
1921 GAUDI2_BMON_DCORE0_TPC6_EML_2,
1922 GAUDI2_BMON_DCORE0_TPC6_EML_3,
1923 }
1924 }
1925 };
1926
1927 static int gaudi2_coresight_timeout(struct hl_device *hdev, u64 addr,
1928 int position, bool up)
1929 {
1930 int rc;
1931 u32 val, timeout_usec;
1932
1933 if (hdev->pldm)
1934 timeout_usec = GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC;
1935 else
1936 timeout_usec = CORESIGHT_TIMEOUT_USEC;
1937
1938 rc = hl_poll_timeout(
1939 hdev,
1940 addr,
1941 val,
1942 up ? val & BIT(position) : !(val & BIT(position)),
1943 1000,
1944 timeout_usec);
1945
1946 if (rc)
1947 dev_err(hdev->dev,
1948 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
1949 addr, position, up);
1950
1951 return rc;
1952 }
1953
1954 static int gaudi2_unlock_coresight_unit(struct hl_device *hdev,
1955 const u64 base_reg)
1956 {
1957 int rc = 0;
1958
1959 WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK);
1960
1961 rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET,
1962 1, 0);
1963
1964 if (rc)
1965 dev_err(hdev->dev,
1966 "Failed to unlock register base addr: 0x%llx , position: 1, up: 0\n",
1967 base_reg);
1968
1969 return rc;
1970 }
1971
1972 static int gaudi2_config_stm(struct hl_device *hdev, struct hl_debug_params *params)
1973 {
1974 struct hl_debug_params_stm *input;
1975 u64 base_reg;
1976 u32 frequency;
1977 u32 read_reg;
1978 int rc;
1979
1980 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
1981 dev_err(hdev->dev, "Invalid register index in STM\n");
1982 return -EINVAL;
1983 }
1984
1985 base_reg = debug_stm_regs[params->reg_idx];
1986
1987 /*
1988 * in case base reg is 0x0 we ignore this configuration
1989 */
1990 if (!base_reg)
1991 return 0;
1992
1993 /* check if stub component on pldm
1994 * we check offset 0xCFC STMDMAIDR in case
1995 * return value is 0x0 - hence stub component
1996 */
1997 read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET);
1998 if (hdev->pldm && read_reg == 0x0)
1999 return 0;
2000
2001 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2002 if (rc)
2003 return -EIO;
2004
2005 if (params->enable) {
2006 input = params->input;
2007
2008 if (!input)
2009 return -EINVAL;
2010
2011 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x80004);
2012 /* dummy read for pldm to flush outstanding writes */
2013 if (hdev->pldm)
2014 RREG32(base_reg + mmSTM_STMTCSR_OFFSET);
2015
2016 WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 7);
2017 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0);
2018 WREG32(base_reg + mmSTM_STMHEER_OFFSET, lower_32_bits(input->he_mask));
2019 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1);
2020 WREG32(base_reg + mmSTM_STMHEER_OFFSET, upper_32_bits(input->he_mask));
2021 WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0x10);
2022 WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0);
2023 WREG32(base_reg + mmSTM_STMSPER_OFFSET, lower_32_bits(input->sp_mask));
2024 WREG32(base_reg + mmSTM_STMITATBID_OFFSET, input->id);
2025 WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80);
2026 frequency = hdev->asic_prop.psoc_timestamp_frequency;
2027 if (frequency == 0)
2028 frequency = input->frequency;
2029 WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, frequency);
2030 WREG32(base_reg + mmSTM_STMSYNCR_OFFSET, 0x7FF);
2031 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x27 | (input->id << 16));
2032 } else {
2033 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4);
2034 WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 0);
2035 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1);
2036 WREG32(base_reg + mmSTM_STMHEER_OFFSET, 0);
2037 WREG32(base_reg + mmSTM_STMHETER_OFFSET, 0);
2038 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0);
2039 WREG32(base_reg + mmSTM_STMSPTER_OFFSET, 0);
2040 WREG32(base_reg + mmSTM_STMSPER_OFFSET, 0);
2041 WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80);
2042 WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0);
2043 WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0);
2044 WREG32(base_reg + mmSTM_STMSPMSCR_OFFSET, 0);
2045 WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, 0);
2046
2047 rc = gaudi2_coresight_timeout(hdev, base_reg + mmSTM_STMTCSR_OFFSET, 23, false);
2048 if (rc) {
2049 dev_err(hdev->dev, "Failed to disable STM on timeout, error %d\n", rc);
2050 return rc;
2051 }
2052
2053 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4);
2054 }
2055
2056 return 0;
2057 }
2058
2059 static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *params)
2060 {
2061 struct hl_debug_params_etf *input;
2062 u64 base_reg;
2063 u32 read_reg;
2064 u32 val;
2065 int rc;
2066
2067 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
2068 dev_err(hdev->dev, "Invalid register index in ETF\n");
2069 return -EINVAL;
2070 }
2071
2072 base_reg = debug_etf_regs[params->reg_idx];
2073
2074 /*
2075 * in case base reg is 0x0 we ignore this configuration
2076 */
2077 if (!base_reg)
2078 return 0;
2079
2080
2081 /* in pldm we need to check if unit is not stub
2082 * for doing do need to read ETF STS register and check
2083 * it is not return 0x0 - in case it does
2084 * it means that this is stub, we ignore this and return 0
2085 * means success
2086 */
2087 read_reg = RREG32(base_reg + mmETF_STS_OFFSET);
2088 if (hdev->pldm && read_reg == 0x0)
2089 return 0;
2090
2091 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2092 if (rc)
2093 return -EIO;
2094
2095 val = RREG32(base_reg + mmETF_CTL_OFFSET);
2096
2097 if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
2098 return 0;
2099
2100 val = RREG32(base_reg + mmETF_FFCR_OFFSET);
2101 val |= 0x1000;
2102 WREG32(base_reg + mmETF_FFCR_OFFSET, val);
2103 val |= 0x40;
2104 WREG32(base_reg + mmETF_FFCR_OFFSET, val);
2105
2106 rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_FFCR_OFFSET, 6, false);
2107 if (rc) {
2108 dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n",
2109 params->enable ? "enable" : "disable", rc);
2110 return rc;
2111 }
2112
2113 rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_STS_OFFSET, 2, true);
2114 if (rc) {
2115 dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n",
2116 params->enable ? "enable" : "disable", rc);
2117 return rc;
2118 }
2119
2120 WREG32(base_reg + mmETF_CTL_OFFSET, 0);
2121
2122 if (params->enable) {
2123 input = params->input;
2124
2125 if (!input)
2126 return -EINVAL;
2127
2128 val = RREG32(base_reg + mmETF_RSZ_OFFSET) << 2;
2129 if (val) {
2130 val = ffs(val);
2131 WREG32(base_reg + mmETF_PSCR_OFFSET, val);
2132 } else {
2133 WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
2134 }
2135
2136 WREG32(base_reg + mmETF_BUFWM_OFFSET, 0x3FFC);
2137 WREG32(base_reg + mmETF_MODE_OFFSET, input->sink_mode);
2138 WREG32(base_reg + mmETF_FFCR_OFFSET, 0x4001);
2139 WREG32(base_reg + mmETF_CTL_OFFSET, 1);
2140 } else {
2141 WREG32(base_reg + mmETF_BUFWM_OFFSET, 0);
2142 WREG32(base_reg + mmETF_MODE_OFFSET, 0);
2143 WREG32(base_reg + mmETF_FFCR_OFFSET, 0);
2144 }
2145
2146 return 0;
2147 }
2148
2149 static int gaudi2_etr_validate_address(struct hl_device *hdev, u64 addr, u64 size)
2150 {
2151 struct asic_fixed_properties *prop = &hdev->asic_prop;
2152 struct gaudi2_device *gaudi2 = hdev->asic_specific;
2153
2154 if (addr > (addr + size)) {
2155 dev_err(hdev->dev, "ETR buffer size %llu overflow\n", size);
2156 return false;
2157 }
2158
2159 if (gaudi2->hw_cap_initialized & HW_CAP_PMMU) {
2160 if (hl_mem_area_inside_range(addr, size,
2161 prop->pmmu.start_addr,
2162 prop->pmmu.end_addr))
2163 return true;
2164
2165 if (hl_mem_area_inside_range(addr, size,
2166 prop->pmmu_huge.start_addr,
2167 prop->pmmu_huge.end_addr))
2168 return true;
2169
2170 if (hl_mem_area_inside_range(addr, size,
2171 prop->dmmu.start_addr,
2172 prop->dmmu.end_addr))
2173 return true;
2174 } else {
2175 if (hl_mem_area_inside_range(addr, size,
2176 prop->dram_user_base_address,
2177 prop->dram_end_address))
2178 return true;
2179 }
2180
2181 if (hl_mem_area_inside_range(addr, size,
2182 prop->sram_user_base_address,
2183 prop->sram_end_address))
2184 return true;
2185
2186 if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU))
2187 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");
2188
2189 return false;
2190 }
2191
2192 static int gaudi2_config_etr(struct hl_device *hdev, struct hl_ctx *ctx,
2193 struct hl_debug_params *params)
2194 {
2195 struct hl_debug_params_etr *input;
2196 u64 msb;
2197 u32 val;
2198 int rc;
2199
2200 rc = gaudi2_unlock_coresight_unit(hdev, mmPSOC_ETR_BASE);
2201 if (rc)
2202 return -EIO;
2203
2204 val = RREG32(mmPSOC_ETR_CTL);
2205
2206 if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
2207 return 0;
2208
2209 val = RREG32(mmPSOC_ETR_FFCR);
2210 val |= 0x1000;
2211 WREG32(mmPSOC_ETR_FFCR, val);
2212 val |= 0x40;
2213 WREG32(mmPSOC_ETR_FFCR, val);
2214
2215 rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
2216 if (rc) {
2217 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
2218 params->enable ? "enable" : "disable", rc);
2219 return rc;
2220 }
2221
2222 rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
2223 if (rc) {
2224 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
2225 params->enable ? "enable" : "disable", rc);
2226 return rc;
2227 }
2228
2229 WREG32(mmPSOC_ETR_CTL, 0);
2230
2231 if (params->enable) {
2232 input = params->input;
2233
2234 if (!input)
2235 return -EINVAL;
2236
2237 if (input->buffer_size == 0) {
2238 dev_err(hdev->dev, "ETR buffer size should be bigger than 0\n");
2239 return -EINVAL;
2240 }
2241
2242 if (!gaudi2_etr_validate_address(hdev, input->buffer_address, input->buffer_size)) {
2243 dev_err(hdev->dev, "ETR buffer address is invalid\n");
2244 return -EINVAL;
2245 }
2246
2247 RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_AWUSER, ctx->asid, MMUBP_ASID_MASK);
2248 RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_ARUSER, ctx->asid, MMUBP_ASID_MASK);
2249
2250 msb = upper_32_bits(input->buffer_address) >> 8;
2251 WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);
2252
2253 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
2254 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
2255 WREG32(mmPSOC_ETR_MODE, input->sink_mode);
2256 /* write the protection bits only if security is disable */
2257 if (!(hdev->fw_components & FW_TYPE_BOOT_CPU)) {
2258 /* make ETR not privileged */
2259 val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
2260 /* make ETR non-secured (inverted logic) */
2261 val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
2262 /* burst size 16 */
2263 val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 0xF);
2264 WREG32(mmPSOC_ETR_AXICTL, val);
2265 }
2266 WREG32(mmPSOC_ETR_DBALO, lower_32_bits(input->buffer_address));
2267 WREG32(mmPSOC_ETR_DBAHI, upper_32_bits(input->buffer_address));
2268 WREG32(mmPSOC_ETR_FFCR, 3);
2269 WREG32(mmPSOC_ETR_PSCR, 0x10);
2270 WREG32(mmPSOC_ETR_CTL, 1);
2271 } else {
2272 WREG32(mmPSOC_ETR_BUFWM, 0);
2273 WREG32(mmPSOC_ETR_RSZ, 0x400);
2274 WREG32(mmPSOC_ETR_DBALO, 0);
2275 WREG32(mmPSOC_ETR_DBAHI, 0);
2276 WREG32(mmPSOC_ETR_PSCR, 0);
2277 WREG32(mmPSOC_ETR_MODE, 0);
2278 WREG32(mmPSOC_ETR_FFCR, 0);
2279
2280 if (params->output_size >= sizeof(u64)) {
2281 u32 rwp, rwphi;
2282
2283 /*
2284 * The trace buffer address is 64 bits wide. The end of
2285 * the buffer is set in the RWP register (lower 32
2286 * bits), and in the RWPHI register (upper 8 bits).
2287 * The 24 msb of the 64-bit address are stored in a
2288 * global configuration register.
2289 */
2290 rwp = RREG32(mmPSOC_ETR_RWP);
2291 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
2292 msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR);
2293 *(u64 *) params->output = ((u64) msb << 40) | ((u64) rwphi << 32) | rwp;
2294 }
2295 }
2296
2297 return 0;
2298 }
2299
2300 static int gaudi2_config_funnel(struct hl_device *hdev, struct hl_debug_params *params)
2301 {
2302 u64 base_reg;
2303 u32 val = params->enable ? 0xFFF : 0;
2304 u32 read_reg;
2305 int rc = 0;
2306
2307 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
2308 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
2309 return -EINVAL;
2310 }
2311
2312 base_reg = debug_funnel_regs[params->reg_idx];
2313
2314 /*
2315 * in case base reg is 0x0 we ignore this configuration
2316 */
2317 if (!base_reg)
2318 return 0;
2319
2320
2321 /* in pldm we need to check if unit is not stub
2322 * for doing so, need to read DEVID value.
2323 * in case return 0x0 - it means that this is stub,
2324 * we ignore this and return 0 - means success
2325 */
2326 read_reg = RREG32(base_reg + mmFUNNEL_DEVID_OFFSET);
2327 if (hdev->pldm && read_reg == 0x0)
2328 return 0;
2329
2330 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2331 if (rc)
2332 return -EIO;
2333
2334 WREG32(base_reg, val);
2335
2336 return 0;
2337 }
2338
2339 static int gaudi2_config_bmon(struct hl_device *hdev, struct hl_debug_params *params)
2340 {
2341 struct hl_debug_params_bmon *input;
2342 u64 base_reg;
2343 u32 read_reg;
2344
2345 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
2346 dev_err(hdev->dev, "Invalid register index in BMON\n");
2347 return -EINVAL;
2348 }
2349
2350 base_reg = debug_bmon_regs[params->reg_idx];
2351
2352 /*
2353 * in case base reg is 0x0 we ignore this configuration
2354 */
2355 if (!base_reg)
2356 return 0;
2357
2358
2359 /* in pldm we need to check if unit is not stub
2360 * for doing do need to read Control Register (offset 0x0) and check
2361 * it is not return 0x0 - in case it does
2362 * it means that this is stub, we ignore this and return 0
2363 * means success
2364 */
2365 read_reg = RREG32(base_reg + mmBMON_CR_OFFSET);
2366 if (hdev->pldm && read_reg == 0x0)
2367 return 0;
2368
2369 WREG32(base_reg + mmBMON_ATTREN_OFFSET, 1);
2370 /* dummy read for pldm to flush outstanding writes */
2371 if (hdev->pldm)
2372 RREG32(base_reg + mmBMON_ATTREN_OFFSET);
2373
2374 /* Write Only Reset AXIMON */
2375
2376 WREG32(base_reg + mmBMON_RESET_OFFSET, 0x1);
2377
2378 if (params->enable) {
2379 input = params->input;
2380
2381 if (!input)
2382 return -EINVAL;
2383
2384 WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, lower_32_bits(input->start_addr0));
2385 WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, upper_32_bits(input->start_addr0));
2386 WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, lower_32_bits(input->addr_mask0));
2387 WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, upper_32_bits(input->addr_mask0));
2388 WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, lower_32_bits(input->start_addr1));
2389 WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, upper_32_bits(input->start_addr1));
2390 WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, lower_32_bits(input->addr_mask1));
2391 WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, upper_32_bits(input->addr_mask1));
2392 WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, lower_32_bits(input->start_addr2));
2393 WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, upper_32_bits(input->start_addr2));
2394 WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, lower_32_bits(input->end_addr2));
2395 WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, upper_32_bits(input->end_addr2));
2396 WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, lower_32_bits(input->start_addr3));
2397 WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, upper_32_bits(input->start_addr3));
2398 WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, lower_32_bits(input->end_addr3));
2399 WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, upper_32_bits(input->end_addr3));
2400
2401 WREG32(base_reg + mmBMON_IDL_OFFSET, 0x0);
2402 WREG32(base_reg + mmBMON_IDH_OFFSET, 0x0);
2403
2404 WREG32(base_reg + mmBMON_ATTREN_OFFSET, 0);
2405 WREG32(base_reg + mmBMON_BW_WIN_OFFSET, input->bw_win);
2406 WREG32(base_reg + mmBMON_WIN_CAPTURE_OFFSET, input->win_capture);
2407 WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0x1 | (13 << 8));
2408 WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (input->id << 8));
2409 WREG32(base_reg + mmBMON_CR_OFFSET, input->control);
2410 } else {
2411 WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, 0);
2412 WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, 0);
2413 WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, 0);
2414 WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, 0);
2415 WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, 0);
2416 WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, 0);
2417 WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, 0);
2418 WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, 0);
2419 WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, 0);
2420 WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, 0);
2421 WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, 0);
2422 WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, 0);
2423 WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, 0);
2424 WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, 0);
2425 WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, 0);
2426 WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, 0);
2427 WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0);
2428 WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (0xA << 8));
2429 WREG32(base_reg + mmBMON_CR_OFFSET, 0x77 | 0xf << 24);
2430 }
2431
2432 return 0;
2433 }
2434
2435 static int gaudi2_config_spmu(struct hl_device *hdev, struct hl_debug_params *params)
2436 {
2437 struct hl_debug_params_spmu *input = params->input;
2438 u32 output_arr_len;
2439 u32 cycle_cnt_idx;
2440 u32 overflow_idx;
2441 u32 events_num;
2442 u32 event_mask;
2443 u64 base_reg;
2444 u32 read_reg;
2445 u64 *output;
2446 int i;
2447
2448 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
2449 dev_err(hdev->dev, "Invalid register index in SPMU\n");
2450 return -EINVAL;
2451 }
2452
2453 base_reg = debug_spmu_regs[params->reg_idx];
2454
2455 /*
2456 * in case base reg is 0x0 we ignore this configuration
2457 */
2458 if (!base_reg)
2459 return 0;
2460
2461 /* in pldm we need to check if unit is not stub
2462 * for doing do need to read PMTRC (at offset 0x200)
2463 * address and check if return value is 0x0 - in case it does
2464 * it means that this is stub, we ignore this and return 0
2465 * means success
2466 */
2467 read_reg = RREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET);
2468 if (hdev->pldm && read_reg == 0x0)
2469 return 0;
2470
2471 if (params->enable) {
2472 input = params->input;
2473
2474 if (!input)
2475 return -EINVAL;
2476
2477 if (input->event_types_num > SPMU_MAX_COUNTERS) {
2478 dev_err(hdev->dev, "too many event types values for SPMU enable\n");
2479 return -EINVAL;
2480 }
2481
2482 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013046);
2483 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040);
2484
2485 /* dummy read for pldm to flush outstanding writes */
2486 if (hdev->pldm)
2487 RREG32(base_reg);
2488
2489 for (i = 0 ; i < input->event_types_num ; i++)
2490 WREG32(base_reg + mmSPMU_PMEVTYPER0_EL0_OFFSET + i * 4,
2491 input->event_types[i]);
2492
2493 WREG32(base_reg + mmSPMU_PMTRC_OFFSET, input->pmtrc_val);
2494 WREG32(base_reg + mmSPMU_TRC_CTRL_HOST_OFFSET, input->trc_ctrl_host_val);
2495 WREG32(base_reg + mmSPMU_TRC_EN_HOST_OFFSET, input->trc_en_host_val);
2496
2497 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013041);
2498
2499 /*
2500 * set enabled events mask based on input->event_types_num
2501 */
2502 event_mask = 0x80000000;
2503 if (input->event_types_num)
2504 event_mask |= GENMASK(input->event_types_num - 1, 0);
2505
2506 WREG32(base_reg + mmSPMU_PMCNTENSET_EL0_OFFSET, event_mask);
2507 } else {
2508 output = params->output;
2509 output_arr_len = params->output_size / 8;
2510 events_num = output_arr_len - 2;
2511 overflow_idx = output_arr_len - 2;
2512 cycle_cnt_idx = output_arr_len - 1;
2513
2514 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040);
2515
2516 if (output && output_arr_len > 2) {
2517
2518 if (events_num > SPMU_MAX_COUNTERS) {
2519 dev_err(hdev->dev, "too many events values for SPMU disable\n");
2520 return -EINVAL;
2521 }
2522
2523 for (i = 0 ; i < events_num ; i++) {
2524 const u64 performance_counter_offset =
2525 base_reg + mmSPMU_PMEVCNTR0_EL0_OFFSET + (i * 8);
2526
2527 output[i] = RREG32(performance_counter_offset);
2528 }
2529
2530 output[overflow_idx] = RREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET);
2531 output[cycle_cnt_idx] = RREG32(base_reg + mmSPMU_PMCCNTR_H_EL0_OFFSET);
2532 output[cycle_cnt_idx] <<= 32;
2533 output[cycle_cnt_idx] |= RREG32(base_reg + mmSPMU_PMCCNTR_L_EL0_OFFSET);
2534 }
2535
2536 WREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET, 0);
2537
2538 /* clean pmtrc to reset value */
2539 WREG32(base_reg + mmSPMU_PMTRC_OFFSET, 0x100400);
2540 }
2541
2542 return 0;
2543 }
2544
2545 int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
2546 {
2547 struct hl_debug_params *params = data;
2548 int rc = 0;
2549
2550 switch (params->op) {
2551 case HL_DEBUG_OP_STM:
2552 rc = gaudi2_config_stm(hdev, params);
2553 break;
2554 case HL_DEBUG_OP_ETF:
2555 rc = gaudi2_config_etf(hdev, params);
2556 break;
2557 case HL_DEBUG_OP_ETR:
2558 rc = gaudi2_config_etr(hdev, ctx, params);
2559 break;
2560 case HL_DEBUG_OP_FUNNEL:
2561 rc = gaudi2_config_funnel(hdev, params);
2562 break;
2563 case HL_DEBUG_OP_BMON:
2564 rc = gaudi2_config_bmon(hdev, params);
2565 break;
2566 case HL_DEBUG_OP_SPMU:
2567 rc = gaudi2_config_spmu(hdev, params);
2568 break;
2569 case HL_DEBUG_OP_TIMESTAMP:
2570 /* Do nothing as this opcode is deprecated */
2571 break;
2572 default:
2573 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
2574 return -EINVAL;
2575 }
2576
2577 return rc;
2578 }
2579
2580 void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
2581 {
2582 struct hl_debug_params params = {};
2583 int i, rc;
2584
2585 /* in pldm attempting to access stubbed etfs can cause problems */
2586 if (!hdev->pldm)
2587 for (i = GAUDI2_ETF_FIRST ; i <= GAUDI2_ETF_LAST ; i++) {
2588 params.reg_idx = i;
2589 rc = gaudi2_config_etf(hdev, &params);
2590 if (rc)
2591 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
2592 }
2593
2594 rc = gaudi2_config_etr(hdev, ctx, &params);
2595 if (rc)
2596 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
2597 }
2598
2599
2600 static int gaudi2_coresight_set_disabled_components(struct hl_device *hdev, u32 unit_count,
2601 u32 enabled_mask,
2602 const struct component_config_offsets *binning_table)
2603 {
2604 u32 component_idx = 0;
2605 u32 disabled_mask;
2606 u32 full_mask;
2607
2608 /* in case no unit - no need to do work */
2609 if (!unit_count)
2610 return 0;
2611
2612 full_mask = GENMASK(unit_count - 1, 0);
2613
2614 /* set the disable bits on disabled mask */
2615 disabled_mask = (~enabled_mask) & full_mask;
2616
2617 while (disabled_mask) {
2618 u32 component_mask = 1 << component_idx;
2619
2620 if (component_idx >= unit_count) {
2621 dev_err(hdev->dev, "index is out of range index(%u) >= units_count(%u)\n",
2622 component_idx, unit_count);
2623 return -EINVAL;
2624 }
2625
2626 /*
2627 * in case mask is set, driver need to set to 0x0
2628 * all offsets for the following structures in the appropriate indices:
2629 * debug_funnel_regs - offsets for all cs_dbg FUNNELs
2630 * debug_etf_regs - offsets for all cs_dbg ETFs
2631 * debug_stm_regs - offsets for all cs_dbg STMs
2632 * debug_spmu_regs - offsets for all cs_dbg SPMUs
2633 * debug_bmon_regs - offsets for all cs_dbg BMONs
2634 * when value is set to COMPONENT_ID_INVALID -
2635 * it means there is no such register for current component.
2636 */
2637
2638 if (disabled_mask & component_mask) {
2639 u32 bmon_idx;
2640 const struct component_config_offsets *binned_component =
2641 &(binning_table[component_idx]);
2642
2643 if (binned_component->funnel_id != COMPONENT_ID_INVALID)
2644 debug_funnel_regs[binned_component->funnel_id] = 0x0;
2645
2646 if (binned_component->etf_id != COMPONENT_ID_INVALID)
2647 debug_etf_regs[binned_component->etf_id] = 0x0;
2648
2649 if (binned_component->stm_id != COMPONENT_ID_INVALID)
2650 debug_stm_regs[binned_component->stm_id] = 0x0;
2651
2652 if (binned_component->spmu_id != COMPONENT_ID_INVALID)
2653 debug_spmu_regs[binned_component->spmu_id] = 0x0;
2654
2655 for (bmon_idx = 0; bmon_idx < binned_component->bmon_count; bmon_idx++)
2656 debug_bmon_regs[binned_component->bmon_ids[bmon_idx]] = 0x0;
2657
2658 /*
2659 * reset enabled bit
2660 */
2661 disabled_mask &= ~component_mask;
2662 }
2663
2664 component_idx++;
2665 }
2666
2667 return 0;
2668 }
2669
2670 int gaudi2_coresight_init(struct hl_device *hdev)
2671 {
2672 struct asic_fixed_properties *prop = &hdev->asic_prop;
2673 int ret;
2674
2675 /*
2676 * Mask out all the disabled binned offsets.
2677 * so when user request to configure a binned or masked out component,
2678 * driver will ignore programming it ( happens when offset value is set to 0x0 )
2679 * this is being set in gaudi2_coresight_set_disabled_components
2680 */
2681
2682 /* Set TPC disable components */
2683 ret = gaudi2_coresight_set_disabled_components(hdev, TPC_ID_SIZE, prop->tpc_enabled_mask,
2684 tpc_binning_cfg_table);
2685 if (ret) {
2686 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for tpc coresight\n");
2687 return ret;
2688 }
2689
2690 /* Set decoder disable components */
2691 ret = gaudi2_coresight_set_disabled_components(hdev, DEC_ID_SIZE,
2692 prop->decoder_enabled_mask, decoder_binning_cfg_table);
2693 if (ret) {
2694 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for decoder coresight\n");
2695 return ret;
2696 }
2697
2698 /* Set HBM (MC0 and MC1) disable components */
2699 ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask,
2700 hbm_mc0_binning_cfg_table);
2701 if (ret) {
2702 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc0 coresight\n");
2703 return ret;
2704 }
2705
2706 ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask,
2707 hbm_mc1_binning_cfg_table);
2708 if (ret) {
2709 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc1 coresight\n");
2710 return ret;
2711 }
2712
2713 /* Set HIF_HMMU disable components */
2714 ret = gaudi2_coresight_set_disabled_components(hdev, HMMU_ID_SIZE,
2715 prop->hmmu_hif_enabled_mask, hmmu_binning_cfg_table);
2716 if (ret) {
2717 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hmmu coresight\n");
2718 return ret;
2719 }
2720
2721 /* Set XBAR_EDGE disable components */
2722 ret = gaudi2_coresight_set_disabled_components(hdev, XBAR_EDGE_ID_SIZE,
2723 prop->xbar_edge_enabled_mask, xbar_edge_binning_cfg_table);
2724 if (ret) {
2725 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for xbar_edge coresight\n");
2726 return ret;
2727 }
2728
2729 /* Set EDMA disable components */
2730 ret = gaudi2_coresight_set_disabled_components(hdev, EDMA_ID_SIZE, prop->edma_enabled_mask,
2731 edma_binning_cfg_table);
2732 if (ret) {
2733 dev_err(hdev->dev, "Failed to set disabled cs_dbg units for edma coresight\n");
2734 return ret;
2735 }
2736
2737 return 0;
2738 }
Kernel DRM miscellaneous fixes and cross-tree changes