drm: bridge: adv7511: remove s32 format from i2s capabilities

[drm/drm-misc.git] / drivers / accel / habanalabs / include / gaudi / asic_reg / tpc2_qm_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_TPC2_QM_REGS_H_
#define ASIC_REG_TPC2_QM_REGS_H_

/*
 *****************************************
 *   TPC2_QM (Prototype: QMAN)
 *****************************************
 */

#define mmTPC2_QM_GLBL_CFG0                                          0xE88000

#define mmTPC2_QM_GLBL_CFG1                                          0xE88004

#define mmTPC2_QM_GLBL_PROT                                          0xE88008

#define mmTPC2_QM_GLBL_ERR_CFG                                       0xE8800C

#define mmTPC2_QM_GLBL_SECURE_PROPS_0                                0xE88010

#define mmTPC2_QM_GLBL_SECURE_PROPS_1                                0xE88014

#define mmTPC2_QM_GLBL_SECURE_PROPS_2                                0xE88018

#define mmTPC2_QM_GLBL_SECURE_PROPS_3                                0xE8801C

#define mmTPC2_QM_GLBL_SECURE_PROPS_4                                0xE88020

#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0                            0xE88024

#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1                            0xE88028

#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2                            0xE8802C

#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3                            0xE88030

#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4                            0xE88034

#define mmTPC2_QM_GLBL_STS0                                          0xE88038

#define mmTPC2_QM_GLBL_STS1_0                                        0xE88040

#define mmTPC2_QM_GLBL_STS1_1                                        0xE88044

#define mmTPC2_QM_GLBL_STS1_2                                        0xE88048

#define mmTPC2_QM_GLBL_STS1_3                                        0xE8804C

#define mmTPC2_QM_GLBL_STS1_4                                        0xE88050

#define mmTPC2_QM_GLBL_MSG_EN_0                                      0xE88054

#define mmTPC2_QM_GLBL_MSG_EN_1                                      0xE88058

#define mmTPC2_QM_GLBL_MSG_EN_2                                      0xE8805C

#define mmTPC2_QM_GLBL_MSG_EN_3                                      0xE88060

#define mmTPC2_QM_GLBL_MSG_EN_4                                      0xE88068

#define mmTPC2_QM_PQ_BASE_LO_0                                       0xE88070

#define mmTPC2_QM_PQ_BASE_LO_1                                       0xE88074

#define mmTPC2_QM_PQ_BASE_LO_2                                       0xE88078

#define mmTPC2_QM_PQ_BASE_LO_3                                       0xE8807C

#define mmTPC2_QM_PQ_BASE_HI_0                                       0xE88080

#define mmTPC2_QM_PQ_BASE_HI_1                                       0xE88084

#define mmTPC2_QM_PQ_BASE_HI_2                                       0xE88088

#define mmTPC2_QM_PQ_BASE_HI_3                                       0xE8808C

#define mmTPC2_QM_PQ_SIZE_0                                          0xE88090

#define mmTPC2_QM_PQ_SIZE_1                                          0xE88094

#define mmTPC2_QM_PQ_SIZE_2                                          0xE88098

#define mmTPC2_QM_PQ_SIZE_3                                          0xE8809C

#define mmTPC2_QM_PQ_PI_0                                            0xE880A0

#define mmTPC2_QM_PQ_PI_1                                            0xE880A4

#define mmTPC2_QM_PQ_PI_2                                            0xE880A8

#define mmTPC2_QM_PQ_PI_3                                            0xE880AC

#define mmTPC2_QM_PQ_CI_0                                            0xE880B0

#define mmTPC2_QM_PQ_CI_1                                            0xE880B4

#define mmTPC2_QM_PQ_CI_2                                            0xE880B8

#define mmTPC2_QM_PQ_CI_3                                            0xE880BC

#define mmTPC2_QM_PQ_CFG0_0                                          0xE880C0

#define mmTPC2_QM_PQ_CFG0_1                                          0xE880C4

#define mmTPC2_QM_PQ_CFG0_2                                          0xE880C8

#define mmTPC2_QM_PQ_CFG0_3                                          0xE880CC

#define mmTPC2_QM_PQ_CFG1_0                                          0xE880D0

#define mmTPC2_QM_PQ_CFG1_1                                          0xE880D4

#define mmTPC2_QM_PQ_CFG1_2                                          0xE880D8

#define mmTPC2_QM_PQ_CFG1_3                                          0xE880DC

#define mmTPC2_QM_PQ_ARUSER_31_11_0                                  0xE880E0

#define mmTPC2_QM_PQ_ARUSER_31_11_1                                  0xE880E4

#define mmTPC2_QM_PQ_ARUSER_31_11_2                                  0xE880E8

#define mmTPC2_QM_PQ_ARUSER_31_11_3                                  0xE880EC

#define mmTPC2_QM_PQ_STS0_0                                          0xE880F0

#define mmTPC2_QM_PQ_STS0_1                                          0xE880F4

#define mmTPC2_QM_PQ_STS0_2                                          0xE880F8

#define mmTPC2_QM_PQ_STS0_3                                          0xE880FC

#define mmTPC2_QM_PQ_STS1_0                                          0xE88100

#define mmTPC2_QM_PQ_STS1_1                                          0xE88104

#define mmTPC2_QM_PQ_STS1_2                                          0xE88108

#define mmTPC2_QM_PQ_STS1_3                                          0xE8810C

#define mmTPC2_QM_CQ_CFG0_0                                          0xE88110

#define mmTPC2_QM_CQ_CFG0_1                                          0xE88114

#define mmTPC2_QM_CQ_CFG0_2                                          0xE88118

#define mmTPC2_QM_CQ_CFG0_3                                          0xE8811C

#define mmTPC2_QM_CQ_CFG0_4                                          0xE88120

#define mmTPC2_QM_CQ_CFG1_0                                          0xE88124

#define mmTPC2_QM_CQ_CFG1_1                                          0xE88128

#define mmTPC2_QM_CQ_CFG1_2                                          0xE8812C

#define mmTPC2_QM_CQ_CFG1_3                                          0xE88130

#define mmTPC2_QM_CQ_CFG1_4                                          0xE88134

#define mmTPC2_QM_CQ_ARUSER_31_11_0                                  0xE88138

#define mmTPC2_QM_CQ_ARUSER_31_11_1                                  0xE8813C

#define mmTPC2_QM_CQ_ARUSER_31_11_2                                  0xE88140

#define mmTPC2_QM_CQ_ARUSER_31_11_3                                  0xE88144

#define mmTPC2_QM_CQ_ARUSER_31_11_4                                  0xE88148

#define mmTPC2_QM_CQ_STS0_0                                          0xE8814C

#define mmTPC2_QM_CQ_STS0_1                                          0xE88150

#define mmTPC2_QM_CQ_STS0_2                                          0xE88154

#define mmTPC2_QM_CQ_STS0_3                                          0xE88158

#define mmTPC2_QM_CQ_STS0_4                                          0xE8815C

#define mmTPC2_QM_CQ_STS1_0                                          0xE88160

#define mmTPC2_QM_CQ_STS1_1                                          0xE88164

#define mmTPC2_QM_CQ_STS1_2                                          0xE88168

#define mmTPC2_QM_CQ_STS1_3                                          0xE8816C

#define mmTPC2_QM_CQ_STS1_4                                          0xE88170

#define mmTPC2_QM_CQ_PTR_LO_0                                        0xE88174

#define mmTPC2_QM_CQ_PTR_HI_0                                        0xE88178

#define mmTPC2_QM_CQ_TSIZE_0                                         0xE8817C

#define mmTPC2_QM_CQ_CTL_0                                           0xE88180

#define mmTPC2_QM_CQ_PTR_LO_1                                        0xE88184

#define mmTPC2_QM_CQ_PTR_HI_1                                        0xE88188

#define mmTPC2_QM_CQ_TSIZE_1                                         0xE8818C

#define mmTPC2_QM_CQ_CTL_1                                           0xE88190

#define mmTPC2_QM_CQ_PTR_LO_2                                        0xE88194

#define mmTPC2_QM_CQ_PTR_HI_2                                        0xE88198

#define mmTPC2_QM_CQ_TSIZE_2                                         0xE8819C

#define mmTPC2_QM_CQ_CTL_2                                           0xE881A0

#define mmTPC2_QM_CQ_PTR_LO_3                                        0xE881A4

#define mmTPC2_QM_CQ_PTR_HI_3                                        0xE881A8

#define mmTPC2_QM_CQ_TSIZE_3                                         0xE881AC

#define mmTPC2_QM_CQ_CTL_3                                           0xE881B0

#define mmTPC2_QM_CQ_PTR_LO_4                                        0xE881B4

#define mmTPC2_QM_CQ_PTR_HI_4                                        0xE881B8

#define mmTPC2_QM_CQ_TSIZE_4                                         0xE881BC

#define mmTPC2_QM_CQ_CTL_4                                           0xE881C0

#define mmTPC2_QM_CQ_PTR_LO_STS_0                                    0xE881C4

#define mmTPC2_QM_CQ_PTR_LO_STS_1                                    0xE881C8

#define mmTPC2_QM_CQ_PTR_LO_STS_2                                    0xE881CC

#define mmTPC2_QM_CQ_PTR_LO_STS_3                                    0xE881D0

#define mmTPC2_QM_CQ_PTR_LO_STS_4                                    0xE881D4

#define mmTPC2_QM_CQ_PTR_HI_STS_0                                    0xE881D8

#define mmTPC2_QM_CQ_PTR_HI_STS_1                                    0xE881DC

#define mmTPC2_QM_CQ_PTR_HI_STS_2                                    0xE881E0

#define mmTPC2_QM_CQ_PTR_HI_STS_3                                    0xE881E4

#define mmTPC2_QM_CQ_PTR_HI_STS_4                                    0xE881E8

#define mmTPC2_QM_CQ_TSIZE_STS_0                                     0xE881EC

#define mmTPC2_QM_CQ_TSIZE_STS_1                                     0xE881F0

#define mmTPC2_QM_CQ_TSIZE_STS_2                                     0xE881F4

#define mmTPC2_QM_CQ_TSIZE_STS_3                                     0xE881F8

#define mmTPC2_QM_CQ_TSIZE_STS_4                                     0xE881FC

#define mmTPC2_QM_CQ_CTL_STS_0                                       0xE88200

#define mmTPC2_QM_CQ_CTL_STS_1                                       0xE88204

#define mmTPC2_QM_CQ_CTL_STS_2                                       0xE88208

#define mmTPC2_QM_CQ_CTL_STS_3                                       0xE8820C

#define mmTPC2_QM_CQ_CTL_STS_4                                       0xE88210

#define mmTPC2_QM_CQ_IFIFO_CNT_0                                     0xE88214

#define mmTPC2_QM_CQ_IFIFO_CNT_1                                     0xE88218

#define mmTPC2_QM_CQ_IFIFO_CNT_2                                     0xE8821C

#define mmTPC2_QM_CQ_IFIFO_CNT_3                                     0xE88220

#define mmTPC2_QM_CQ_IFIFO_CNT_4                                     0xE88224

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0                             0xE88228

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1                             0xE8822C

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2                             0xE88230

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3                             0xE88234

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4                             0xE88238

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0                             0xE8823C

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1                             0xE88240

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2                             0xE88244

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3                             0xE88248

#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4                             0xE8824C

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0                             0xE88250

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1                             0xE88254

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2                             0xE88258

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3                             0xE8825C

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4                             0xE88260

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0                             0xE88264

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1                             0xE88268

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2                             0xE8826C

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3                             0xE88270

#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4                             0xE88274

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0                             0xE88278

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1                             0xE8827C

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2                             0xE88280

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3                             0xE88284

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4                             0xE88288

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0                             0xE8828C

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1                             0xE88290

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2                             0xE88294

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3                             0xE88298

#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4                             0xE8829C

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0                             0xE882A0

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1                             0xE882A4

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2                             0xE882A8

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3                             0xE882AC

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4                             0xE882B0

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0                             0xE882B4

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1                             0xE882B8

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2                             0xE882BC

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3                             0xE882C0

#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4                             0xE882C4

#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0                             0xE882C8

#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1                             0xE882CC

#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2                             0xE882D0

#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3                             0xE882D4

#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4                             0xE882D8

#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xE882E0

#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xE882E4

#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xE882E8

#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xE882EC

#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xE882F0

#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xE882F4

#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xE882F8

#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xE882FC

#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xE88300

#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xE88304

#define mmTPC2_QM_CP_FENCE0_RDATA_0                                  0xE88308

#define mmTPC2_QM_CP_FENCE0_RDATA_1                                  0xE8830C

#define mmTPC2_QM_CP_FENCE0_RDATA_2                                  0xE88310

#define mmTPC2_QM_CP_FENCE0_RDATA_3                                  0xE88314

#define mmTPC2_QM_CP_FENCE0_RDATA_4                                  0xE88318

#define mmTPC2_QM_CP_FENCE1_RDATA_0                                  0xE8831C

#define mmTPC2_QM_CP_FENCE1_RDATA_1                                  0xE88320

#define mmTPC2_QM_CP_FENCE1_RDATA_2                                  0xE88324

#define mmTPC2_QM_CP_FENCE1_RDATA_3                                  0xE88328

#define mmTPC2_QM_CP_FENCE1_RDATA_4                                  0xE8832C

#define mmTPC2_QM_CP_FENCE2_RDATA_0                                  0xE88330

#define mmTPC2_QM_CP_FENCE2_RDATA_1                                  0xE88334

#define mmTPC2_QM_CP_FENCE2_RDATA_2                                  0xE88338

#define mmTPC2_QM_CP_FENCE2_RDATA_3                                  0xE8833C

#define mmTPC2_QM_CP_FENCE2_RDATA_4                                  0xE88340

#define mmTPC2_QM_CP_FENCE3_RDATA_0                                  0xE88344

#define mmTPC2_QM_CP_FENCE3_RDATA_1                                  0xE88348

#define mmTPC2_QM_CP_FENCE3_RDATA_2                                  0xE8834C

#define mmTPC2_QM_CP_FENCE3_RDATA_3                                  0xE88350

#define mmTPC2_QM_CP_FENCE3_RDATA_4                                  0xE88354

#define mmTPC2_QM_CP_FENCE0_CNT_0                                    0xE88358

#define mmTPC2_QM_CP_FENCE0_CNT_1                                    0xE8835C

#define mmTPC2_QM_CP_FENCE0_CNT_2                                    0xE88360

#define mmTPC2_QM_CP_FENCE0_CNT_3                                    0xE88364

#define mmTPC2_QM_CP_FENCE0_CNT_4                                    0xE88368

#define mmTPC2_QM_CP_FENCE1_CNT_0                                    0xE8836C

#define mmTPC2_QM_CP_FENCE1_CNT_1                                    0xE88370

#define mmTPC2_QM_CP_FENCE1_CNT_2                                    0xE88374

#define mmTPC2_QM_CP_FENCE1_CNT_3                                    0xE88378

#define mmTPC2_QM_CP_FENCE1_CNT_4                                    0xE8837C

#define mmTPC2_QM_CP_FENCE2_CNT_0                                    0xE88380

#define mmTPC2_QM_CP_FENCE2_CNT_1                                    0xE88384

#define mmTPC2_QM_CP_FENCE2_CNT_2                                    0xE88388

#define mmTPC2_QM_CP_FENCE2_CNT_3                                    0xE8838C

#define mmTPC2_QM_CP_FENCE2_CNT_4                                    0xE88390

#define mmTPC2_QM_CP_FENCE3_CNT_0                                    0xE88394

#define mmTPC2_QM_CP_FENCE3_CNT_1                                    0xE88398

#define mmTPC2_QM_CP_FENCE3_CNT_2                                    0xE8839C

#define mmTPC2_QM_CP_FENCE3_CNT_3                                    0xE883A0

#define mmTPC2_QM_CP_FENCE3_CNT_4                                    0xE883A4

#define mmTPC2_QM_CP_STS_0                                           0xE883A8

#define mmTPC2_QM_CP_STS_1                                           0xE883AC

#define mmTPC2_QM_CP_STS_2                                           0xE883B0

#define mmTPC2_QM_CP_STS_3                                           0xE883B4

#define mmTPC2_QM_CP_STS_4                                           0xE883B8

#define mmTPC2_QM_CP_CURRENT_INST_LO_0                               0xE883BC

#define mmTPC2_QM_CP_CURRENT_INST_LO_1                               0xE883C0

#define mmTPC2_QM_CP_CURRENT_INST_LO_2                               0xE883C4

#define mmTPC2_QM_CP_CURRENT_INST_LO_3                               0xE883C8

#define mmTPC2_QM_CP_CURRENT_INST_LO_4                               0xE883CC

#define mmTPC2_QM_CP_CURRENT_INST_HI_0                               0xE883D0

#define mmTPC2_QM_CP_CURRENT_INST_HI_1                               0xE883D4

#define mmTPC2_QM_CP_CURRENT_INST_HI_2                               0xE883D8

#define mmTPC2_QM_CP_CURRENT_INST_HI_3                               0xE883DC

#define mmTPC2_QM_CP_CURRENT_INST_HI_4                               0xE883E0

#define mmTPC2_QM_CP_BARRIER_CFG_0                                   0xE883F4

#define mmTPC2_QM_CP_BARRIER_CFG_1                                   0xE883F8

#define mmTPC2_QM_CP_BARRIER_CFG_2                                   0xE883FC

#define mmTPC2_QM_CP_BARRIER_CFG_3                                   0xE88400

#define mmTPC2_QM_CP_BARRIER_CFG_4                                   0xE88404

#define mmTPC2_QM_CP_DBG_0_0                                         0xE88408

#define mmTPC2_QM_CP_DBG_0_1                                         0xE8840C

#define mmTPC2_QM_CP_DBG_0_2                                         0xE88410

#define mmTPC2_QM_CP_DBG_0_3                                         0xE88414

#define mmTPC2_QM_CP_DBG_0_4                                         0xE88418

#define mmTPC2_QM_CP_ARUSER_31_11_0                                  0xE8841C

#define mmTPC2_QM_CP_ARUSER_31_11_1                                  0xE88420

#define mmTPC2_QM_CP_ARUSER_31_11_2                                  0xE88424

#define mmTPC2_QM_CP_ARUSER_31_11_3                                  0xE88428

#define mmTPC2_QM_CP_ARUSER_31_11_4                                  0xE8842C

#define mmTPC2_QM_CP_AWUSER_31_11_0                                  0xE88430

#define mmTPC2_QM_CP_AWUSER_31_11_1                                  0xE88434

#define mmTPC2_QM_CP_AWUSER_31_11_2                                  0xE88438

#define mmTPC2_QM_CP_AWUSER_31_11_3                                  0xE8843C

#define mmTPC2_QM_CP_AWUSER_31_11_4                                  0xE88440

#define mmTPC2_QM_ARB_CFG_0                                          0xE88A00

#define mmTPC2_QM_ARB_CHOISE_Q_PUSH                                  0xE88A04

#define mmTPC2_QM_ARB_WRR_WEIGHT_0                                   0xE88A08

#define mmTPC2_QM_ARB_WRR_WEIGHT_1                                   0xE88A0C

#define mmTPC2_QM_ARB_WRR_WEIGHT_2                                   0xE88A10

#define mmTPC2_QM_ARB_WRR_WEIGHT_3                                   0xE88A14

#define mmTPC2_QM_ARB_CFG_1                                          0xE88A18

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0                               0xE88A20

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1                               0xE88A24

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2                               0xE88A28

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3                               0xE88A2C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4                               0xE88A30

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5                               0xE88A34

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6                               0xE88A38

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7                               0xE88A3C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8                               0xE88A40

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9                               0xE88A44

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10                              0xE88A48

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11                              0xE88A4C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12                              0xE88A50

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13                              0xE88A54

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14                              0xE88A58

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15                              0xE88A5C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16                              0xE88A60

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17                              0xE88A64

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18                              0xE88A68

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19                              0xE88A6C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20                              0xE88A70

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21                              0xE88A74

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22                              0xE88A78

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23                              0xE88A7C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24                              0xE88A80

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25                              0xE88A84

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26                              0xE88A88

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27                              0xE88A8C

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28                              0xE88A90

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29                              0xE88A94

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30                              0xE88A98

#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31                              0xE88A9C

#define mmTPC2_QM_ARB_MST_CRED_INC                                   0xE88AA0

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xE88AA4

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xE88AA8

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xE88AAC

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xE88AB0

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xE88AB4

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xE88AB8

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xE88ABC

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xE88AC0

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xE88AC4

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xE88AC8

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xE88ACC

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xE88AD0

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xE88AD4

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xE88AD8

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xE88ADC

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xE88AE0

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xE88AE4

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xE88AE8

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xE88AEC

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xE88AF0

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xE88AF4

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xE88AF8

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xE88AFC

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xE88B00

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xE88B04

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xE88B08

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xE88B0C

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xE88B10

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xE88B14

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xE88B18

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xE88B1C

#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xE88B20

#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xE88B28

#define mmTPC2_QM_ARB_MST_SLAVE_EN                                   0xE88B2C

#define mmTPC2_QM_ARB_MST_QUIET_PER                                  0xE88B34

#define mmTPC2_QM_ARB_SLV_CHOISE_WDT                                 0xE88B38

#define mmTPC2_QM_ARB_SLV_ID                                         0xE88B3C

#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT                               0xE88B44

#define mmTPC2_QM_ARB_MSG_AWUSER_31_11                               0xE88B48

#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP                            0xE88B4C

#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xE88B50

#define mmTPC2_QM_ARB_BASE_LO                                        0xE88B54

#define mmTPC2_QM_ARB_BASE_HI                                        0xE88B58

#define mmTPC2_QM_ARB_STATE_STS                                      0xE88B80

#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS                            0xE88B84

#define mmTPC2_QM_ARB_MSG_STS                                        0xE88B88

#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD                              0xE88B8C

#define mmTPC2_QM_ARB_ERR_CAUSE                                      0xE88B9C

#define mmTPC2_QM_ARB_ERR_MSG_EN                                     0xE88BA0

#define mmTPC2_QM_ARB_ERR_STS_DRP                                    0xE88BA8

#define mmTPC2_QM_ARB_MST_CRED_STS_0                                 0xE88BB0

#define mmTPC2_QM_ARB_MST_CRED_STS_1                                 0xE88BB4

#define mmTPC2_QM_ARB_MST_CRED_STS_2                                 0xE88BB8

#define mmTPC2_QM_ARB_MST_CRED_STS_3                                 0xE88BBC

#define mmTPC2_QM_ARB_MST_CRED_STS_4                                 0xE88BC0

#define mmTPC2_QM_ARB_MST_CRED_STS_5                                 0xE88BC4

#define mmTPC2_QM_ARB_MST_CRED_STS_6                                 0xE88BC8

#define mmTPC2_QM_ARB_MST_CRED_STS_7                                 0xE88BCC

#define mmTPC2_QM_ARB_MST_CRED_STS_8                                 0xE88BD0

#define mmTPC2_QM_ARB_MST_CRED_STS_9                                 0xE88BD4

#define mmTPC2_QM_ARB_MST_CRED_STS_10                                0xE88BD8

#define mmTPC2_QM_ARB_MST_CRED_STS_11                                0xE88BDC

#define mmTPC2_QM_ARB_MST_CRED_STS_12                                0xE88BE0

#define mmTPC2_QM_ARB_MST_CRED_STS_13                                0xE88BE4

#define mmTPC2_QM_ARB_MST_CRED_STS_14                                0xE88BE8

#define mmTPC2_QM_ARB_MST_CRED_STS_15                                0xE88BEC

#define mmTPC2_QM_ARB_MST_CRED_STS_16                                0xE88BF0

#define mmTPC2_QM_ARB_MST_CRED_STS_17                                0xE88BF4

#define mmTPC2_QM_ARB_MST_CRED_STS_18                                0xE88BF8

#define mmTPC2_QM_ARB_MST_CRED_STS_19                                0xE88BFC

#define mmTPC2_QM_ARB_MST_CRED_STS_20                                0xE88C00

#define mmTPC2_QM_ARB_MST_CRED_STS_21                                0xE88C04

#define mmTPC2_QM_ARB_MST_CRED_STS_22                                0xE88C08

#define mmTPC2_QM_ARB_MST_CRED_STS_23                                0xE88C0C

#define mmTPC2_QM_ARB_MST_CRED_STS_24                                0xE88C10

#define mmTPC2_QM_ARB_MST_CRED_STS_25                                0xE88C14

#define mmTPC2_QM_ARB_MST_CRED_STS_26                                0xE88C18

#define mmTPC2_QM_ARB_MST_CRED_STS_27                                0xE88C1C

#define mmTPC2_QM_ARB_MST_CRED_STS_28                                0xE88C20

#define mmTPC2_QM_ARB_MST_CRED_STS_29                                0xE88C24

#define mmTPC2_QM_ARB_MST_CRED_STS_30                                0xE88C28

#define mmTPC2_QM_ARB_MST_CRED_STS_31                                0xE88C2C

#define mmTPC2_QM_CGM_CFG                                            0xE88C70

#define mmTPC2_QM_CGM_STS                                            0xE88C74

#define mmTPC2_QM_CGM_CFG1                                           0xE88C78

#define mmTPC2_QM_LOCAL_RANGE_BASE                                   0xE88C80

#define mmTPC2_QM_LOCAL_RANGE_SIZE                                   0xE88C84

#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG                               0xE88C90

#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1                              0xE88C94

#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0                              0xE88C98

#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1                              0xE88C9C

#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0                              0xE88CA0

#define mmTPC2_QM_GLBL_AXCACHE                                       0xE88CA4

#define mmTPC2_QM_IND_GW_APB_CFG                                     0xE88CB0

#define mmTPC2_QM_IND_GW_APB_WDATA                                   0xE88CB4

#define mmTPC2_QM_IND_GW_APB_RDATA                                   0xE88CB8

#define mmTPC2_QM_IND_GW_APB_STATUS                                  0xE88CBC

#define mmTPC2_QM_GLBL_ERR_ADDR_LO                                   0xE88CD0

#define mmTPC2_QM_GLBL_ERR_ADDR_HI                                   0xE88CD4

#define mmTPC2_QM_GLBL_ERR_WDATA                                     0xE88CD8

#define mmTPC2_QM_GLBL_MEM_INIT_BUSY                                 0xE88D00

#endif /* ASIC_REG_TPC2_QM_REGS_H_ */