drm: bridge: adv7511: remove s32 format from i2s capabilities
[drm/drm-misc.git] / drivers / accel / habanalabs / include / gaudi / asic_reg / tpc6_qm_regs.h
blobe35ef7fd8b1c3d88be47967b95b9a4e4f684889f
1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
6 */
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_TPC6_QM_REGS_H_
14 #define ASIC_REG_TPC6_QM_REGS_H_
17 *****************************************
18 * TPC6_QM (Prototype: QMAN)
19 *****************************************
22 #define mmTPC6_QM_GLBL_CFG0 0xF88000
24 #define mmTPC6_QM_GLBL_CFG1 0xF88004
26 #define mmTPC6_QM_GLBL_PROT 0xF88008
28 #define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C
30 #define mmTPC6_QM_GLBL_SECURE_PROPS_0 0xF88010
32 #define mmTPC6_QM_GLBL_SECURE_PROPS_1 0xF88014
34 #define mmTPC6_QM_GLBL_SECURE_PROPS_2 0xF88018
36 #define mmTPC6_QM_GLBL_SECURE_PROPS_3 0xF8801C
38 #define mmTPC6_QM_GLBL_SECURE_PROPS_4 0xF88020
40 #define mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 0xF88024
42 #define mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 0xF88028
44 #define mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 0xF8802C
46 #define mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 0xF88030
48 #define mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 0xF88034
50 #define mmTPC6_QM_GLBL_STS0 0xF88038
52 #define mmTPC6_QM_GLBL_STS1_0 0xF88040
54 #define mmTPC6_QM_GLBL_STS1_1 0xF88044
56 #define mmTPC6_QM_GLBL_STS1_2 0xF88048
58 #define mmTPC6_QM_GLBL_STS1_3 0xF8804C
60 #define mmTPC6_QM_GLBL_STS1_4 0xF88050
62 #define mmTPC6_QM_GLBL_MSG_EN_0 0xF88054
64 #define mmTPC6_QM_GLBL_MSG_EN_1 0xF88058
66 #define mmTPC6_QM_GLBL_MSG_EN_2 0xF8805C
68 #define mmTPC6_QM_GLBL_MSG_EN_3 0xF88060
70 #define mmTPC6_QM_GLBL_MSG_EN_4 0xF88068
72 #define mmTPC6_QM_PQ_BASE_LO_0 0xF88070
74 #define mmTPC6_QM_PQ_BASE_LO_1 0xF88074
76 #define mmTPC6_QM_PQ_BASE_LO_2 0xF88078
78 #define mmTPC6_QM_PQ_BASE_LO_3 0xF8807C
80 #define mmTPC6_QM_PQ_BASE_HI_0 0xF88080
82 #define mmTPC6_QM_PQ_BASE_HI_1 0xF88084
84 #define mmTPC6_QM_PQ_BASE_HI_2 0xF88088
86 #define mmTPC6_QM_PQ_BASE_HI_3 0xF8808C
88 #define mmTPC6_QM_PQ_SIZE_0 0xF88090
90 #define mmTPC6_QM_PQ_SIZE_1 0xF88094
92 #define mmTPC6_QM_PQ_SIZE_2 0xF88098
94 #define mmTPC6_QM_PQ_SIZE_3 0xF8809C
96 #define mmTPC6_QM_PQ_PI_0 0xF880A0
98 #define mmTPC6_QM_PQ_PI_1 0xF880A4
100 #define mmTPC6_QM_PQ_PI_2 0xF880A8
102 #define mmTPC6_QM_PQ_PI_3 0xF880AC
104 #define mmTPC6_QM_PQ_CI_0 0xF880B0
106 #define mmTPC6_QM_PQ_CI_1 0xF880B4
108 #define mmTPC6_QM_PQ_CI_2 0xF880B8
110 #define mmTPC6_QM_PQ_CI_3 0xF880BC
112 #define mmTPC6_QM_PQ_CFG0_0 0xF880C0
114 #define mmTPC6_QM_PQ_CFG0_1 0xF880C4
116 #define mmTPC6_QM_PQ_CFG0_2 0xF880C8
118 #define mmTPC6_QM_PQ_CFG0_3 0xF880CC
120 #define mmTPC6_QM_PQ_CFG1_0 0xF880D0
122 #define mmTPC6_QM_PQ_CFG1_1 0xF880D4
124 #define mmTPC6_QM_PQ_CFG1_2 0xF880D8
126 #define mmTPC6_QM_PQ_CFG1_3 0xF880DC
128 #define mmTPC6_QM_PQ_ARUSER_31_11_0 0xF880E0
130 #define mmTPC6_QM_PQ_ARUSER_31_11_1 0xF880E4
132 #define mmTPC6_QM_PQ_ARUSER_31_11_2 0xF880E8
134 #define mmTPC6_QM_PQ_ARUSER_31_11_3 0xF880EC
136 #define mmTPC6_QM_PQ_STS0_0 0xF880F0
138 #define mmTPC6_QM_PQ_STS0_1 0xF880F4
140 #define mmTPC6_QM_PQ_STS0_2 0xF880F8
142 #define mmTPC6_QM_PQ_STS0_3 0xF880FC
144 #define mmTPC6_QM_PQ_STS1_0 0xF88100
146 #define mmTPC6_QM_PQ_STS1_1 0xF88104
148 #define mmTPC6_QM_PQ_STS1_2 0xF88108
150 #define mmTPC6_QM_PQ_STS1_3 0xF8810C
152 #define mmTPC6_QM_CQ_CFG0_0 0xF88110
154 #define mmTPC6_QM_CQ_CFG0_1 0xF88114
156 #define mmTPC6_QM_CQ_CFG0_2 0xF88118
158 #define mmTPC6_QM_CQ_CFG0_3 0xF8811C
160 #define mmTPC6_QM_CQ_CFG0_4 0xF88120
162 #define mmTPC6_QM_CQ_CFG1_0 0xF88124
164 #define mmTPC6_QM_CQ_CFG1_1 0xF88128
166 #define mmTPC6_QM_CQ_CFG1_2 0xF8812C
168 #define mmTPC6_QM_CQ_CFG1_3 0xF88130
170 #define mmTPC6_QM_CQ_CFG1_4 0xF88134
172 #define mmTPC6_QM_CQ_ARUSER_31_11_0 0xF88138
174 #define mmTPC6_QM_CQ_ARUSER_31_11_1 0xF8813C
176 #define mmTPC6_QM_CQ_ARUSER_31_11_2 0xF88140
178 #define mmTPC6_QM_CQ_ARUSER_31_11_3 0xF88144
180 #define mmTPC6_QM_CQ_ARUSER_31_11_4 0xF88148
182 #define mmTPC6_QM_CQ_STS0_0 0xF8814C
184 #define mmTPC6_QM_CQ_STS0_1 0xF88150
186 #define mmTPC6_QM_CQ_STS0_2 0xF88154
188 #define mmTPC6_QM_CQ_STS0_3 0xF88158
190 #define mmTPC6_QM_CQ_STS0_4 0xF8815C
192 #define mmTPC6_QM_CQ_STS1_0 0xF88160
194 #define mmTPC6_QM_CQ_STS1_1 0xF88164
196 #define mmTPC6_QM_CQ_STS1_2 0xF88168
198 #define mmTPC6_QM_CQ_STS1_3 0xF8816C
200 #define mmTPC6_QM_CQ_STS1_4 0xF88170
202 #define mmTPC6_QM_CQ_PTR_LO_0 0xF88174
204 #define mmTPC6_QM_CQ_PTR_HI_0 0xF88178
206 #define mmTPC6_QM_CQ_TSIZE_0 0xF8817C
208 #define mmTPC6_QM_CQ_CTL_0 0xF88180
210 #define mmTPC6_QM_CQ_PTR_LO_1 0xF88184
212 #define mmTPC6_QM_CQ_PTR_HI_1 0xF88188
214 #define mmTPC6_QM_CQ_TSIZE_1 0xF8818C
216 #define mmTPC6_QM_CQ_CTL_1 0xF88190
218 #define mmTPC6_QM_CQ_PTR_LO_2 0xF88194
220 #define mmTPC6_QM_CQ_PTR_HI_2 0xF88198
222 #define mmTPC6_QM_CQ_TSIZE_2 0xF8819C
224 #define mmTPC6_QM_CQ_CTL_2 0xF881A0
226 #define mmTPC6_QM_CQ_PTR_LO_3 0xF881A4
228 #define mmTPC6_QM_CQ_PTR_HI_3 0xF881A8
230 #define mmTPC6_QM_CQ_TSIZE_3 0xF881AC
232 #define mmTPC6_QM_CQ_CTL_3 0xF881B0
234 #define mmTPC6_QM_CQ_PTR_LO_4 0xF881B4
236 #define mmTPC6_QM_CQ_PTR_HI_4 0xF881B8
238 #define mmTPC6_QM_CQ_TSIZE_4 0xF881BC
240 #define mmTPC6_QM_CQ_CTL_4 0xF881C0
242 #define mmTPC6_QM_CQ_PTR_LO_STS_0 0xF881C4
244 #define mmTPC6_QM_CQ_PTR_LO_STS_1 0xF881C8
246 #define mmTPC6_QM_CQ_PTR_LO_STS_2 0xF881CC
248 #define mmTPC6_QM_CQ_PTR_LO_STS_3 0xF881D0
250 #define mmTPC6_QM_CQ_PTR_LO_STS_4 0xF881D4
252 #define mmTPC6_QM_CQ_PTR_HI_STS_0 0xF881D8
254 #define mmTPC6_QM_CQ_PTR_HI_STS_1 0xF881DC
256 #define mmTPC6_QM_CQ_PTR_HI_STS_2 0xF881E0
258 #define mmTPC6_QM_CQ_PTR_HI_STS_3 0xF881E4
260 #define mmTPC6_QM_CQ_PTR_HI_STS_4 0xF881E8
262 #define mmTPC6_QM_CQ_TSIZE_STS_0 0xF881EC
264 #define mmTPC6_QM_CQ_TSIZE_STS_1 0xF881F0
266 #define mmTPC6_QM_CQ_TSIZE_STS_2 0xF881F4
268 #define mmTPC6_QM_CQ_TSIZE_STS_3 0xF881F8
270 #define mmTPC6_QM_CQ_TSIZE_STS_4 0xF881FC
272 #define mmTPC6_QM_CQ_CTL_STS_0 0xF88200
274 #define mmTPC6_QM_CQ_CTL_STS_1 0xF88204
276 #define mmTPC6_QM_CQ_CTL_STS_2 0xF88208
278 #define mmTPC6_QM_CQ_CTL_STS_3 0xF8820C
280 #define mmTPC6_QM_CQ_CTL_STS_4 0xF88210
282 #define mmTPC6_QM_CQ_IFIFO_CNT_0 0xF88214
284 #define mmTPC6_QM_CQ_IFIFO_CNT_1 0xF88218
286 #define mmTPC6_QM_CQ_IFIFO_CNT_2 0xF8821C
288 #define mmTPC6_QM_CQ_IFIFO_CNT_3 0xF88220
290 #define mmTPC6_QM_CQ_IFIFO_CNT_4 0xF88224
292 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 0xF88228
294 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 0xF8822C
296 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 0xF88230
298 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 0xF88234
300 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 0xF88238
302 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 0xF8823C
304 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 0xF88240
306 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 0xF88244
308 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 0xF88248
310 #define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 0xF8824C
312 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 0xF88250
314 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 0xF88254
316 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 0xF88258
318 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 0xF8825C
320 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 0xF88260
322 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 0xF88264
324 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 0xF88268
326 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 0xF8826C
328 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 0xF88270
330 #define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 0xF88274
332 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 0xF88278
334 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 0xF8827C
336 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 0xF88280
338 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 0xF88284
340 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 0xF88288
342 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 0xF8828C
344 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 0xF88290
346 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 0xF88294
348 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 0xF88298
350 #define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 0xF8829C
352 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 0xF882A0
354 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 0xF882A4
356 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 0xF882A8
358 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 0xF882AC
360 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 0xF882B0
362 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 0xF882B4
364 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 0xF882B8
366 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 0xF882BC
368 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 0xF882C0
370 #define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 0xF882C4
372 #define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 0xF882C8
374 #define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 0xF882CC
376 #define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 0xF882D0
378 #define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 0xF882D4
380 #define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 0xF882D8
382 #define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF882E0
384 #define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF882E4
386 #define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF882E8
388 #define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF882EC
390 #define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF882F0
392 #define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF882F4
394 #define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF882F8
396 #define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF882FC
398 #define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF88300
400 #define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF88304
402 #define mmTPC6_QM_CP_FENCE0_RDATA_0 0xF88308
404 #define mmTPC6_QM_CP_FENCE0_RDATA_1 0xF8830C
406 #define mmTPC6_QM_CP_FENCE0_RDATA_2 0xF88310
408 #define mmTPC6_QM_CP_FENCE0_RDATA_3 0xF88314
410 #define mmTPC6_QM_CP_FENCE0_RDATA_4 0xF88318
412 #define mmTPC6_QM_CP_FENCE1_RDATA_0 0xF8831C
414 #define mmTPC6_QM_CP_FENCE1_RDATA_1 0xF88320
416 #define mmTPC6_QM_CP_FENCE1_RDATA_2 0xF88324
418 #define mmTPC6_QM_CP_FENCE1_RDATA_3 0xF88328
420 #define mmTPC6_QM_CP_FENCE1_RDATA_4 0xF8832C
422 #define mmTPC6_QM_CP_FENCE2_RDATA_0 0xF88330
424 #define mmTPC6_QM_CP_FENCE2_RDATA_1 0xF88334
426 #define mmTPC6_QM_CP_FENCE2_RDATA_2 0xF88338
428 #define mmTPC6_QM_CP_FENCE2_RDATA_3 0xF8833C
430 #define mmTPC6_QM_CP_FENCE2_RDATA_4 0xF88340
432 #define mmTPC6_QM_CP_FENCE3_RDATA_0 0xF88344
434 #define mmTPC6_QM_CP_FENCE3_RDATA_1 0xF88348
436 #define mmTPC6_QM_CP_FENCE3_RDATA_2 0xF8834C
438 #define mmTPC6_QM_CP_FENCE3_RDATA_3 0xF88350
440 #define mmTPC6_QM_CP_FENCE3_RDATA_4 0xF88354
442 #define mmTPC6_QM_CP_FENCE0_CNT_0 0xF88358
444 #define mmTPC6_QM_CP_FENCE0_CNT_1 0xF8835C
446 #define mmTPC6_QM_CP_FENCE0_CNT_2 0xF88360
448 #define mmTPC6_QM_CP_FENCE0_CNT_3 0xF88364
450 #define mmTPC6_QM_CP_FENCE0_CNT_4 0xF88368
452 #define mmTPC6_QM_CP_FENCE1_CNT_0 0xF8836C
454 #define mmTPC6_QM_CP_FENCE1_CNT_1 0xF88370
456 #define mmTPC6_QM_CP_FENCE1_CNT_2 0xF88374
458 #define mmTPC6_QM_CP_FENCE1_CNT_3 0xF88378
460 #define mmTPC6_QM_CP_FENCE1_CNT_4 0xF8837C
462 #define mmTPC6_QM_CP_FENCE2_CNT_0 0xF88380
464 #define mmTPC6_QM_CP_FENCE2_CNT_1 0xF88384
466 #define mmTPC6_QM_CP_FENCE2_CNT_2 0xF88388
468 #define mmTPC6_QM_CP_FENCE2_CNT_3 0xF8838C
470 #define mmTPC6_QM_CP_FENCE2_CNT_4 0xF88390
472 #define mmTPC6_QM_CP_FENCE3_CNT_0 0xF88394
474 #define mmTPC6_QM_CP_FENCE3_CNT_1 0xF88398
476 #define mmTPC6_QM_CP_FENCE3_CNT_2 0xF8839C
478 #define mmTPC6_QM_CP_FENCE3_CNT_3 0xF883A0
480 #define mmTPC6_QM_CP_FENCE3_CNT_4 0xF883A4
482 #define mmTPC6_QM_CP_STS_0 0xF883A8
484 #define mmTPC6_QM_CP_STS_1 0xF883AC
486 #define mmTPC6_QM_CP_STS_2 0xF883B0
488 #define mmTPC6_QM_CP_STS_3 0xF883B4
490 #define mmTPC6_QM_CP_STS_4 0xF883B8
492 #define mmTPC6_QM_CP_CURRENT_INST_LO_0 0xF883BC
494 #define mmTPC6_QM_CP_CURRENT_INST_LO_1 0xF883C0
496 #define mmTPC6_QM_CP_CURRENT_INST_LO_2 0xF883C4
498 #define mmTPC6_QM_CP_CURRENT_INST_LO_3 0xF883C8
500 #define mmTPC6_QM_CP_CURRENT_INST_LO_4 0xF883CC
502 #define mmTPC6_QM_CP_CURRENT_INST_HI_0 0xF883D0
504 #define mmTPC6_QM_CP_CURRENT_INST_HI_1 0xF883D4
506 #define mmTPC6_QM_CP_CURRENT_INST_HI_2 0xF883D8
508 #define mmTPC6_QM_CP_CURRENT_INST_HI_3 0xF883DC
510 #define mmTPC6_QM_CP_CURRENT_INST_HI_4 0xF883E0
512 #define mmTPC6_QM_CP_BARRIER_CFG_0 0xF883F4
514 #define mmTPC6_QM_CP_BARRIER_CFG_1 0xF883F8
516 #define mmTPC6_QM_CP_BARRIER_CFG_2 0xF883FC
518 #define mmTPC6_QM_CP_BARRIER_CFG_3 0xF88400
520 #define mmTPC6_QM_CP_BARRIER_CFG_4 0xF88404
522 #define mmTPC6_QM_CP_DBG_0_0 0xF88408
524 #define mmTPC6_QM_CP_DBG_0_1 0xF8840C
526 #define mmTPC6_QM_CP_DBG_0_2 0xF88410
528 #define mmTPC6_QM_CP_DBG_0_3 0xF88414
530 #define mmTPC6_QM_CP_DBG_0_4 0xF88418
532 #define mmTPC6_QM_CP_ARUSER_31_11_0 0xF8841C
534 #define mmTPC6_QM_CP_ARUSER_31_11_1 0xF88420
536 #define mmTPC6_QM_CP_ARUSER_31_11_2 0xF88424
538 #define mmTPC6_QM_CP_ARUSER_31_11_3 0xF88428
540 #define mmTPC6_QM_CP_ARUSER_31_11_4 0xF8842C
542 #define mmTPC6_QM_CP_AWUSER_31_11_0 0xF88430
544 #define mmTPC6_QM_CP_AWUSER_31_11_1 0xF88434
546 #define mmTPC6_QM_CP_AWUSER_31_11_2 0xF88438
548 #define mmTPC6_QM_CP_AWUSER_31_11_3 0xF8843C
550 #define mmTPC6_QM_CP_AWUSER_31_11_4 0xF88440
552 #define mmTPC6_QM_ARB_CFG_0 0xF88A00
554 #define mmTPC6_QM_ARB_CHOISE_Q_PUSH 0xF88A04
556 #define mmTPC6_QM_ARB_WRR_WEIGHT_0 0xF88A08
558 #define mmTPC6_QM_ARB_WRR_WEIGHT_1 0xF88A0C
560 #define mmTPC6_QM_ARB_WRR_WEIGHT_2 0xF88A10
562 #define mmTPC6_QM_ARB_WRR_WEIGHT_3 0xF88A14
564 #define mmTPC6_QM_ARB_CFG_1 0xF88A18
566 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_0 0xF88A20
568 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_1 0xF88A24
570 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_2 0xF88A28
572 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_3 0xF88A2C
574 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_4 0xF88A30
576 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_5 0xF88A34
578 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_6 0xF88A38
580 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_7 0xF88A3C
582 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_8 0xF88A40
584 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_9 0xF88A44
586 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_10 0xF88A48
588 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_11 0xF88A4C
590 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_12 0xF88A50
592 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_13 0xF88A54
594 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_14 0xF88A58
596 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_15 0xF88A5C
598 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_16 0xF88A60
600 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_17 0xF88A64
602 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_18 0xF88A68
604 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_19 0xF88A6C
606 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_20 0xF88A70
608 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_21 0xF88A74
610 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_22 0xF88A78
612 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_23 0xF88A7C
614 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_24 0xF88A80
616 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_25 0xF88A84
618 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_26 0xF88A88
620 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_27 0xF88A8C
622 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_28 0xF88A90
624 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_29 0xF88A94
626 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_30 0xF88A98
628 #define mmTPC6_QM_ARB_MST_AVAIL_CRED_31 0xF88A9C
630 #define mmTPC6_QM_ARB_MST_CRED_INC 0xF88AA0
632 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF88AA4
634 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF88AA8
636 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF88AAC
638 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF88AB0
640 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF88AB4
642 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF88AB8
644 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF88ABC
646 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF88AC0
648 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF88AC4
650 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF88AC8
652 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF88ACC
654 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF88AD0
656 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF88AD4
658 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF88AD8
660 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF88ADC
662 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF88AE0
664 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF88AE4
666 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF88AE8
668 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF88AEC
670 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF88AF0
672 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF88AF4
674 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF88AF8
676 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF88AFC
678 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF88B00
680 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF88B04
682 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF88B08
684 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF88B0C
686 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF88B10
688 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF88B14
690 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF88B18
692 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF88B1C
694 #define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF88B20
696 #define mmTPC6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF88B28
698 #define mmTPC6_QM_ARB_MST_SLAVE_EN 0xF88B2C
700 #define mmTPC6_QM_ARB_MST_QUIET_PER 0xF88B34
702 #define mmTPC6_QM_ARB_SLV_CHOISE_WDT 0xF88B38
704 #define mmTPC6_QM_ARB_SLV_ID 0xF88B3C
706 #define mmTPC6_QM_ARB_MSG_MAX_INFLIGHT 0xF88B44
708 #define mmTPC6_QM_ARB_MSG_AWUSER_31_11 0xF88B48
710 #define mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP 0xF88B4C
712 #define mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF88B50
714 #define mmTPC6_QM_ARB_BASE_LO 0xF88B54
716 #define mmTPC6_QM_ARB_BASE_HI 0xF88B58
718 #define mmTPC6_QM_ARB_STATE_STS 0xF88B80
720 #define mmTPC6_QM_ARB_CHOISE_FULLNESS_STS 0xF88B84
722 #define mmTPC6_QM_ARB_MSG_STS 0xF88B88
724 #define mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD 0xF88B8C
726 #define mmTPC6_QM_ARB_ERR_CAUSE 0xF88B9C
728 #define mmTPC6_QM_ARB_ERR_MSG_EN 0xF88BA0
730 #define mmTPC6_QM_ARB_ERR_STS_DRP 0xF88BA8
732 #define mmTPC6_QM_ARB_MST_CRED_STS_0 0xF88BB0
734 #define mmTPC6_QM_ARB_MST_CRED_STS_1 0xF88BB4
736 #define mmTPC6_QM_ARB_MST_CRED_STS_2 0xF88BB8
738 #define mmTPC6_QM_ARB_MST_CRED_STS_3 0xF88BBC
740 #define mmTPC6_QM_ARB_MST_CRED_STS_4 0xF88BC0
742 #define mmTPC6_QM_ARB_MST_CRED_STS_5 0xF88BC4
744 #define mmTPC6_QM_ARB_MST_CRED_STS_6 0xF88BC8
746 #define mmTPC6_QM_ARB_MST_CRED_STS_7 0xF88BCC
748 #define mmTPC6_QM_ARB_MST_CRED_STS_8 0xF88BD0
750 #define mmTPC6_QM_ARB_MST_CRED_STS_9 0xF88BD4
752 #define mmTPC6_QM_ARB_MST_CRED_STS_10 0xF88BD8
754 #define mmTPC6_QM_ARB_MST_CRED_STS_11 0xF88BDC
756 #define mmTPC6_QM_ARB_MST_CRED_STS_12 0xF88BE0
758 #define mmTPC6_QM_ARB_MST_CRED_STS_13 0xF88BE4
760 #define mmTPC6_QM_ARB_MST_CRED_STS_14 0xF88BE8
762 #define mmTPC6_QM_ARB_MST_CRED_STS_15 0xF88BEC
764 #define mmTPC6_QM_ARB_MST_CRED_STS_16 0xF88BF0
766 #define mmTPC6_QM_ARB_MST_CRED_STS_17 0xF88BF4
768 #define mmTPC6_QM_ARB_MST_CRED_STS_18 0xF88BF8
770 #define mmTPC6_QM_ARB_MST_CRED_STS_19 0xF88BFC
772 #define mmTPC6_QM_ARB_MST_CRED_STS_20 0xF88C00
774 #define mmTPC6_QM_ARB_MST_CRED_STS_21 0xF88C04
776 #define mmTPC6_QM_ARB_MST_CRED_STS_22 0xF88C08
778 #define mmTPC6_QM_ARB_MST_CRED_STS_23 0xF88C0C
780 #define mmTPC6_QM_ARB_MST_CRED_STS_24 0xF88C10
782 #define mmTPC6_QM_ARB_MST_CRED_STS_25 0xF88C14
784 #define mmTPC6_QM_ARB_MST_CRED_STS_26 0xF88C18
786 #define mmTPC6_QM_ARB_MST_CRED_STS_27 0xF88C1C
788 #define mmTPC6_QM_ARB_MST_CRED_STS_28 0xF88C20
790 #define mmTPC6_QM_ARB_MST_CRED_STS_29 0xF88C24
792 #define mmTPC6_QM_ARB_MST_CRED_STS_30 0xF88C28
794 #define mmTPC6_QM_ARB_MST_CRED_STS_31 0xF88C2C
796 #define mmTPC6_QM_CGM_CFG 0xF88C70
798 #define mmTPC6_QM_CGM_STS 0xF88C74
800 #define mmTPC6_QM_CGM_CFG1 0xF88C78
802 #define mmTPC6_QM_LOCAL_RANGE_BASE 0xF88C80
804 #define mmTPC6_QM_LOCAL_RANGE_SIZE 0xF88C84
806 #define mmTPC6_QM_CSMR_STRICT_PRIO_CFG 0xF88C90
808 #define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 0xF88C94
810 #define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 0xF88C98
812 #define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 0xF88C9C
814 #define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 0xF88CA0
816 #define mmTPC6_QM_GLBL_AXCACHE 0xF88CA4
818 #define mmTPC6_QM_IND_GW_APB_CFG 0xF88CB0
820 #define mmTPC6_QM_IND_GW_APB_WDATA 0xF88CB4
822 #define mmTPC6_QM_IND_GW_APB_RDATA 0xF88CB8
824 #define mmTPC6_QM_IND_GW_APB_STATUS 0xF88CBC
826 #define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88CD0
828 #define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88CD4
830 #define mmTPC6_QM_GLBL_ERR_WDATA 0xF88CD8
832 #define mmTPC6_QM_GLBL_MEM_INIT_BUSY 0xF88D00
834 #endif /* ASIC_REG_TPC6_QM_REGS_H_ */