1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2020 HabanaLabs, Ltd.
15 #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
16 #define CFG_BAR_SIZE 0x8000000ull /* 128MB */
18 #define CFG_BASE 0x7FFC000000ull
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
21 #define SRAM_BASE_ADDR 0x7FF0000000ull
22 #define SRAM_SIZE 0x1400000 /* 20MB */
24 #define SPI_FLASH_BASE_ADDR 0x7FF8000000ull
26 #define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull
27 #define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */
29 #define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull
30 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
32 #define DRAM_PHYS_BASE 0x0ull
34 #define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */
35 #define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */
37 #define GAUDI_MSI_ENTRIES 32
39 #define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */
43 #define PROT_BITS_OFFS 0xF80
45 #define MME_NUMBER_OF_MASTER_ENGINES 2
47 #define MME_NUMBER_OF_SLAVE_ENGINES 2
49 #define TPC_NUMBER_OF_ENGINES 8
51 #define DMA_NUMBER_OF_CHANNELS 8
53 #define NIC_NUMBER_OF_MACROS 5
55 #define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2)
57 #define NUMBER_OF_IF 8
59 #define DEVICE_CACHE_LINE_SIZE 128