drm/virtio: Add drm_panic support

[drm/drm-misc.git] / drivers / accel / habanalabs / include / gaudi2 / asic_reg / nic0_qpc0_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_NIC0_QPC0_REGS_H_
#define ASIC_REG_NIC0_QPC0_REGS_H_

/*
 *****************************************
 *   NIC0_QPC0
 *   (Prototype: NIC_QPC)
 *****************************************
 */

#define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000

#define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004

#define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008

#define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C

#define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010

#define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014

#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018

#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C

#define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020

#define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024

#define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028

#define mmNIC0_QPC0_AXI_PROT 0x541F030

#define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034

#define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038

#define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C

#define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040

#define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044

#define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048

#define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050

#define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054

#define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058

#define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C

#define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060

#define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064

#define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068

#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C

#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070

#define mmNIC0_QPC0_GW_BUSY 0x541F080

#define mmNIC0_QPC0_GW_CTRL 0x541F084

#define mmNIC0_QPC0_GW_DATA_0 0x541F08C

#define mmNIC0_QPC0_GW_DATA_1 0x541F090

#define mmNIC0_QPC0_GW_DATA_2 0x541F094

#define mmNIC0_QPC0_GW_DATA_3 0x541F098

#define mmNIC0_QPC0_GW_DATA_4 0x541F09C

#define mmNIC0_QPC0_GW_DATA_5 0x541F0A0

#define mmNIC0_QPC0_GW_DATA_6 0x541F0A4

#define mmNIC0_QPC0_GW_DATA_7 0x541F0A8

#define mmNIC0_QPC0_GW_DATA_8 0x541F0AC

#define mmNIC0_QPC0_GW_DATA_9 0x541F0B0

#define mmNIC0_QPC0_GW_DATA_10 0x541F0B4

#define mmNIC0_QPC0_GW_DATA_11 0x541F0B8

#define mmNIC0_QPC0_GW_DATA_12 0x541F0BC

#define mmNIC0_QPC0_GW_DATA_13 0x541F0C0

#define mmNIC0_QPC0_GW_DATA_14 0x541F0C4

#define mmNIC0_QPC0_GW_DATA_15 0x541F0C8

#define mmNIC0_QPC0_GW_DATA_16 0x541F0CC

#define mmNIC0_QPC0_GW_DATA_17 0x541F0D0

#define mmNIC0_QPC0_GW_DATA_18 0x541F0D4

#define mmNIC0_QPC0_GW_DATA_19 0x541F0D8

#define mmNIC0_QPC0_GW_DATA_20 0x541F0DC

#define mmNIC0_QPC0_GW_DATA_21 0x541F0E0

#define mmNIC0_QPC0_GW_DATA_22 0x541F0E4

#define mmNIC0_QPC0_GW_DATA_23 0x541F0E8

#define mmNIC0_QPC0_GW_DATA_24 0x541F0EC

#define mmNIC0_QPC0_GW_DATA_25 0x541F0F0

#define mmNIC0_QPC0_GW_DATA_26 0x541F0F4

#define mmNIC0_QPC0_GW_DATA_27 0x541F0F8

#define mmNIC0_QPC0_GW_DATA_28 0x541F0FC

#define mmNIC0_QPC0_GW_DATA_29 0x541F100

#define mmNIC0_QPC0_GW_DATA_30 0x541F104

#define mmNIC0_QPC0_GW_DATA_31 0x541F108

#define mmNIC0_QPC0_GW_MASK_0 0x541F124

#define mmNIC0_QPC0_GW_MASK_1 0x541F128

#define mmNIC0_QPC0_GW_MASK_2 0x541F12C

#define mmNIC0_QPC0_GW_MASK_3 0x541F130

#define mmNIC0_QPC0_GW_MASK_4 0x541F134

#define mmNIC0_QPC0_GW_MASK_5 0x541F138

#define mmNIC0_QPC0_GW_MASK_6 0x541F13C

#define mmNIC0_QPC0_GW_MASK_7 0x541F140

#define mmNIC0_QPC0_GW_MASK_8 0x541F144

#define mmNIC0_QPC0_GW_MASK_9 0x541F148

#define mmNIC0_QPC0_GW_MASK_10 0x541F14C

#define mmNIC0_QPC0_GW_MASK_11 0x541F150

#define mmNIC0_QPC0_GW_MASK_12 0x541F154

#define mmNIC0_QPC0_GW_MASK_13 0x541F158

#define mmNIC0_QPC0_GW_MASK_14 0x541F15C

#define mmNIC0_QPC0_GW_MASK_15 0x541F160

#define mmNIC0_QPC0_GW_MASK_16 0x541F164

#define mmNIC0_QPC0_GW_MASK_17 0x541F168

#define mmNIC0_QPC0_GW_MASK_18 0x541F16C

#define mmNIC0_QPC0_GW_MASK_19 0x541F170

#define mmNIC0_QPC0_GW_MASK_20 0x541F174

#define mmNIC0_QPC0_GW_MASK_21 0x541F178

#define mmNIC0_QPC0_GW_MASK_22 0x541F17C

#define mmNIC0_QPC0_GW_MASK_23 0x541F180

#define mmNIC0_QPC0_GW_MASK_24 0x541F184

#define mmNIC0_QPC0_GW_MASK_25 0x541F188

#define mmNIC0_QPC0_GW_MASK_26 0x541F18C

#define mmNIC0_QPC0_GW_MASK_27 0x541F190

#define mmNIC0_QPC0_GW_MASK_28 0x541F194

#define mmNIC0_QPC0_GW_MASK_29 0x541F198

#define mmNIC0_QPC0_GW_MASK_30 0x541F19C

#define mmNIC0_QPC0_GW_MASK_31 0x541F1A0

#define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0

#define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC

#define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200

#define mmNIC0_QPC0_CC_ROLLBACK 0x541F204

#define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208

#define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248

#define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C

#define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250

#define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254

#define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258

#define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C

#define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260

#define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264

#define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268

#define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C

#define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270

#define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274

#define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278

#define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C

#define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280

#define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284

#define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288

#define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8

#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC

#define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0

#define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4

#define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8

#define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC

#define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0

#define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4

#define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8

#define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC

#define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0

#define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4

#define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8

#define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC

#define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300

#define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304

#define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308

#define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348

#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8

#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC

#define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0

#define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4

#define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8

#define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC

#define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0

#define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4

#define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8

#define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC

#define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400

#define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404

#define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408

#define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C

#define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410

#define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414

#define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418

#define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C

#define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420

#define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424

#define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428

#define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C

#define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430

#define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434

#define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438

#define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C

#define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440

#define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444

#define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448

#define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C

#define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450

#define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454

#define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458

#define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C

#define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460

#define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464

#define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468

#define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C

#define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470

#define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474

#define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478

#define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C

#define mmNIC0_QPC0_DBG_INDICATION 0x541F480

#define mmNIC0_QPC0_WTD_WC_FSM 0x541F484

#define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488

#define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C

#define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490

#define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494

#define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498

#define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C

#define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0

#define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4

#define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0

#define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4

#define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8

#define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC

#define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0

#define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4

#define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8

#define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC

#define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0

#define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4

#define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8

#define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC

#define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0

#define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4

#define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8

#define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC

#define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0

#define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4

#define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8

#define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC

#define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500

#define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504

#define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600

#define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604

#define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608

#define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C

#define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610

#define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614

#define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618

#define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C

#define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620

#define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624

#define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628

#define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C

#define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648

#define mmNIC0_QPC0_DBG_CFG 0x541F64C

#define mmNIC0_QPC0_RES_RING0_PI 0x541F650

#define mmNIC0_QPC0_RES_RING0_CI 0x541F654

#define mmNIC0_QPC0_RES_RING0_CFG 0x541F658

#define mmNIC0_QPC0_RES_RING1_PI 0x541F65C

#define mmNIC0_QPC0_RES_RING1_CI 0x541F660

#define mmNIC0_QPC0_RES_RING1_CFG 0x541F664

#define mmNIC0_QPC0_RES_RING2_PI 0x541F668

#define mmNIC0_QPC0_RES_RING2_CI 0x541F66C

#define mmNIC0_QPC0_RES_RING2_CFG 0x541F670

#define mmNIC0_QPC0_RES_RING3_PI 0x541F674

#define mmNIC0_QPC0_RES_RING3_CI 0x541F678

#define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C

#define mmNIC0_QPC0_REQ_RING0_CI 0x541F680

#define mmNIC0_QPC0_REQ_RING1_CI 0x541F684

#define mmNIC0_QPC0_REQ_RING2_CI 0x541F688

#define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C

#define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690

#define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694

#define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698

#define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C

#define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0

#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4

#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8

#define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700

#define mmNIC0_QPC0_TMR_GW_VALID 0x541F704

#define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708

#define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C

#define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710

#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830

#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834

#define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838

#define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C

#define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840

#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844

#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848

#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C

#define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850

#define mmNIC0_QPC0_LBW_PROT 0x541F858

#define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C

#define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8

#define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC

#define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0

#define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4

#define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8

#define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918

#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C

#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920

#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924

#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928

#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C

#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930

#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934

#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938

#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958

#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C

#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960

#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964

#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968

#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C

#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970

#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974

#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978

#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C

#define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980

#define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984

#define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988

#define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C

#define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990

#define mmNIC0_QPC0_WTD_CONFIG 0x541F994

#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998

#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C

#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0

#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4

#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8

#define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC

#define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0

#define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4

#define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8

#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC

#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0

#define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4

#define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8

#define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC

#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0

#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4

#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8

#define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC

#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20

#define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24

#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40

#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44

#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48

#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C

#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50

#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54

#define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4

#define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8

#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */