drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12
  13 #ifndef ASIC_REG_PSOC_ETR_REGS_H_
  14 #define ASIC_REG_PSOC_ETR_REGS_H_
  15
  16 /*
  17  *****************************************
  18  *   PSOC_ETR
  19  *   (Prototype: ETR)
  20  *****************************************
  21  */
  22
  23 #define mmPSOC_ETR_RSZ 0x6C44004
  24
  25 #define mmPSOC_ETR_STS 0x6C4400C
  26
  27 #define mmPSOC_ETR_RRD 0x6C44010
  28
  29 #define mmPSOC_ETR_RRP 0x6C44014
  30
  31 #define mmPSOC_ETR_RWP 0x6C44018
  32
  33 #define mmPSOC_ETR_TRG 0x6C4401C
  34
  35 #define mmPSOC_ETR_CTL 0x6C44020
  36
  37 #define mmPSOC_ETR_RWD 0x6C44024
  38
  39 #define mmPSOC_ETR_MODE 0x6C44028
  40
  41 #define mmPSOC_ETR_LBUFLEVEL 0x6C4402C
  42
  43 #define mmPSOC_ETR_CBUFLEVEL 0x6C44030
  44
  45 #define mmPSOC_ETR_BUFWM 0x6C44034
  46
  47 #define mmPSOC_ETR_RRPHI 0x6C44038
  48
  49 #define mmPSOC_ETR_RWPHI 0x6C4403C
  50
  51 #define mmPSOC_ETR_AXICTL 0x6C44110
  52
  53 #define mmPSOC_ETR_DBALO 0x6C44118
  54
  55 #define mmPSOC_ETR_DBAHI 0x6C4411C
  56
  57 #define mmPSOC_ETR_FFSR 0x6C44300
  58
  59 #define mmPSOC_ETR_FFCR 0x6C44304
  60
  61 #define mmPSOC_ETR_PSCR 0x6C44308
  62
  63 #define mmPSOC_ETR_ITMISCOP0 0x6C44EE0
  64
  65 #define mmPSOC_ETR_ITTRFLIN 0x6C44EE8
  66
  67 #define mmPSOC_ETR_ITATBDATA0 0x6C44EEC
  68
  69 #define mmPSOC_ETR_ITATBCTR2 0x6C44EF0
  70
  71 #define mmPSOC_ETR_ITATBCTR1 0x6C44EF4
  72
  73 #define mmPSOC_ETR_ITATBCTR0 0x6C44EF8
  74
  75 #define mmPSOC_ETR_ITCTRL 0x6C44F00
  76
  77 #define mmPSOC_ETR_CLAIMSET 0x6C44FA0
  78
  79 #define mmPSOC_ETR_CLAIMCLR 0x6C44FA4
  80
  81 #define mmPSOC_ETR_LAR 0x6C44FB0
  82
  83 #define mmPSOC_ETR_LSR 0x6C44FB4
  84
  85 #define mmPSOC_ETR_AUTHSTATUS 0x6C44FB8
  86
  87 #define mmPSOC_ETR_DEVID 0x6C44FC8
  88
  89 #define mmPSOC_ETR_DEVTYPE 0x6C44FCC
  90
  91 #define mmPSOC_ETR_PERIPHID4 0x6C44FD0
  92
  93 #define mmPSOC_ETR_PERIPHID5 0x6C44FD4
  94
  95 #define mmPSOC_ETR_PERIPHID6 0x6C44FD8
  96
  97 #define mmPSOC_ETR_PERIPHID7 0x6C44FDC
  98
  99 #define mmPSOC_ETR_PERIPHID0 0x6C44FE0
 100
 101 #define mmPSOC_ETR_PERIPHID1 0x6C44FE4
 102
 103 #define mmPSOC_ETR_PERIPHID2 0x6C44FE8
 104
 105 #define mmPSOC_ETR_PERIPHID3 0x6C44FEC
 106
 107 #define mmPSOC_ETR_COMPID0 0x6C44FF0
 108
 109 #define mmPSOC_ETR_COMPID1 0x6C44FF4
 110
 111 #define mmPSOC_ETR_COMPID2 0x6C44FF8
 112
 113 #define mmPSOC_ETR_COMPID3 0x6C44FFC
 114
 115 #endif /* ASIC_REG_PSOC_ETR_REGS_H_ */