1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_DMA_MACRO_REGS_H_
14 #define ASIC_REG_DMA_MACRO_REGS_H_
17 *****************************************
18 * DMA_MACRO (Prototype: DMA_MACRO)
19 *****************************************
22 #define mmDMA_MACRO_LBW_RANGE_HIT_BLOCK 0x4B0000
24 #define mmDMA_MACRO_LBW_RANGE_MASK_0 0x4B0004
26 #define mmDMA_MACRO_LBW_RANGE_MASK_1 0x4B0008
28 #define mmDMA_MACRO_LBW_RANGE_MASK_2 0x4B000C
30 #define mmDMA_MACRO_LBW_RANGE_MASK_3 0x4B0010
32 #define mmDMA_MACRO_LBW_RANGE_MASK_4 0x4B0014
34 #define mmDMA_MACRO_LBW_RANGE_MASK_5 0x4B0018
36 #define mmDMA_MACRO_LBW_RANGE_MASK_6 0x4B001C
38 #define mmDMA_MACRO_LBW_RANGE_MASK_7 0x4B0020
40 #define mmDMA_MACRO_LBW_RANGE_MASK_8 0x4B0024
42 #define mmDMA_MACRO_LBW_RANGE_MASK_9 0x4B0028
44 #define mmDMA_MACRO_LBW_RANGE_MASK_10 0x4B002C
46 #define mmDMA_MACRO_LBW_RANGE_MASK_11 0x4B0030
48 #define mmDMA_MACRO_LBW_RANGE_MASK_12 0x4B0034
50 #define mmDMA_MACRO_LBW_RANGE_MASK_13 0x4B0038
52 #define mmDMA_MACRO_LBW_RANGE_MASK_14 0x4B003C
54 #define mmDMA_MACRO_LBW_RANGE_MASK_15 0x4B0040
56 #define mmDMA_MACRO_LBW_RANGE_BASE_0 0x4B0044
58 #define mmDMA_MACRO_LBW_RANGE_BASE_1 0x4B0048
60 #define mmDMA_MACRO_LBW_RANGE_BASE_2 0x4B004C
62 #define mmDMA_MACRO_LBW_RANGE_BASE_3 0x4B0050
64 #define mmDMA_MACRO_LBW_RANGE_BASE_4 0x4B0054
66 #define mmDMA_MACRO_LBW_RANGE_BASE_5 0x4B0058
68 #define mmDMA_MACRO_LBW_RANGE_BASE_6 0x4B005C
70 #define mmDMA_MACRO_LBW_RANGE_BASE_7 0x4B0060
72 #define mmDMA_MACRO_LBW_RANGE_BASE_8 0x4B0064
74 #define mmDMA_MACRO_LBW_RANGE_BASE_9 0x4B0068
76 #define mmDMA_MACRO_LBW_RANGE_BASE_10 0x4B006C
78 #define mmDMA_MACRO_LBW_RANGE_BASE_11 0x4B0070
80 #define mmDMA_MACRO_LBW_RANGE_BASE_12 0x4B0074
82 #define mmDMA_MACRO_LBW_RANGE_BASE_13 0x4B0078
84 #define mmDMA_MACRO_LBW_RANGE_BASE_14 0x4B007C
86 #define mmDMA_MACRO_LBW_RANGE_BASE_15 0x4B0080
88 #define mmDMA_MACRO_HBW_RANGE_HIT_BLOCK 0x4B0084
90 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_0 0x4B00A8
92 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_1 0x4B00AC
94 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_2 0x4B00B0
96 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_3 0x4B00B4
98 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_4 0x4B00B8
100 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_5 0x4B00BC
102 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_6 0x4B00C0
104 #define mmDMA_MACRO_HBW_RANGE_MASK_49_32_7 0x4B00C4
106 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_0 0x4B00C8
108 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_1 0x4B00CC
110 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_2 0x4B00D0
112 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_3 0x4B00D4
114 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_4 0x4B00D8
116 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_5 0x4B00DC
118 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_6 0x4B00E0
120 #define mmDMA_MACRO_HBW_RANGE_MASK_31_0_7 0x4B00E4
122 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_0 0x4B00E8
124 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_1 0x4B00EC
126 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_2 0x4B00F0
128 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_3 0x4B00F4
130 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_4 0x4B00F8
132 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_5 0x4B00FC
134 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_6 0x4B0100
136 #define mmDMA_MACRO_HBW_RANGE_BASE_49_32_7 0x4B0104
138 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_0 0x4B0108
140 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_1 0x4B010C
142 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_2 0x4B0110
144 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_3 0x4B0114
146 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_4 0x4B0118
148 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_5 0x4B011C
150 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_6 0x4B0120
152 #define mmDMA_MACRO_HBW_RANGE_BASE_31_0_7 0x4B0124
154 #define mmDMA_MACRO_WRITE_EN 0x4B0128
156 #define mmDMA_MACRO_WRITE_CREDIT 0x4B012C
158 #define mmDMA_MACRO_READ_EN 0x4B0130
160 #define mmDMA_MACRO_READ_CREDIT 0x4B0134
162 #define mmDMA_MACRO_SRAM_BUSY 0x4B0138
164 #define mmDMA_MACRO_RAZWI_LBW_WT_VLD 0x4B013C
166 #define mmDMA_MACRO_RAZWI_LBW_WT_ID 0x4B0140
168 #define mmDMA_MACRO_RAZWI_LBW_RD_VLD 0x4B0144
170 #define mmDMA_MACRO_RAZWI_LBW_RD_ID 0x4B0148
172 #define mmDMA_MACRO_RAZWI_HBW_WT_VLD 0x4B014C
174 #define mmDMA_MACRO_RAZWI_HBW_WT_ID 0x4B0150
176 #define mmDMA_MACRO_RAZWI_HBW_RD_VLD 0x4B0154
178 #define mmDMA_MACRO_RAZWI_HBW_RD_ID 0x4B0158
180 #endif /* ASIC_REG_DMA_MACRO_REGS_H_ */