drm: bridge: adv7511: remove s32 format from i2s capabilities

[drm/drm-misc.git] / drivers / accel / habanalabs / include / goya / asic_reg / mme1_rtr_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_MME1_RTR_REGS_H_
#define ASIC_REG_MME1_RTR_REGS_H_

/*
 *****************************************
 *   MME1_RTR (Prototype: MME_RTR)
 *****************************************
 */

#define mmMME1_RTR_HBW_RD_RQ_E_ARB                                   0x40100

#define mmMME1_RTR_HBW_RD_RQ_W_ARB                                   0x40104

#define mmMME1_RTR_HBW_RD_RQ_N_ARB                                   0x40108

#define mmMME1_RTR_HBW_RD_RQ_S_ARB                                   0x4010C

#define mmMME1_RTR_HBW_RD_RQ_L_ARB                                   0x40110

#define mmMME1_RTR_HBW_E_ARB_MAX                                     0x40120

#define mmMME1_RTR_HBW_W_ARB_MAX                                     0x40124

#define mmMME1_RTR_HBW_N_ARB_MAX                                     0x40128

#define mmMME1_RTR_HBW_S_ARB_MAX                                     0x4012C

#define mmMME1_RTR_HBW_L_ARB_MAX                                     0x40130

#define mmMME1_RTR_HBW_RD_RS_MAX_CREDIT                              0x40140

#define mmMME1_RTR_HBW_WR_RQ_MAX_CREDIT                              0x40144

#define mmMME1_RTR_HBW_RD_RQ_MAX_CREDIT                              0x40148

#define mmMME1_RTR_HBW_RD_RS_E_ARB                                   0x40150

#define mmMME1_RTR_HBW_RD_RS_W_ARB                                   0x40154

#define mmMME1_RTR_HBW_RD_RS_N_ARB                                   0x40158

#define mmMME1_RTR_HBW_RD_RS_S_ARB                                   0x4015C

#define mmMME1_RTR_HBW_RD_RS_L_ARB                                   0x40160

#define mmMME1_RTR_HBW_WR_RQ_E_ARB                                   0x40170

#define mmMME1_RTR_HBW_WR_RQ_W_ARB                                   0x40174

#define mmMME1_RTR_HBW_WR_RQ_N_ARB                                   0x40178

#define mmMME1_RTR_HBW_WR_RQ_S_ARB                                   0x4017C

#define mmMME1_RTR_HBW_WR_RQ_L_ARB                                   0x40180

#define mmMME1_RTR_HBW_WR_RS_E_ARB                                   0x40190

#define mmMME1_RTR_HBW_WR_RS_W_ARB                                   0x40194

#define mmMME1_RTR_HBW_WR_RS_N_ARB                                   0x40198

#define mmMME1_RTR_HBW_WR_RS_S_ARB                                   0x4019C

#define mmMME1_RTR_HBW_WR_RS_L_ARB                                   0x401A0

#define mmMME1_RTR_LBW_RD_RQ_E_ARB                                   0x40200

#define mmMME1_RTR_LBW_RD_RQ_W_ARB                                   0x40204

#define mmMME1_RTR_LBW_RD_RQ_N_ARB                                   0x40208

#define mmMME1_RTR_LBW_RD_RQ_S_ARB                                   0x4020C

#define mmMME1_RTR_LBW_RD_RQ_L_ARB                                   0x40210

#define mmMME1_RTR_LBW_E_ARB_MAX                                     0x40220

#define mmMME1_RTR_LBW_W_ARB_MAX                                     0x40224

#define mmMME1_RTR_LBW_N_ARB_MAX                                     0x40228

#define mmMME1_RTR_LBW_S_ARB_MAX                                     0x4022C

#define mmMME1_RTR_LBW_L_ARB_MAX                                     0x40230

#define mmMME1_RTR_LBW_SRAM_MAX_CREDIT                               0x40240

#define mmMME1_RTR_LBW_RD_RS_E_ARB                                   0x40250

#define mmMME1_RTR_LBW_RD_RS_W_ARB                                   0x40254

#define mmMME1_RTR_LBW_RD_RS_N_ARB                                   0x40258

#define mmMME1_RTR_LBW_RD_RS_S_ARB                                   0x4025C

#define mmMME1_RTR_LBW_RD_RS_L_ARB                                   0x40260

#define mmMME1_RTR_LBW_WR_RQ_E_ARB                                   0x40270

#define mmMME1_RTR_LBW_WR_RQ_W_ARB                                   0x40274

#define mmMME1_RTR_LBW_WR_RQ_N_ARB                                   0x40278

#define mmMME1_RTR_LBW_WR_RQ_S_ARB                                   0x4027C

#define mmMME1_RTR_LBW_WR_RQ_L_ARB                                   0x40280

#define mmMME1_RTR_LBW_WR_RS_E_ARB                                   0x40290

#define mmMME1_RTR_LBW_WR_RS_W_ARB                                   0x40294

#define mmMME1_RTR_LBW_WR_RS_N_ARB                                   0x40298

#define mmMME1_RTR_LBW_WR_RS_S_ARB                                   0x4029C

#define mmMME1_RTR_LBW_WR_RS_L_ARB                                   0x402A0

#define mmMME1_RTR_DBG_E_ARB                                         0x40300

#define mmMME1_RTR_DBG_W_ARB                                         0x40304

#define mmMME1_RTR_DBG_N_ARB                                         0x40308

#define mmMME1_RTR_DBG_S_ARB                                         0x4030C

#define mmMME1_RTR_DBG_L_ARB                                         0x40310

#define mmMME1_RTR_DBG_E_ARB_MAX                                     0x40320

#define mmMME1_RTR_DBG_W_ARB_MAX                                     0x40324

#define mmMME1_RTR_DBG_N_ARB_MAX                                     0x40328

#define mmMME1_RTR_DBG_S_ARB_MAX                                     0x4032C

#define mmMME1_RTR_DBG_L_ARB_MAX                                     0x40330

#define mmMME1_RTR_SPLIT_COEF_0                                      0x40400

#define mmMME1_RTR_SPLIT_COEF_1                                      0x40404

#define mmMME1_RTR_SPLIT_COEF_2                                      0x40408

#define mmMME1_RTR_SPLIT_COEF_3                                      0x4040C

#define mmMME1_RTR_SPLIT_COEF_4                                      0x40410

#define mmMME1_RTR_SPLIT_COEF_5                                      0x40414

#define mmMME1_RTR_SPLIT_COEF_6                                      0x40418

#define mmMME1_RTR_SPLIT_COEF_7                                      0x4041C

#define mmMME1_RTR_SPLIT_COEF_8                                      0x40420

#define mmMME1_RTR_SPLIT_COEF_9                                      0x40424

#define mmMME1_RTR_SPLIT_CFG                                         0x40440

#define mmMME1_RTR_SPLIT_RD_SAT                                      0x40444

#define mmMME1_RTR_SPLIT_RD_RST_TOKEN                                0x40448

#define mmMME1_RTR_SPLIT_RD_TIMEOUT_0                                0x4044C

#define mmMME1_RTR_SPLIT_RD_TIMEOUT_1                                0x40450

#define mmMME1_RTR_SPLIT_WR_SAT                                      0x40454

#define mmMME1_RTR_WPLIT_WR_TST_TOLEN                                0x40458

#define mmMME1_RTR_SPLIT_WR_TIMEOUT_0                                0x4045C

#define mmMME1_RTR_SPLIT_WR_TIMEOUT_1                                0x40460

#define mmMME1_RTR_HBW_RANGE_HIT                                     0x40470

#define mmMME1_RTR_HBW_RANGE_MASK_L_0                                0x40480

#define mmMME1_RTR_HBW_RANGE_MASK_L_1                                0x40484

#define mmMME1_RTR_HBW_RANGE_MASK_L_2                                0x40488

#define mmMME1_RTR_HBW_RANGE_MASK_L_3                                0x4048C

#define mmMME1_RTR_HBW_RANGE_MASK_L_4                                0x40490

#define mmMME1_RTR_HBW_RANGE_MASK_L_5                                0x40494

#define mmMME1_RTR_HBW_RANGE_MASK_L_6                                0x40498

#define mmMME1_RTR_HBW_RANGE_MASK_L_7                                0x4049C

#define mmMME1_RTR_HBW_RANGE_MASK_H_0                                0x404A0

#define mmMME1_RTR_HBW_RANGE_MASK_H_1                                0x404A4

#define mmMME1_RTR_HBW_RANGE_MASK_H_2                                0x404A8

#define mmMME1_RTR_HBW_RANGE_MASK_H_3                                0x404AC

#define mmMME1_RTR_HBW_RANGE_MASK_H_4                                0x404B0

#define mmMME1_RTR_HBW_RANGE_MASK_H_5                                0x404B4

#define mmMME1_RTR_HBW_RANGE_MASK_H_6                                0x404B8

#define mmMME1_RTR_HBW_RANGE_MASK_H_7                                0x404BC

#define mmMME1_RTR_HBW_RANGE_BASE_L_0                                0x404C0

#define mmMME1_RTR_HBW_RANGE_BASE_L_1                                0x404C4

#define mmMME1_RTR_HBW_RANGE_BASE_L_2                                0x404C8

#define mmMME1_RTR_HBW_RANGE_BASE_L_3                                0x404CC

#define mmMME1_RTR_HBW_RANGE_BASE_L_4                                0x404D0

#define mmMME1_RTR_HBW_RANGE_BASE_L_5                                0x404D4

#define mmMME1_RTR_HBW_RANGE_BASE_L_6                                0x404D8

#define mmMME1_RTR_HBW_RANGE_BASE_L_7                                0x404DC

#define mmMME1_RTR_HBW_RANGE_BASE_H_0                                0x404E0

#define mmMME1_RTR_HBW_RANGE_BASE_H_1                                0x404E4

#define mmMME1_RTR_HBW_RANGE_BASE_H_2                                0x404E8

#define mmMME1_RTR_HBW_RANGE_BASE_H_3                                0x404EC

#define mmMME1_RTR_HBW_RANGE_BASE_H_4                                0x404F0

#define mmMME1_RTR_HBW_RANGE_BASE_H_5                                0x404F4

#define mmMME1_RTR_HBW_RANGE_BASE_H_6                                0x404F8

#define mmMME1_RTR_HBW_RANGE_BASE_H_7                                0x404FC

#define mmMME1_RTR_LBW_RANGE_HIT                                     0x40500

#define mmMME1_RTR_LBW_RANGE_MASK_0                                  0x40510

#define mmMME1_RTR_LBW_RANGE_MASK_1                                  0x40514

#define mmMME1_RTR_LBW_RANGE_MASK_2                                  0x40518

#define mmMME1_RTR_LBW_RANGE_MASK_3                                  0x4051C

#define mmMME1_RTR_LBW_RANGE_MASK_4                                  0x40520

#define mmMME1_RTR_LBW_RANGE_MASK_5                                  0x40524

#define mmMME1_RTR_LBW_RANGE_MASK_6                                  0x40528

#define mmMME1_RTR_LBW_RANGE_MASK_7                                  0x4052C

#define mmMME1_RTR_LBW_RANGE_MASK_8                                  0x40530

#define mmMME1_RTR_LBW_RANGE_MASK_9                                  0x40534

#define mmMME1_RTR_LBW_RANGE_MASK_10                                 0x40538

#define mmMME1_RTR_LBW_RANGE_MASK_11                                 0x4053C

#define mmMME1_RTR_LBW_RANGE_MASK_12                                 0x40540

#define mmMME1_RTR_LBW_RANGE_MASK_13                                 0x40544

#define mmMME1_RTR_LBW_RANGE_MASK_14                                 0x40548

#define mmMME1_RTR_LBW_RANGE_MASK_15                                 0x4054C

#define mmMME1_RTR_LBW_RANGE_BASE_0                                  0x40550

#define mmMME1_RTR_LBW_RANGE_BASE_1                                  0x40554

#define mmMME1_RTR_LBW_RANGE_BASE_2                                  0x40558

#define mmMME1_RTR_LBW_RANGE_BASE_3                                  0x4055C

#define mmMME1_RTR_LBW_RANGE_BASE_4                                  0x40560

#define mmMME1_RTR_LBW_RANGE_BASE_5                                  0x40564

#define mmMME1_RTR_LBW_RANGE_BASE_6                                  0x40568

#define mmMME1_RTR_LBW_RANGE_BASE_7                                  0x4056C

#define mmMME1_RTR_LBW_RANGE_BASE_8                                  0x40570

#define mmMME1_RTR_LBW_RANGE_BASE_9                                  0x40574

#define mmMME1_RTR_LBW_RANGE_BASE_10                                 0x40578

#define mmMME1_RTR_LBW_RANGE_BASE_11                                 0x4057C

#define mmMME1_RTR_LBW_RANGE_BASE_12                                 0x40580

#define mmMME1_RTR_LBW_RANGE_BASE_13                                 0x40584

#define mmMME1_RTR_LBW_RANGE_BASE_14                                 0x40588

#define mmMME1_RTR_LBW_RANGE_BASE_15                                 0x4058C

#define mmMME1_RTR_RGLTR                                             0x40590

#define mmMME1_RTR_RGLTR_WR_RESULT                                   0x40594

#define mmMME1_RTR_RGLTR_RD_RESULT                                   0x40598

#define mmMME1_RTR_SCRAMB_EN                                         0x40600

#define mmMME1_RTR_NON_LIN_SCRAMB                                    0x40604

#endif /* ASIC_REG_MME1_RTR_REGS_H_ */