drm: bridge: adv7511: remove s32 format from i2s capabilities
[drm/drm-misc.git] / drivers / accel / habanalabs / include / goya / asic_reg / mme_cmdq_masks.h
blobfe7d95bdcef9c0270ff4af69e5b1074ad52fbcde
1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
6 */
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_MME_CMDQ_MASKS_H_
14 #define ASIC_REG_MME_CMDQ_MASKS_H_
17 *****************************************
18 * MME_CMDQ (Prototype: CMDQ)
19 *****************************************
22 /* MME_CMDQ_GLBL_CFG0 */
23 #define MME_CMDQ_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME_CMDQ_GLBL_CFG0_PQF_EN_MASK 0x1
25 #define MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT 1
26 #define MME_CMDQ_GLBL_CFG0_CQF_EN_MASK 0x2
27 #define MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT 2
28 #define MME_CMDQ_GLBL_CFG0_CP_EN_MASK 0x4
29 #define MME_CMDQ_GLBL_CFG0_DMA_EN_SHIFT 3
30 #define MME_CMDQ_GLBL_CFG0_DMA_EN_MASK 0x8
32 /* MME_CMDQ_GLBL_CFG1 */
33 #define MME_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT 0
34 #define MME_CMDQ_GLBL_CFG1_PQF_STOP_MASK 0x1
35 #define MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT 1
36 #define MME_CMDQ_GLBL_CFG1_CQF_STOP_MASK 0x2
37 #define MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT 2
38 #define MME_CMDQ_GLBL_CFG1_CP_STOP_MASK 0x4
39 #define MME_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT 3
40 #define MME_CMDQ_GLBL_CFG1_DMA_STOP_MASK 0x8
41 #define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT 8
42 #define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK 0x100
43 #define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT 9
44 #define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200
45 #define MME_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT 10
46 #define MME_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x400
47 #define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT 11
48 #define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800
50 /* MME_CMDQ_GLBL_PROT */
51 #define MME_CMDQ_GLBL_PROT_PQF_PROT_SHIFT 0
52 #define MME_CMDQ_GLBL_PROT_PQF_PROT_MASK 0x1
53 #define MME_CMDQ_GLBL_PROT_CQF_PROT_SHIFT 1
54 #define MME_CMDQ_GLBL_PROT_CQF_PROT_MASK 0x2
55 #define MME_CMDQ_GLBL_PROT_CP_PROT_SHIFT 2
56 #define MME_CMDQ_GLBL_PROT_CP_PROT_MASK 0x4
57 #define MME_CMDQ_GLBL_PROT_DMA_PROT_SHIFT 3
58 #define MME_CMDQ_GLBL_PROT_DMA_PROT_MASK 0x8
59 #define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT 4
60 #define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK 0x10
61 #define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT 5
62 #define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK 0x20
63 #define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT 6
64 #define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK 0x40
65 #define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT 7
66 #define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK 0x80
68 /* MME_CMDQ_GLBL_ERR_CFG */
69 #define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0
70 #define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1
71 #define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1
72 #define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2
73 #define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2
74 #define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4
75 #define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3
76 #define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8
77 #define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
78 #define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10
79 #define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5
80 #define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20
81 #define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6
82 #define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40
83 #define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7
84 #define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80
85 #define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8
86 #define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100
87 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9
88 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
89 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10
90 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400
91 #define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11
92 #define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
94 /* MME_CMDQ_GLBL_ERR_ADDR_LO */
95 #define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
96 #define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
98 /* MME_CMDQ_GLBL_ERR_ADDR_HI */
99 #define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
100 #define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
102 /* MME_CMDQ_GLBL_ERR_WDATA */
103 #define MME_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT 0
104 #define MME_CMDQ_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
106 /* MME_CMDQ_GLBL_SECURE_PROPS */
107 #define MME_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT 0
108 #define MME_CMDQ_GLBL_SECURE_PROPS_ASID_MASK 0x3FF
109 #define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT 10
110 #define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400
112 /* MME_CMDQ_GLBL_NON_SECURE_PROPS */
113 #define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0
114 #define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF
115 #define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10
116 #define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400
118 /* MME_CMDQ_GLBL_STS0 */
119 #define MME_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT 0
120 #define MME_CMDQ_GLBL_STS0_PQF_IDLE_MASK 0x1
121 #define MME_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT 1
122 #define MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK 0x2
123 #define MME_CMDQ_GLBL_STS0_CP_IDLE_SHIFT 2
124 #define MME_CMDQ_GLBL_STS0_CP_IDLE_MASK 0x4
125 #define MME_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT 3
126 #define MME_CMDQ_GLBL_STS0_DMA_IDLE_MASK 0x8
127 #define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT 4
128 #define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK 0x10
129 #define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT 5
130 #define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK 0x20
131 #define MME_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT 6
132 #define MME_CMDQ_GLBL_STS0_CP_IS_STOP_MASK 0x40
133 #define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT 7
134 #define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK 0x80
136 /* MME_CMDQ_GLBL_STS1 */
137 #define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT 0
138 #define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK 0x1
139 #define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT 1
140 #define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK 0x2
141 #define MME_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT 2
142 #define MME_CMDQ_GLBL_STS1_CP_RD_ERR_MASK 0x4
143 #define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3
144 #define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8
145 #define MME_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT 4
146 #define MME_CMDQ_GLBL_STS1_CP_STOP_OP_MASK 0x10
147 #define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5
148 #define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20
149 #define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT 8
150 #define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK 0x100
151 #define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT 9
152 #define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200
153 #define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10
154 #define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400
155 #define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11
156 #define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
158 /* MME_CMDQ_CQ_CFG0 */
159 #define MME_CMDQ_CQ_CFG0_RESERVED_SHIFT 0
160 #define MME_CMDQ_CQ_CFG0_RESERVED_MASK 0x1
162 /* MME_CMDQ_CQ_CFG1 */
163 #define MME_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT 0
164 #define MME_CMDQ_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF
165 #define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
166 #define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
168 /* MME_CMDQ_CQ_ARUSER */
169 #define MME_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT 0
170 #define MME_CMDQ_CQ_ARUSER_NOSNOOP_MASK 0x1
171 #define MME_CMDQ_CQ_ARUSER_WORD_SHIFT 1
172 #define MME_CMDQ_CQ_ARUSER_WORD_MASK 0x2
174 /* MME_CMDQ_CQ_PTR_LO */
175 #define MME_CMDQ_CQ_PTR_LO_VAL_SHIFT 0
176 #define MME_CMDQ_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF
178 /* MME_CMDQ_CQ_PTR_HI */
179 #define MME_CMDQ_CQ_PTR_HI_VAL_SHIFT 0
180 #define MME_CMDQ_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF
182 /* MME_CMDQ_CQ_TSIZE */
183 #define MME_CMDQ_CQ_TSIZE_VAL_SHIFT 0
184 #define MME_CMDQ_CQ_TSIZE_VAL_MASK 0xFFFFFFFF
186 /* MME_CMDQ_CQ_CTL */
187 #define MME_CMDQ_CQ_CTL_RPT_SHIFT 0
188 #define MME_CMDQ_CQ_CTL_RPT_MASK 0xFFFF
189 #define MME_CMDQ_CQ_CTL_CTL_SHIFT 16
190 #define MME_CMDQ_CQ_CTL_CTL_MASK 0xFFFF0000
192 /* MME_CMDQ_CQ_PTR_LO_STS */
193 #define MME_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT 0
194 #define MME_CMDQ_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
196 /* MME_CMDQ_CQ_PTR_HI_STS */
197 #define MME_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT 0
198 #define MME_CMDQ_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
200 /* MME_CMDQ_CQ_TSIZE_STS */
201 #define MME_CMDQ_CQ_TSIZE_STS_VAL_SHIFT 0
202 #define MME_CMDQ_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
204 /* MME_CMDQ_CQ_CTL_STS */
205 #define MME_CMDQ_CQ_CTL_STS_RPT_SHIFT 0
206 #define MME_CMDQ_CQ_CTL_STS_RPT_MASK 0xFFFF
207 #define MME_CMDQ_CQ_CTL_STS_CTL_SHIFT 16
208 #define MME_CMDQ_CQ_CTL_STS_CTL_MASK 0xFFFF0000
210 /* MME_CMDQ_CQ_STS0 */
211 #define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0
212 #define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF
213 #define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT 16
214 #define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000
216 /* MME_CMDQ_CQ_STS1 */
217 #define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0
218 #define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF
219 #define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30
220 #define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000
221 #define MME_CMDQ_CQ_STS1_CQ_BUSY_SHIFT 31
222 #define MME_CMDQ_CQ_STS1_CQ_BUSY_MASK 0x80000000
224 /* MME_CMDQ_CQ_RD_RATE_LIM_EN */
225 #define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0
226 #define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1
228 /* MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */
229 #define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0
230 #define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF
232 /* MME_CMDQ_CQ_RD_RATE_LIM_SAT */
233 #define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0
234 #define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF
236 /* MME_CMDQ_CQ_RD_RATE_LIM_TOUT */
237 #define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0
238 #define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF
240 /* MME_CMDQ_CQ_IFIFO_CNT */
241 #define MME_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT 0
242 #define MME_CMDQ_CQ_IFIFO_CNT_VAL_MASK 0x3
244 /* MME_CMDQ_CP_MSG_BASE0_ADDR_LO */
245 #define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
246 #define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
248 /* MME_CMDQ_CP_MSG_BASE0_ADDR_HI */
249 #define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
250 #define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
252 /* MME_CMDQ_CP_MSG_BASE1_ADDR_LO */
253 #define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
254 #define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
256 /* MME_CMDQ_CP_MSG_BASE1_ADDR_HI */
257 #define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
258 #define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
260 /* MME_CMDQ_CP_MSG_BASE2_ADDR_LO */
261 #define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
262 #define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
264 /* MME_CMDQ_CP_MSG_BASE2_ADDR_HI */
265 #define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
266 #define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
268 /* MME_CMDQ_CP_MSG_BASE3_ADDR_LO */
269 #define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
270 #define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
272 /* MME_CMDQ_CP_MSG_BASE3_ADDR_HI */
273 #define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
274 #define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
276 /* MME_CMDQ_CP_LDMA_TSIZE_OFFSET */
277 #define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
278 #define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF
280 /* MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */
281 #define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
282 #define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
284 /* MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */
285 #define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0
286 #define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF
288 /* MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */
289 #define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
290 #define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
292 /* MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */
293 #define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0
294 #define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF
296 /* MME_CMDQ_CP_LDMA_COMMIT_OFFSET */
297 #define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0
298 #define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF
300 /* MME_CMDQ_CP_FENCE0_RDATA */
301 #define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
302 #define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
304 /* MME_CMDQ_CP_FENCE1_RDATA */
305 #define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
306 #define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
308 /* MME_CMDQ_CP_FENCE2_RDATA */
309 #define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
310 #define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
312 /* MME_CMDQ_CP_FENCE3_RDATA */
313 #define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
314 #define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
316 /* MME_CMDQ_CP_FENCE0_CNT */
317 #define MME_CMDQ_CP_FENCE0_CNT_VAL_SHIFT 0
318 #define MME_CMDQ_CP_FENCE0_CNT_VAL_MASK 0xFF
320 /* MME_CMDQ_CP_FENCE1_CNT */
321 #define MME_CMDQ_CP_FENCE1_CNT_VAL_SHIFT 0
322 #define MME_CMDQ_CP_FENCE1_CNT_VAL_MASK 0xFF
324 /* MME_CMDQ_CP_FENCE2_CNT */
325 #define MME_CMDQ_CP_FENCE2_CNT_VAL_SHIFT 0
326 #define MME_CMDQ_CP_FENCE2_CNT_VAL_MASK 0xFF
328 /* MME_CMDQ_CP_FENCE3_CNT */
329 #define MME_CMDQ_CP_FENCE3_CNT_VAL_SHIFT 0
330 #define MME_CMDQ_CP_FENCE3_CNT_VAL_MASK 0xFF
332 /* MME_CMDQ_CP_STS */
333 #define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
334 #define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF
335 #define MME_CMDQ_CP_STS_ERDY_SHIFT 16
336 #define MME_CMDQ_CP_STS_ERDY_MASK 0x10000
337 #define MME_CMDQ_CP_STS_RRDY_SHIFT 17
338 #define MME_CMDQ_CP_STS_RRDY_MASK 0x20000
339 #define MME_CMDQ_CP_STS_MRDY_SHIFT 18
340 #define MME_CMDQ_CP_STS_MRDY_MASK 0x40000
341 #define MME_CMDQ_CP_STS_SW_STOP_SHIFT 19
342 #define MME_CMDQ_CP_STS_SW_STOP_MASK 0x80000
343 #define MME_CMDQ_CP_STS_FENCE_ID_SHIFT 20
344 #define MME_CMDQ_CP_STS_FENCE_ID_MASK 0x300000
345 #define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT 22
346 #define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000
348 /* MME_CMDQ_CP_CURRENT_INST_LO */
349 #define MME_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT 0
350 #define MME_CMDQ_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
352 /* MME_CMDQ_CP_CURRENT_INST_HI */
353 #define MME_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT 0
354 #define MME_CMDQ_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
356 /* MME_CMDQ_CP_BARRIER_CFG */
357 #define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT 0
358 #define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
360 /* MME_CMDQ_CP_DBG_0 */
361 #define MME_CMDQ_CP_DBG_0_VAL_SHIFT 0
362 #define MME_CMDQ_CP_DBG_0_VAL_MASK 0xFF
364 /* MME_CMDQ_CQ_BUF_ADDR */
365 #define MME_CMDQ_CQ_BUF_ADDR_VAL_SHIFT 0
366 #define MME_CMDQ_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF
368 /* MME_CMDQ_CQ_BUF_RDATA */
369 #define MME_CMDQ_CQ_BUF_RDATA_VAL_SHIFT 0
370 #define MME_CMDQ_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF
372 #endif /* ASIC_REG_MME_CMDQ_MASKS_H_ */