drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12
  13 #ifndef ASIC_REG_TPC0_NRTR_MASKS_H_
  14 #define ASIC_REG_TPC0_NRTR_MASKS_H_
  15
  16 /*
  17  *****************************************
  18  *   TPC0_NRTR (Prototype: IF_NRTR)
  19  *****************************************
  20  */
  21
  22 /* TPC0_NRTR_HBW_MAX_CRED */
  23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT                           0
  24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK                            0x3F
  25 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT                           8
  26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK                            0x3F00
  27 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT                           16
  28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK                            0x3F0000
  29 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT                           24
  30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK                            0x3F000000
  31
  32 /* TPC0_NRTR_LBW_MAX_CRED */
  33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT                           0
  34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK                            0x3F
  35 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT                           8
  36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK                            0x3F00
  37 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT                           16
  38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK                            0x3F0000
  39 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT                           24
  40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK                            0x3F000000
  41
  42 /* TPC0_NRTR_DBG_E_ARB */
  43 #define TPC0_NRTR_DBG_E_ARB_W_SHIFT                                  0
  44 #define TPC0_NRTR_DBG_E_ARB_W_MASK                                   0x7
  45 #define TPC0_NRTR_DBG_E_ARB_S_SHIFT                                  8
  46 #define TPC0_NRTR_DBG_E_ARB_S_MASK                                   0x700
  47 #define TPC0_NRTR_DBG_E_ARB_N_SHIFT                                  16
  48 #define TPC0_NRTR_DBG_E_ARB_N_MASK                                   0x70000
  49 #define TPC0_NRTR_DBG_E_ARB_L_SHIFT                                  24
  50 #define TPC0_NRTR_DBG_E_ARB_L_MASK                                   0x7000000
  51
  52 /* TPC0_NRTR_DBG_W_ARB */
  53 #define TPC0_NRTR_DBG_W_ARB_E_SHIFT                                  0
  54 #define TPC0_NRTR_DBG_W_ARB_E_MASK                                   0x7
  55 #define TPC0_NRTR_DBG_W_ARB_S_SHIFT                                  8
  56 #define TPC0_NRTR_DBG_W_ARB_S_MASK                                   0x700
  57 #define TPC0_NRTR_DBG_W_ARB_N_SHIFT                                  16
  58 #define TPC0_NRTR_DBG_W_ARB_N_MASK                                   0x70000
  59 #define TPC0_NRTR_DBG_W_ARB_L_SHIFT                                  24
  60 #define TPC0_NRTR_DBG_W_ARB_L_MASK                                   0x7000000
  61
  62 /* TPC0_NRTR_DBG_N_ARB */
  63 #define TPC0_NRTR_DBG_N_ARB_W_SHIFT                                  0
  64 #define TPC0_NRTR_DBG_N_ARB_W_MASK                                   0x7
  65 #define TPC0_NRTR_DBG_N_ARB_E_SHIFT                                  8
  66 #define TPC0_NRTR_DBG_N_ARB_E_MASK                                   0x700
  67 #define TPC0_NRTR_DBG_N_ARB_S_SHIFT                                  16
  68 #define TPC0_NRTR_DBG_N_ARB_S_MASK                                   0x70000
  69 #define TPC0_NRTR_DBG_N_ARB_L_SHIFT                                  24
  70 #define TPC0_NRTR_DBG_N_ARB_L_MASK                                   0x7000000
  71
  72 /* TPC0_NRTR_DBG_S_ARB */
  73 #define TPC0_NRTR_DBG_S_ARB_W_SHIFT                                  0
  74 #define TPC0_NRTR_DBG_S_ARB_W_MASK                                   0x7
  75 #define TPC0_NRTR_DBG_S_ARB_E_SHIFT                                  8
  76 #define TPC0_NRTR_DBG_S_ARB_E_MASK                                   0x700
  77 #define TPC0_NRTR_DBG_S_ARB_N_SHIFT                                  16
  78 #define TPC0_NRTR_DBG_S_ARB_N_MASK                                   0x70000
  79 #define TPC0_NRTR_DBG_S_ARB_L_SHIFT                                  24
  80 #define TPC0_NRTR_DBG_S_ARB_L_MASK                                   0x7000000
  81
  82 /* TPC0_NRTR_DBG_L_ARB */
  83 #define TPC0_NRTR_DBG_L_ARB_W_SHIFT                                  0
  84 #define TPC0_NRTR_DBG_L_ARB_W_MASK                                   0x7
  85 #define TPC0_NRTR_DBG_L_ARB_E_SHIFT                                  8
  86 #define TPC0_NRTR_DBG_L_ARB_E_MASK                                   0x700
  87 #define TPC0_NRTR_DBG_L_ARB_S_SHIFT                                  16
  88 #define TPC0_NRTR_DBG_L_ARB_S_MASK                                   0x70000
  89 #define TPC0_NRTR_DBG_L_ARB_N_SHIFT                                  24
  90 #define TPC0_NRTR_DBG_L_ARB_N_MASK                                   0x7000000
  91
  92 /* TPC0_NRTR_DBG_E_ARB_MAX */
  93 #define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT                         0
  94 #define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK                          0x3F
  95
  96 /* TPC0_NRTR_DBG_W_ARB_MAX */
  97 #define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT                         0
  98 #define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK                          0x3F
  99
 100 /* TPC0_NRTR_DBG_N_ARB_MAX */
 101 #define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT                         0
 102 #define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK                          0x3F
 103
 104 /* TPC0_NRTR_DBG_S_ARB_MAX */
 105 #define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT                         0
 106 #define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_MASK                          0x3F
 107
 108 /* TPC0_NRTR_DBG_L_ARB_MAX */
 109 #define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT                         0
 110 #define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_MASK                          0x3F
 111
 112 /* TPC0_NRTR_SPLIT_COEF */
 113 #define TPC0_NRTR_SPLIT_COEF_VAL_SHIFT                               0
 114 #define TPC0_NRTR_SPLIT_COEF_VAL_MASK                                0xFFFF
 115
 116 /* TPC0_NRTR_SPLIT_CFG */
 117 #define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT                    0
 118 #define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK                     0x1
 119 #define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT                 1
 120 #define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK                  0x2
 121 #define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT                       2
 122 #define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK                        0xC
 123 #define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT                     4
 124 #define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK                      0x10
 125 #define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT                     5
 126 #define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK                      0x20
 127 #define TPC0_NRTR_SPLIT_CFG_B2B_OPT_SHIFT                            6
 128 #define TPC0_NRTR_SPLIT_CFG_B2B_OPT_MASK                             0x1C0
 129
 130 /* TPC0_NRTR_SPLIT_RD_SAT */
 131 #define TPC0_NRTR_SPLIT_RD_SAT_VAL_SHIFT                             0
 132 #define TPC0_NRTR_SPLIT_RD_SAT_VAL_MASK                              0xFFFF
 133
 134 /* TPC0_NRTR_SPLIT_RD_RST_TOKEN */
 135 #define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT                       0
 136 #define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK                        0xFFFF
 137
 138 /* TPC0_NRTR_SPLIT_RD_TIMEOUT */
 139 #define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT                         0
 140 #define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK                          0xFFFFFFFF
 141
 142 /* TPC0_NRTR_SPLIT_WR_SAT */
 143 #define TPC0_NRTR_SPLIT_WR_SAT_VAL_SHIFT                             0
 144 #define TPC0_NRTR_SPLIT_WR_SAT_VAL_MASK                              0xFFFF
 145
 146 /* TPC0_NRTR_WPLIT_WR_TST_TOLEN */
 147 #define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT                       0
 148 #define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK                        0xFFFF
 149
 150 /* TPC0_NRTR_SPLIT_WR_TIMEOUT */
 151 #define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT                         0
 152 #define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK                          0xFFFFFFFF
 153
 154 /* TPC0_NRTR_HBW_RANGE_HIT */
 155 #define TPC0_NRTR_HBW_RANGE_HIT_IND_SHIFT                            0
 156 #define TPC0_NRTR_HBW_RANGE_HIT_IND_MASK                             0xFF
 157
 158 /* TPC0_NRTR_HBW_RANGE_MASK_L */
 159 #define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT                         0
 160 #define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_MASK                          0xFFFFFFFF
 161
 162 /* TPC0_NRTR_HBW_RANGE_MASK_H */
 163 #define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT                         0
 164 #define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_MASK                          0x3FFFF
 165
 166 /* TPC0_NRTR_HBW_RANGE_BASE_L */
 167 #define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT                         0
 168 #define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_MASK                          0xFFFFFFFF
 169
 170 /* TPC0_NRTR_HBW_RANGE_BASE_H */
 171 #define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT                         0
 172 #define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_MASK                          0x3FFFF
 173
 174 /* TPC0_NRTR_LBW_RANGE_HIT */
 175 #define TPC0_NRTR_LBW_RANGE_HIT_IND_SHIFT                            0
 176 #define TPC0_NRTR_LBW_RANGE_HIT_IND_MASK                             0xFFFF
 177
 178 /* TPC0_NRTR_LBW_RANGE_MASK */
 179 #define TPC0_NRTR_LBW_RANGE_MASK_VAL_SHIFT                           0
 180 #define TPC0_NRTR_LBW_RANGE_MASK_VAL_MASK                            0x3FFFFFF
 181
 182 /* TPC0_NRTR_LBW_RANGE_BASE */
 183 #define TPC0_NRTR_LBW_RANGE_BASE_VAL_SHIFT                           0
 184 #define TPC0_NRTR_LBW_RANGE_BASE_VAL_MASK                            0x3FFFFFF
 185
 186 /* TPC0_NRTR_RGLTR */
 187 #define TPC0_NRTR_RGLTR_WR_EN_SHIFT                                  0
 188 #define TPC0_NRTR_RGLTR_WR_EN_MASK                                   0x1
 189 #define TPC0_NRTR_RGLTR_RD_EN_SHIFT                                  4
 190 #define TPC0_NRTR_RGLTR_RD_EN_MASK                                   0x10
 191
 192 /* TPC0_NRTR_RGLTR_WR_RESULT */
 193 #define TPC0_NRTR_RGLTR_WR_RESULT_VAL_SHIFT                          0
 194 #define TPC0_NRTR_RGLTR_WR_RESULT_VAL_MASK                           0xFF
 195
 196 /* TPC0_NRTR_RGLTR_RD_RESULT */
 197 #define TPC0_NRTR_RGLTR_RD_RESULT_VAL_SHIFT                          0
 198 #define TPC0_NRTR_RGLTR_RD_RESULT_VAL_MASK                           0xFF
 199
 200 /* TPC0_NRTR_SCRAMB_EN */
 201 #define TPC0_NRTR_SCRAMB_EN_VAL_SHIFT                                0
 202 #define TPC0_NRTR_SCRAMB_EN_VAL_MASK                                 0x1
 203
 204 /* TPC0_NRTR_NON_LIN_SCRAMB */
 205 #define TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT                            0
 206 #define TPC0_NRTR_NON_LIN_SCRAMB_EN_MASK                             0x1
 207
 208 #endif /* ASIC_REG_TPC0_NRTR_MASKS_H_ */