drm/vkms: Add support for ABGR8888 pixel format

[drm/drm-misc.git] / drivers / accel / habanalabs / include / goya / asic_reg / tpc1_cfg_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_TPC1_CFG_REGS_H_
#define ASIC_REG_TPC1_CFG_REGS_H_

/*
 *****************************************
 *   TPC1_CFG (Prototype: TPC)
 *****************************************
 */

#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xE46400

#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xE46404

#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xE46408

#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xE4640C

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xE46410

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xE46414

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET                 0xE46418

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xE4641C

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xE46420

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET                 0xE46424

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xE46428

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xE4642C

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET                 0xE46430

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xE46434

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xE46438

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET                 0xE4643C

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xE46440

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xE46444

#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET                 0xE46448

#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xE4644C

#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xE46450

#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xE46454

#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xE46458

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xE4645C

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xE46460

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET                 0xE46464

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xE46468

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xE4646C

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET                 0xE46470

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xE46474

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xE46478

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET                 0xE4647C

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xE46480

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xE46484

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET                 0xE46488

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xE4648C

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xE46490

#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET                 0xE46494

#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xE46498

#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xE4649C

#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xE464A0

#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xE464A4

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xE464A8

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xE464AC

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET                 0xE464B0

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xE464B4

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xE464B8

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET                 0xE464BC

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xE464C0

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xE464C4

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET                 0xE464C8

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xE464CC

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xE464D0

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET                 0xE464D4

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xE464D8

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xE464DC

#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET                 0xE464E0

#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xE464E4

#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xE464E8

#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xE464EC

#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xE464F0

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xE464F4

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xE464F8

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET                 0xE464FC

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xE46500

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xE46504

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET                 0xE46508

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xE4650C

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xE46510

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET                 0xE46514

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xE46518

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xE4651C

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET                 0xE46520

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xE46524

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xE46528

#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET                 0xE4652C

#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xE46530

#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xE46534

#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xE46538

#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xE4653C

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xE46540

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xE46544

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET                 0xE46548

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xE4654C

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xE46550

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET                 0xE46554

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xE46558

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xE4655C

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET                 0xE46560

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xE46564

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xE46568

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET                 0xE4656C

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xE46570

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xE46574

#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET                 0xE46578

#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xE4657C

#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xE46580

#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xE46584

#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xE46588

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xE4658C

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xE46590

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET                 0xE46594

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xE46598

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xE4659C

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET                 0xE465A0

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xE465A4

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xE465A8

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET                 0xE465AC

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xE465B0

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xE465B4

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET                 0xE465B8

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xE465BC

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xE465C0

#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET                 0xE465C4

#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xE465C8

#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xE465CC

#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xE465D0

#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xE465D4

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xE465D8

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xE465DC

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET                 0xE465E0

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xE465E4

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xE465E8

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET                 0xE465EC

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xE465F0

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xE465F4

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET                 0xE465F8

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xE465FC

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xE46600

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET                 0xE46604

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xE46608

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xE4660C

#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET                 0xE46610

#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xE46614

#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xE46618

#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xE4661C

#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xE46620

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xE46624

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xE46628

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET                 0xE4662C

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xE46630

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xE46634

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET                 0xE46638

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xE4663C

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xE46640

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET                 0xE46644

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xE46648

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xE4664C

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET                 0xE46650

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xE46654

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xE46658

#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET                 0xE4665C

#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xE46660

#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xE46664

#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0                             0xE46668

#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0                             0xE4666C

#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1                             0xE46670

#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1                             0xE46674

#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2                             0xE46678

#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2                             0xE4667C

#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3                             0xE46680

#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3                             0xE46684

#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4                             0xE46688

#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4                             0xE4668C

#define mmTPC1_CFG_KERNEL_SRF_0                                      0xE46690

#define mmTPC1_CFG_KERNEL_SRF_1                                      0xE46694

#define mmTPC1_CFG_KERNEL_SRF_2                                      0xE46698

#define mmTPC1_CFG_KERNEL_SRF_3                                      0xE4669C

#define mmTPC1_CFG_KERNEL_SRF_4                                      0xE466A0

#define mmTPC1_CFG_KERNEL_SRF_5                                      0xE466A4

#define mmTPC1_CFG_KERNEL_SRF_6                                      0xE466A8

#define mmTPC1_CFG_KERNEL_SRF_7                                      0xE466AC

#define mmTPC1_CFG_KERNEL_SRF_8                                      0xE466B0

#define mmTPC1_CFG_KERNEL_SRF_9                                      0xE466B4

#define mmTPC1_CFG_KERNEL_SRF_10                                     0xE466B8

#define mmTPC1_CFG_KERNEL_SRF_11                                     0xE466BC

#define mmTPC1_CFG_KERNEL_SRF_12                                     0xE466C0

#define mmTPC1_CFG_KERNEL_SRF_13                                     0xE466C4

#define mmTPC1_CFG_KERNEL_SRF_14                                     0xE466C8

#define mmTPC1_CFG_KERNEL_SRF_15                                     0xE466CC

#define mmTPC1_CFG_KERNEL_SRF_16                                     0xE466D0

#define mmTPC1_CFG_KERNEL_SRF_17                                     0xE466D4

#define mmTPC1_CFG_KERNEL_SRF_18                                     0xE466D8

#define mmTPC1_CFG_KERNEL_SRF_19                                     0xE466DC

#define mmTPC1_CFG_KERNEL_SRF_20                                     0xE466E0

#define mmTPC1_CFG_KERNEL_SRF_21                                     0xE466E4

#define mmTPC1_CFG_KERNEL_SRF_22                                     0xE466E8

#define mmTPC1_CFG_KERNEL_SRF_23                                     0xE466EC

#define mmTPC1_CFG_KERNEL_SRF_24                                     0xE466F0

#define mmTPC1_CFG_KERNEL_SRF_25                                     0xE466F4

#define mmTPC1_CFG_KERNEL_SRF_26                                     0xE466F8

#define mmTPC1_CFG_KERNEL_SRF_27                                     0xE466FC

#define mmTPC1_CFG_KERNEL_SRF_28                                     0xE46700

#define mmTPC1_CFG_KERNEL_SRF_29                                     0xE46704

#define mmTPC1_CFG_KERNEL_SRF_30                                     0xE46708

#define mmTPC1_CFG_KERNEL_SRF_31                                     0xE4670C

#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG                              0xE46710

#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xE46714

#define mmTPC1_CFG_RESERVED_DESC_END                                 0xE46738

#define mmTPC1_CFG_ROUND_CSR                                         0xE467FC

#define mmTPC1_CFG_TBUF_BASE_ADDR_LOW                                0xE46800

#define mmTPC1_CFG_TBUF_BASE_ADDR_HIGH                               0xE46804

#define mmTPC1_CFG_SEMAPHORE                                         0xE46808

#define mmTPC1_CFG_VFLAGS                                            0xE4680C

#define mmTPC1_CFG_SFLAGS                                            0xE46810

#define mmTPC1_CFG_LFSR_POLYNOM                                      0xE46818

#define mmTPC1_CFG_STATUS                                            0xE4681C

#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH                             0xE46820

#define mmTPC1_CFG_CFG_SUBTRACT_VALUE                                0xE46824

#define mmTPC1_CFG_SM_BASE_ADDRESS_LOW                               0xE46828

#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH                              0xE4682C

#define mmTPC1_CFG_TPC_CMD                                           0xE46830

#define mmTPC1_CFG_TPC_EXECUTE                                       0xE46838

#define mmTPC1_CFG_TPC_STALL                                         0xE4683C

#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW                          0xE46840

#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xE46844

#define mmTPC1_CFG_MSS_CONFIG                                        0xE46854

#define mmTPC1_CFG_TPC_INTR_CAUSE                                    0xE46858

#define mmTPC1_CFG_TPC_INTR_MASK                                     0xE4685C

#define mmTPC1_CFG_TSB_CONFIG                                        0xE46860

#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xE46A00

#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xE46A04

#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE                         0xE46A08

#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xE46A0C

#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xE46A10

#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xE46A14

#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET                     0xE46A18

#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xE46A1C

#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xE46A20

#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET                     0xE46A24

#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xE46A28

#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xE46A2C

#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET                     0xE46A30

#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xE46A34

#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xE46A38

#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET                     0xE46A3C

#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xE46A40

#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xE46A44

#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET                     0xE46A48

#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xE46A4C

#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xE46A50

#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE                         0xE46A54

#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xE46A58

#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xE46A5C

#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xE46A60

#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET                     0xE46A64

#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xE46A68

#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xE46A6C

#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET                     0xE46A70

#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xE46A74

#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xE46A78

#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET                     0xE46A7C

#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xE46A80

#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xE46A84

#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET                     0xE46A88

#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xE46A8C

#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xE46A90

#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET                     0xE46A94

#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xE46A98

#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xE46A9C

#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE                         0xE46AA0

#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xE46AA4

#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xE46AA8

#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xE46AAC

#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET                     0xE46AB0

#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xE46AB4

#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xE46AB8

#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET                     0xE46ABC

#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xE46AC0

#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xE46AC4

#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET                     0xE46AC8

#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xE46ACC

#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xE46AD0

#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET                     0xE46AD4

#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xE46AD8

#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xE46ADC

#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET                     0xE46AE0

#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xE46AE4

#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xE46AE8

#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE                         0xE46AEC

#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xE46AF0

#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xE46AF4

#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xE46AF8

#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET                     0xE46AFC

#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xE46B00

#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xE46B04

#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET                     0xE46B08

#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xE46B0C

#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xE46B10

#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET                     0xE46B14

#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xE46B18

#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xE46B1C

#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET                     0xE46B20

#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xE46B24

#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xE46B28

#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET                     0xE46B2C

#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xE46B30

#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xE46B34

#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE                         0xE46B38

#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xE46B3C

#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xE46B40

#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xE46B44

#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET                     0xE46B48

#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xE46B4C

#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xE46B50

#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET                     0xE46B54

#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xE46B58

#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xE46B5C

#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET                     0xE46B60

#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xE46B64

#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xE46B68

#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET                     0xE46B6C

#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xE46B70

#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xE46B74

#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET                     0xE46B78

#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xE46B7C

#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xE46B80

#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE                         0xE46B84

#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xE46B88

#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xE46B8C

#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xE46B90

#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET                     0xE46B94

#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xE46B98

#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xE46B9C

#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET                     0xE46BA0

#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xE46BA4

#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xE46BA8

#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET                     0xE46BAC

#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xE46BB0

#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xE46BB4

#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET                     0xE46BB8

#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xE46BBC

#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xE46BC0

#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET                     0xE46BC4

#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xE46BC8

#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xE46BCC

#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE                         0xE46BD0

#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xE46BD4

#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xE46BD8

#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xE46BDC

#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET                     0xE46BE0

#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xE46BE4

#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xE46BE8

#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET                     0xE46BEC

#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xE46BF0

#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xE46BF4

#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET                     0xE46BF8

#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xE46BFC

#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xE46C00

#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET                     0xE46C04

#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xE46C08

#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xE46C0C

#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET                     0xE46C10

#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xE46C14

#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xE46C18

#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE                         0xE46C1C

#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xE46C20

#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xE46C24

#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xE46C28

#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET                     0xE46C2C

#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xE46C30

#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xE46C34

#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET                     0xE46C38

#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xE46C3C

#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xE46C40

#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET                     0xE46C44

#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xE46C48

#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xE46C4C

#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET                     0xE46C50

#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xE46C54

#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xE46C58

#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET                     0xE46C5C

#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xE46C60

#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xE46C64

#define mmTPC1_CFG_QM_TID_BASE_DIM_0                                 0xE46C68

#define mmTPC1_CFG_QM_TID_SIZE_DIM_0                                 0xE46C6C

#define mmTPC1_CFG_QM_TID_BASE_DIM_1                                 0xE46C70

#define mmTPC1_CFG_QM_TID_SIZE_DIM_1                                 0xE46C74

#define mmTPC1_CFG_QM_TID_BASE_DIM_2                                 0xE46C78

#define mmTPC1_CFG_QM_TID_SIZE_DIM_2                                 0xE46C7C

#define mmTPC1_CFG_QM_TID_BASE_DIM_3                                 0xE46C80

#define mmTPC1_CFG_QM_TID_SIZE_DIM_3                                 0xE46C84

#define mmTPC1_CFG_QM_TID_BASE_DIM_4                                 0xE46C88

#define mmTPC1_CFG_QM_TID_SIZE_DIM_4                                 0xE46C8C

#define mmTPC1_CFG_QM_SRF_0                                          0xE46C90

#define mmTPC1_CFG_QM_SRF_1                                          0xE46C94

#define mmTPC1_CFG_QM_SRF_2                                          0xE46C98

#define mmTPC1_CFG_QM_SRF_3                                          0xE46C9C

#define mmTPC1_CFG_QM_SRF_4                                          0xE46CA0

#define mmTPC1_CFG_QM_SRF_5                                          0xE46CA4

#define mmTPC1_CFG_QM_SRF_6                                          0xE46CA8

#define mmTPC1_CFG_QM_SRF_7                                          0xE46CAC

#define mmTPC1_CFG_QM_SRF_8                                          0xE46CB0

#define mmTPC1_CFG_QM_SRF_9                                          0xE46CB4

#define mmTPC1_CFG_QM_SRF_10                                         0xE46CB8

#define mmTPC1_CFG_QM_SRF_11                                         0xE46CBC

#define mmTPC1_CFG_QM_SRF_12                                         0xE46CC0

#define mmTPC1_CFG_QM_SRF_13                                         0xE46CC4

#define mmTPC1_CFG_QM_SRF_14                                         0xE46CC8

#define mmTPC1_CFG_QM_SRF_15                                         0xE46CCC

#define mmTPC1_CFG_QM_SRF_16                                         0xE46CD0

#define mmTPC1_CFG_QM_SRF_17                                         0xE46CD4

#define mmTPC1_CFG_QM_SRF_18                                         0xE46CD8

#define mmTPC1_CFG_QM_SRF_19                                         0xE46CDC

#define mmTPC1_CFG_QM_SRF_20                                         0xE46CE0

#define mmTPC1_CFG_QM_SRF_21                                         0xE46CE4

#define mmTPC1_CFG_QM_SRF_22                                         0xE46CE8

#define mmTPC1_CFG_QM_SRF_23                                         0xE46CEC

#define mmTPC1_CFG_QM_SRF_24                                         0xE46CF0

#define mmTPC1_CFG_QM_SRF_25                                         0xE46CF4

#define mmTPC1_CFG_QM_SRF_26                                         0xE46CF8

#define mmTPC1_CFG_QM_SRF_27                                         0xE46CFC

#define mmTPC1_CFG_QM_SRF_28                                         0xE46D00

#define mmTPC1_CFG_QM_SRF_29                                         0xE46D04

#define mmTPC1_CFG_QM_SRF_30                                         0xE46D08

#define mmTPC1_CFG_QM_SRF_31                                         0xE46D0C

#define mmTPC1_CFG_QM_KERNEL_CONFIG                                  0xE46D10

#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE                            0xE46D14

#define mmTPC1_CFG_ARUSER                                            0xE46D18

#define mmTPC1_CFG_AWUSER                                            0xE46D1C

#define mmTPC1_CFG_FUNC_MBIST_CNTRL                                  0xE46E00

#define mmTPC1_CFG_FUNC_MBIST_PAT                                    0xE46E04

#define mmTPC1_CFG_FUNC_MBIST_MEM_0                                  0xE46E08

#define mmTPC1_CFG_FUNC_MBIST_MEM_1                                  0xE46E0C

#define mmTPC1_CFG_FUNC_MBIST_MEM_2                                  0xE46E10

#define mmTPC1_CFG_FUNC_MBIST_MEM_3                                  0xE46E14

#define mmTPC1_CFG_FUNC_MBIST_MEM_4                                  0xE46E18

#define mmTPC1_CFG_FUNC_MBIST_MEM_5                                  0xE46E1C

#define mmTPC1_CFG_FUNC_MBIST_MEM_6                                  0xE46E20

#define mmTPC1_CFG_FUNC_MBIST_MEM_7                                  0xE46E24

#define mmTPC1_CFG_FUNC_MBIST_MEM_8                                  0xE46E28

#define mmTPC1_CFG_FUNC_MBIST_MEM_9                                  0xE46E2C

#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */