drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v2_0.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2019 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef INCLUDE_MMU_V2_0_H_
   9 #define INCLUDE_MMU_V2_0_H_
  10
  11 #define HOP0_MASK_4K                    0xFE00000000000000ull
  12 #define HOP1_MASK_4K                    0x01FF000000000000ull
  13 #define HOP2_MASK_4K                    0x0000FF8000000000ull
  14 #define HOP3_MASK_4K                    0x0000007FC0000000ull
  15 #define HOP4_MASK_4K                    0x000000003FE00000ull
  16 #define HOP5_MASK_4K                    0x00000000001FF000ull
  17
  18 #define HOP0_MASK_64K                   0xFF00000000000000ull
  19 #define HOP1_MASK_64K                   0x00FF000000000000ull
  20 #define HOP2_MASK_64K                   0x0000FF0000000000ull
  21 #define HOP3_MASK_64K                   0x000000FF00000000ull
  22 #define HOP4_MASK_64K                   0x00000000FF000000ull
  23 #define HOP5_MASK_64K                   0x0000000000FF0000ull
  24
  25 #define HOP0_SHIFT_4K                   57
  26 #define HOP1_SHIFT_4K                   48
  27 #define HOP2_SHIFT_4K                   39
  28 #define HOP3_SHIFT_4K                   30
  29 #define HOP4_SHIFT_4K                   21
  30 #define HOP5_SHIFT_4K                   12
  31
  32 #define HOP0_SHIFT_64K                  56
  33 #define HOP1_SHIFT_64K                  48
  34 #define HOP2_SHIFT_64K                  40
  35 #define HOP3_SHIFT_64K                  32
  36 #define HOP4_SHIFT_64K                  24
  37 #define HOP5_SHIFT_64K                  16
  38
  39 #define DHOP0_MASK                      HOP0_MASK_4K
  40 #define DHOP1_MASK                      HOP1_MASK_4K
  41 #define DHOP2_MASK                      HOP2_MASK_4K
  42 #define DHOP3_MASK                      HOP3_MASK_4K
  43 #define DHOP4_MASK                      0x000003C000000ull
  44
  45 #define DHOP0_SHIFT                     HOP0_SHIFT_4K
  46 #define DHOP1_SHIFT                     HOP1_SHIFT_4K
  47 #define DHOP2_SHIFT                     HOP2_SHIFT_4K
  48 #define DHOP3_SHIFT                     HOP3_SHIFT_4K
  49 #define DHOP4_SHIFT                     26
  50
  51 #endif /* INCLUDE_MMU_V2_0_H_ */