drivers/accel/ivpu/ivpu_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2020-2024 Intel Corporation
   4  */
   5
   6 #ifndef __IVPU_DRV_H__
   7 #define __IVPU_DRV_H__
   8
   9 #include <drm/drm_device.h>
  10 #include <drm/drm_drv.h>
  11 #include <drm/drm_managed.h>
  12 #include <drm/drm_mm.h>
  13 #include <drm/drm_print.h>
  14
  15 #include <linux/pci.h>
  16 #include <linux/xarray.h>
  17 #include <uapi/drm/ivpu_accel.h>
  18
  19 #include "ivpu_mmu_context.h"
  20 #include "ivpu_ipc.h"
  21
  22 #define DRIVER_NAME "intel_vpu"
  23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
  24
  25 #define PCI_DEVICE_ID_MTL       0x7d1d
  26 #define PCI_DEVICE_ID_ARL       0xad1d
  27 #define PCI_DEVICE_ID_LNL       0x643e
  28 #define PCI_DEVICE_ID_PTL_P     0xb03e
  29
  30 #define IVPU_HW_IP_37XX 37
  31 #define IVPU_HW_IP_40XX 40
  32 #define IVPU_HW_IP_50XX 50
  33 #define IVPU_HW_IP_60XX 60
  34
  35 #define IVPU_HW_IP_REV_LNL_B0 4
  36
  37 #define IVPU_HW_BTRS_MTL 1
  38 #define IVPU_HW_BTRS_LNL 2
  39
  40 #define IVPU_GLOBAL_CONTEXT_MMU_SSID   0
  41 /* SSID 1 is used by the VPU to represent reserved context */
  42 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
  43 #define IVPU_USER_CONTEXT_MIN_SSID     2
  44 #define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 63)
  45
  46 #define IVPU_MIN_DB 1
  47 #define IVPU_MAX_DB 255
  48
  49 #define IVPU_JOB_ID_JOB_MASK            GENMASK(7, 0)
  50 #define IVPU_JOB_ID_CONTEXT_MASK        GENMASK(31, 8)
  51
  52 #define IVPU_NUM_PRIORITIES    4
  53 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
  54
  55 #define IVPU_CMDQ_MIN_ID 1
  56 #define IVPU_CMDQ_MAX_ID 255
  57
  58 #define IVPU_PLATFORM_SILICON 0
  59 #define IVPU_PLATFORM_SIMICS  2
  60 #define IVPU_PLATFORM_FPGA    3
  61 #define IVPU_PLATFORM_HSLE    4
  62 #define IVPU_PLATFORM_INVALID 8
  63
  64 #define IVPU_SCHED_MODE_AUTO -1
  65
  66 #define IVPU_DBG_REG     BIT(0)
  67 #define IVPU_DBG_IRQ     BIT(1)
  68 #define IVPU_DBG_MMU     BIT(2)
  69 #define IVPU_DBG_FILE    BIT(3)
  70 #define IVPU_DBG_MISC    BIT(4)
  71 #define IVPU_DBG_FW_BOOT BIT(5)
  72 #define IVPU_DBG_PM      BIT(6)
  73 #define IVPU_DBG_IPC     BIT(7)
  74 #define IVPU_DBG_BO      BIT(8)
  75 #define IVPU_DBG_JOB     BIT(9)
  76 #define IVPU_DBG_JSM     BIT(10)
  77 #define IVPU_DBG_KREF    BIT(11)
  78 #define IVPU_DBG_RPM     BIT(12)
  79 #define IVPU_DBG_MMU_MAP BIT(13)
  80
  81 #define ivpu_err(vdev, fmt, ...) \
  82         drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  83
  84 #define ivpu_err_ratelimited(vdev, fmt, ...) \
  85         drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  86
  87 #define ivpu_warn(vdev, fmt, ...) \
  88         drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  89
  90 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
  91         drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  92
  93 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
  94
  95 #define ivpu_dbg(vdev, type, fmt, args...) do {                                \
  96         if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask))                         \
  97                 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args);          \
  98 } while (0)
  99
 100 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
 101
 102 #define IVPU_PRINT_WA(wa_name) do {                                     \
 103         if (IVPU_WA(wa_name))                                           \
 104                 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n");       \
 105 } while (0)
 106
 107 struct ivpu_wa_table {
 108         bool punit_disabled;
 109         bool clear_runtime_mem;
 110         bool interrupt_clear_with_0;
 111         bool disable_clock_relinquish;
 112         bool disable_d0i3_msg;
 113         bool wp0_during_power_up;
 114 };
 115
 116 struct ivpu_hw_info;
 117 struct ivpu_mmu_info;
 118 struct ivpu_fw_info;
 119 struct ivpu_ipc_info;
 120 struct ivpu_pm_info;
 121
 122 struct ivpu_device {
 123         struct drm_device drm;
 124         void __iomem *regb;
 125         void __iomem *regv;
 126         u32 platform;
 127         u32 irq;
 128
 129         struct ivpu_wa_table wa;
 130         struct ivpu_hw_info *hw;
 131         struct ivpu_mmu_info *mmu;
 132         struct ivpu_fw_info *fw;
 133         struct ivpu_ipc_info *ipc;
 134         struct ivpu_pm_info *pm;
 135
 136         struct ivpu_mmu_context gctx;
 137         struct ivpu_mmu_context rctx;
 138         struct mutex context_list_lock; /* Protects user context addition/removal */
 139         struct xarray context_xa;
 140         struct xa_limit context_xa_limit;
 141
 142         struct xarray db_xa;
 143         struct xa_limit db_limit;
 144         u32 db_next;
 145
 146         struct work_struct irq_ipc_work;
 147         struct work_struct irq_dct_work;
 148         struct work_struct context_abort_work;
 149
 150         struct mutex bo_list_lock; /* Protects bo_list */
 151         struct list_head bo_list;
 152
 153         struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
 154         struct xarray submitted_jobs_xa;
 155         struct ivpu_ipc_consumer job_done_consumer;
 156
 157         atomic64_t unique_id_counter;
 158
 159         ktime_t busy_start_ts;
 160         ktime_t busy_time;
 161
 162         struct {
 163                 int boot;
 164                 int jsm;
 165                 int tdr;
 166                 int autosuspend;
 167                 int d0i3_entry_msg;
 168                 int state_dump_msg;
 169         } timeout;
 170 };
 171
 172 /*
 173  * file_priv has its own refcount (ref) that allows user space to close the fd
 174  * without blocking even if VPU is still processing some jobs.
 175  */
 176 struct ivpu_file_priv {
 177         struct kref ref;
 178         struct ivpu_device *vdev;
 179         struct mutex lock; /* Protects cmdq */
 180         struct xarray cmdq_xa;
 181         struct ivpu_mmu_context ctx;
 182         struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
 183         struct list_head ms_instance_list;
 184         struct ivpu_bo *ms_info_bo;
 185         struct xa_limit job_limit;
 186         u32 job_id_next;
 187         struct xa_limit cmdq_limit;
 188         u32 cmdq_id_next;
 189         bool has_mmu_faults;
 190         bool bound;
 191         bool aborted;
 192 };
 193
 194 extern int ivpu_dbg_mask;
 195 extern u8 ivpu_pll_min_ratio;
 196 extern u8 ivpu_pll_max_ratio;
 197 extern int ivpu_sched_mode;
 198 extern bool ivpu_disable_mmu_cont_pages;
 199 extern bool ivpu_force_snoop;
 200
 201 #define IVPU_TEST_MODE_FW_TEST            BIT(0)
 202 #define IVPU_TEST_MODE_NULL_HW            BIT(1)
 203 #define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
 204 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
 205 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
 206 #define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
 207 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
 208 #define IVPU_TEST_MODE_TURBO              BIT(9)
 209 extern int ivpu_test_mode;
 210
 211 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
 212 void ivpu_file_priv_put(struct ivpu_file_priv **link);
 213
 214 int ivpu_boot(struct ivpu_device *vdev);
 215 int ivpu_shutdown(struct ivpu_device *vdev);
 216 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
 217 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
 218
 219 static inline u8 ivpu_revision(struct ivpu_device *vdev)
 220 {
 221         return to_pci_dev(vdev->drm.dev)->revision;
 222 }
 223
 224 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
 225 {
 226         return to_pci_dev(vdev->drm.dev)->device;
 227 }
 228
 229 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
 230 {
 231         switch (ivpu_device_id(vdev)) {
 232         case PCI_DEVICE_ID_MTL:
 233         case PCI_DEVICE_ID_ARL:
 234                 return IVPU_HW_IP_37XX;
 235         case PCI_DEVICE_ID_LNL:
 236                 return IVPU_HW_IP_40XX;
 237         case PCI_DEVICE_ID_PTL_P:
 238                 return IVPU_HW_IP_50XX;
 239         default:
 240                 dump_stack();
 241                 ivpu_err(vdev, "Unknown NPU IP generation\n");
 242                 return 0;
 243         }
 244 }
 245
 246 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
 247 {
 248         switch (ivpu_device_id(vdev)) {
 249         case PCI_DEVICE_ID_MTL:
 250         case PCI_DEVICE_ID_ARL:
 251                 return IVPU_HW_BTRS_MTL;
 252         case PCI_DEVICE_ID_LNL:
 253         case PCI_DEVICE_ID_PTL_P:
 254                 return IVPU_HW_BTRS_LNL;
 255         default:
 256                 dump_stack();
 257                 ivpu_err(vdev, "Unknown buttress generation\n");
 258                 return 0;
 259         }
 260 }
 261
 262 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
 263 {
 264         return container_of(dev, struct ivpu_device, drm);
 265 }
 266
 267 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
 268 {
 269         struct xa_limit ctx_limit = vdev->context_xa_limit;
 270
 271         return (ctx_limit.max - ctx_limit.min + 1);
 272 }
 273
 274 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
 275 {
 276         WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
 277         return vdev->platform;
 278 }
 279
 280 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
 281 {
 282         return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
 283 }
 284
 285 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
 286 {
 287         return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
 288 }
 289
 290 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
 291 {
 292         return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
 293                ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
 294 }
 295
 296 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
 297 {
 298         return ivpu_force_snoop;
 299 }
 300
 301 #endif /* __IVPU_DRV_H__ */