drivers/accel/ivpu/ivpu_fw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2020-2024 Intel Corporation
   4  */
   5
   6 #include <linux/firmware.h>
   7 #include <linux/highmem.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/pci.h>
  10
  11 #include "vpu_boot_api.h"
  12 #include "ivpu_drv.h"
  13 #include "ivpu_fw.h"
  14 #include "ivpu_fw_log.h"
  15 #include "ivpu_gem.h"
  16 #include "ivpu_hw.h"
  17 #include "ivpu_ipc.h"
  18 #include "ivpu_pm.h"
  19
  20 #define FW_GLOBAL_MEM_START     (2ull * SZ_1G)
  21 #define FW_GLOBAL_MEM_END       (3ull * SZ_1G)
  22 #define FW_SHARED_MEM_SIZE      SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */
  23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */
  24 #define FW_RUNTIME_MAX_SIZE     SZ_512M
  25 #define FW_SHAVE_NN_MAX_SIZE    SZ_2M
  26 #define FW_RUNTIME_MIN_ADDR     (FW_GLOBAL_MEM_START)
  27 #define FW_RUNTIME_MAX_ADDR     (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE)
  28 #define FW_FILE_IMAGE_OFFSET    (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE)
  29
  30 #define WATCHDOG_MSS_REDIRECT   32
  31 #define WATCHDOG_NCE_REDIRECT   33
  32
  33 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31)
  34
  35 /* Check if FW API is compatible with the driver */
  36 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \
  37         ivpu_fw_check_api(vdev, fw_hdr, #name, \
  38                           VPU_##name##_API_VER_INDEX, \
  39                           VPU_##name##_API_VER_MAJOR, \
  40                           VPU_##name##_API_VER_MINOR, min_major)
  41
  42 /* Check if API version is lower that the given version */
  43 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \
  44         ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)
  45
  46 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000
  47
  48 static char *ivpu_firmware;
  49 #if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
  50 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
  51 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");
  52 #endif
  53
  54 static struct {
  55         int gen;
  56         const char *name;
  57 } fw_names[] = {
  58         { IVPU_HW_IP_37XX, "vpu_37xx.bin" },
  59         { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
  60         { IVPU_HW_IP_40XX, "vpu_40xx.bin" },
  61         { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
  62         { IVPU_HW_IP_50XX, "vpu_50xx.bin" },
  63         { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" },
  64 };
  65
  66 /* Production fw_names from the table above */
  67 MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin");
  68 MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin");
  69 MODULE_FIRMWARE("intel/vpu/vpu_50xx_v0.0.bin");
  70
  71 static int ivpu_fw_request(struct ivpu_device *vdev)
  72 {
  73         int ret = -ENOENT;
  74         int i;
  75
  76         if (ivpu_firmware) {
  77                 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev);
  78                 if (!ret)
  79                         vdev->fw->name = ivpu_firmware;
  80                 return ret;
  81         }
  82
  83         for (i = 0; i < ARRAY_SIZE(fw_names); i++) {
  84                 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev))
  85                         continue;
  86
  87                 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);
  88                 if (!ret) {
  89                         vdev->fw->name = fw_names[i].name;
  90                         return 0;
  91                 }
  92         }
  93
  94         ivpu_err(vdev, "Failed to request firmware: %d\n", ret);
  95         return ret;
  96 }
  97
  98 static int
  99 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
 100                   const char *str, int index, u16 expected_major, u16 expected_minor,
 101                   u16 min_major)
 102 {
 103         u16 major = (u16)(fw_hdr->api_version[index] >> 16);
 104         u16 minor = (u16)(fw_hdr->api_version[index]);
 105
 106         if (major < min_major) {
 107                 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n",
 108                          str, major, minor, min_major);
 109                 return -EINVAL;
 110         }
 111         if (major != expected_major) {
 112                 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n",
 113                           str, major, minor, expected_major, expected_minor);
 114         }
 115         ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n",
 116                  str, major, minor, expected_major, expected_minor);
 117
 118         return 0;
 119 }
 120
 121 static bool
 122 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
 123                          const char *str, int index, u16 major, u16 minor)
 124 {
 125         u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16);
 126         u16 fw_minor = (u16)(fw_hdr->api_version[index]);
 127
 128         if (fw_major < major || (fw_major == major && fw_minor < minor))
 129                 return true;
 130
 131         return false;
 132 }
 133
 134 static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range_size)
 135 {
 136         if (addr < range_start || addr + size > range_start + range_size)
 137                 return false;
 138
 139         return true;
 140 }
 141
 142 static u32
 143 ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
 144 {
 145         if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO)
 146                 return ivpu_sched_mode;
 147
 148         if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, JSM, 3, 24))
 149                 return VPU_SCHEDULING_MODE_OS;
 150
 151         switch (ivpu_device_id(vdev)) {
 152         case PCI_DEVICE_ID_MTL:
 153         case PCI_DEVICE_ID_ARL:
 154         case PCI_DEVICE_ID_LNL:
 155         case PCI_DEVICE_ID_PTL_P:
 156                 return VPU_SCHEDULING_MODE_HW;
 157         default:
 158                 return VPU_SCHEDULING_MODE_OS;
 159         }
 160 }
 161
 162 static int ivpu_fw_parse(struct ivpu_device *vdev)
 163 {
 164         struct ivpu_fw_info *fw = vdev->fw;
 165         const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data;
 166         u64 runtime_addr, image_load_addr, runtime_size, image_size;
 167
 168         if (fw->file->size <= FW_FILE_IMAGE_OFFSET) {
 169                 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size);
 170                 return -EINVAL;
 171         }
 172
 173         if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) {
 174                 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version);
 175                 return -EINVAL;
 176         }
 177
 178         runtime_addr = fw_hdr->boot_params_load_address;
 179         runtime_size = fw_hdr->runtime_size;
 180         image_load_addr = fw_hdr->image_load_address;
 181         image_size = fw_hdr->image_size;
 182
 183         if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) {
 184                 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr);
 185                 return -EINVAL;
 186         }
 187
 188         if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) {
 189                 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size);
 190                 return -EINVAL;
 191         }
 192
 193         if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) {
 194                 ivpu_err(vdev, "Invalid image size: %llu\n", image_size);
 195                 return -EINVAL;
 196         }
 197
 198         if (image_load_addr < runtime_addr ||
 199             image_load_addr + image_size > runtime_addr + runtime_size) {
 200                 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n",
 201                          image_load_addr, image_size);
 202                 return -EINVAL;
 203         }
 204
 205         if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) {
 206                 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size);
 207                 return -EINVAL;
 208         }
 209
 210         if (fw_hdr->entry_point < image_load_addr ||
 211             fw_hdr->entry_point >= image_load_addr + image_size) {
 212                 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point);
 213                 return -EINVAL;
 214         }
 215         ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
 216                  fw_hdr->header_version, fw_hdr->image_format);
 217
 218         if (!scnprintf(fw->version, sizeof(fw->version), "%s", fw->file->data + VPU_FW_HEADER_SIZE))
 219                 ivpu_warn(vdev, "Missing firmware version\n");
 220
 221         ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version);
 222
 223         if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3))
 224                 return -EINVAL;
 225         if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3))
 226                 return -EINVAL;
 227
 228         fw->runtime_addr = runtime_addr;
 229         fw->runtime_size = runtime_size;
 230         fw->image_load_offset = image_load_addr - runtime_addr;
 231         fw->image_size = image_size;
 232         fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size);
 233
 234         fw->cold_boot_entry_point = fw_hdr->entry_point;
 235         fw->entry_point = fw->cold_boot_entry_point;
 236
 237         fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL);
 238         fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING;
 239         fw->trace_hw_component_mask = -1;
 240
 241         fw->dvfs_mode = 0;
 242
 243         fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr);
 244         fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
 245         fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
 246         ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS");
 247
 248         if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address,
 249                                                                  fw_hdr->ro_section_size,
 250                                                                  fw_hdr->image_load_address,
 251                                                                  fw_hdr->image_size)) {
 252                 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n",
 253                          fw_hdr->ro_section_start_address, fw_hdr->ro_section_size);
 254                 return -EINVAL;
 255         }
 256
 257         fw->read_only_addr = fw_hdr->ro_section_start_address;
 258         fw->read_only_size = fw_hdr->ro_section_size;
 259
 260         ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n",
 261                  fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size);
 262         ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n",
 263                  fw->runtime_addr, image_load_addr, fw->entry_point);
 264         ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n",
 265                  fw->read_only_addr, fw->read_only_size);
 266
 267         return 0;
 268 }
 269
 270 static void ivpu_fw_release(struct ivpu_device *vdev)
 271 {
 272         release_firmware(vdev->fw->file);
 273 }
 274
 275 /* Initialize workarounds that depend on FW version */
 276 static void
 277 ivpu_fw_init_wa(struct ivpu_device *vdev)
 278 {
 279         const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
 280
 281         if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
 282             (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
 283                 vdev->wa.disable_d0i3_msg = true;
 284
 285         /* Force enable the feature for testing purposes */
 286         if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
 287                 vdev->wa.disable_d0i3_msg = false;
 288
 289         IVPU_PRINT_WA(disable_d0i3_msg);
 290 }
 291
 292 static int ivpu_fw_update_global_range(struct ivpu_device *vdev)
 293 {
 294         struct ivpu_fw_info *fw = vdev->fw;
 295         u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT);
 296         u64 size = FW_SHARED_MEM_SIZE;
 297
 298         if (start + size > FW_GLOBAL_MEM_END) {
 299                 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size);
 300                 return -EINVAL;
 301         }
 302
 303         ivpu_hw_range_init(&vdev->hw->ranges.global, start, size);
 304         return 0;
 305 }
 306
 307 static int ivpu_fw_mem_init(struct ivpu_device *vdev)
 308 {
 309         struct ivpu_fw_info *fw = vdev->fw;
 310         struct ivpu_addr_range fw_range;
 311         int log_verb_size;
 312         int ret;
 313
 314         ret = ivpu_fw_update_global_range(vdev);
 315         if (ret)
 316                 return ret;
 317
 318         fw_range.start = fw->runtime_addr;
 319         fw_range.end = fw->runtime_addr + fw->runtime_size;
 320         fw->mem = ivpu_bo_create(vdev, &vdev->gctx, &fw_range, fw->runtime_size,
 321                                  DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
 322         if (!fw->mem) {
 323                 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n");
 324                 return -ENOMEM;
 325         }
 326
 327         ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr,
 328                                             fw->read_only_size);
 329         if (ret) {
 330                 ivpu_err(vdev, "Failed to set firmware image read-only\n");
 331                 goto err_free_fw_mem;
 332         }
 333
 334         fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE,
 335                                                  DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
 336         if (!fw->mem_log_crit) {
 337                 ivpu_err(vdev, "Failed to create critical log buffer\n");
 338                 ret = -ENOMEM;
 339                 goto err_free_fw_mem;
 340         }
 341
 342         if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO)
 343                 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE;
 344         else
 345                 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE;
 346
 347         fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size,
 348                                                  DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
 349         if (!fw->mem_log_verb) {
 350                 ivpu_err(vdev, "Failed to create verbose log buffer\n");
 351                 ret = -ENOMEM;
 352                 goto err_free_log_crit;
 353         }
 354
 355         if (fw->shave_nn_size) {
 356                 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave,
 357                                                   fw->shave_nn_size, DRM_IVPU_BO_WC);
 358                 if (!fw->mem_shave_nn) {
 359                         ivpu_err(vdev, "Failed to create shavenn buffer\n");
 360                         ret = -ENOMEM;
 361                         goto err_free_log_verb;
 362                 }
 363         }
 364
 365         return 0;
 366
 367 err_free_log_verb:
 368         ivpu_bo_free(fw->mem_log_verb);
 369 err_free_log_crit:
 370         ivpu_bo_free(fw->mem_log_crit);
 371 err_free_fw_mem:
 372         ivpu_bo_free(fw->mem);
 373         return ret;
 374 }
 375
 376 static void ivpu_fw_mem_fini(struct ivpu_device *vdev)
 377 {
 378         struct ivpu_fw_info *fw = vdev->fw;
 379
 380         if (fw->mem_shave_nn) {
 381                 ivpu_bo_free(fw->mem_shave_nn);
 382                 fw->mem_shave_nn = NULL;
 383         }
 384
 385         ivpu_bo_free(fw->mem_log_verb);
 386         ivpu_bo_free(fw->mem_log_crit);
 387         ivpu_bo_free(fw->mem);
 388
 389         fw->mem_log_verb = NULL;
 390         fw->mem_log_crit = NULL;
 391         fw->mem = NULL;
 392 }
 393
 394 int ivpu_fw_init(struct ivpu_device *vdev)
 395 {
 396         int ret;
 397
 398         ret = ivpu_fw_request(vdev);
 399         if (ret)
 400                 return ret;
 401
 402         ret = ivpu_fw_parse(vdev);
 403         if (ret)
 404                 goto err_fw_release;
 405
 406         ivpu_fw_init_wa(vdev);
 407
 408         ret = ivpu_fw_mem_init(vdev);
 409         if (ret)
 410                 goto err_fw_release;
 411
 412         ivpu_fw_load(vdev);
 413
 414         return 0;
 415
 416 err_fw_release:
 417         ivpu_fw_release(vdev);
 418         return ret;
 419 }
 420
 421 void ivpu_fw_fini(struct ivpu_device *vdev)
 422 {
 423         ivpu_fw_mem_fini(vdev);
 424         ivpu_fw_release(vdev);
 425 }
 426
 427 void ivpu_fw_load(struct ivpu_device *vdev)
 428 {
 429         struct ivpu_fw_info *fw = vdev->fw;
 430         u64 image_end_offset = fw->image_load_offset + fw->image_size;
 431
 432         memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset);
 433         memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset,
 434                fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size);
 435
 436         if (IVPU_WA(clear_runtime_mem)) {
 437                 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset;
 438                 u64 size = ivpu_bo_size(fw->mem) - image_end_offset;
 439
 440                 memset(start, 0, size);
 441         }
 442
 443         wmb(); /* Flush WC buffers after writing fw->mem */
 444 }
 445
 446 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
 447 {
 448         ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n",
 449                  boot_params->magic);
 450         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n",
 451                  boot_params->vpu_id);
 452         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n",
 453                  boot_params->vpu_count);
 454         ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n",
 455                  boot_params->frequency);
 456         ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n",
 457                  boot_params->perf_clk_frequency);
 458
 459         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n",
 460                  boot_params->ipc_header_area_start);
 461         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n",
 462                  boot_params->ipc_header_area_size);
 463         ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n",
 464                  boot_params->shared_region_base);
 465         ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n",
 466                  boot_params->shared_region_size);
 467         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n",
 468                  boot_params->ipc_payload_area_start);
 469         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n",
 470                  boot_params->ipc_payload_area_size);
 471         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n",
 472                  boot_params->global_aliased_pio_base);
 473         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n",
 474                  boot_params->global_aliased_pio_size);
 475
 476         ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n",
 477                  boot_params->autoconfig);
 478
 479         ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n",
 480                  boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use);
 481         ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n",
 482                  boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg);
 483
 484         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n",
 485                  boot_params->global_memory_allocator_base);
 486         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n",
 487                  boot_params->global_memory_allocator_size);
 488
 489         ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n",
 490                  boot_params->shave_nn_fw_base);
 491
 492         ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n",
 493                  boot_params->watchdog_irq_mss);
 494         ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n",
 495                  boot_params->watchdog_irq_nce);
 496         ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n",
 497                  boot_params->host_to_vpu_irq);
 498         ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n",
 499                  boot_params->job_done_irq);
 500
 501         ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n",
 502                  boot_params->host_version_id);
 503         ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n",
 504                  boot_params->si_stepping);
 505         ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n",
 506                  boot_params->device_id);
 507         ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n",
 508                  boot_params->feature_exclusion);
 509         ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n",
 510                  boot_params->sku);
 511         ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n",
 512                  boot_params->min_freq_pll_ratio);
 513         ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n",
 514                  boot_params->pn_freq_pll_ratio);
 515         ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n",
 516                  boot_params->max_freq_pll_ratio);
 517         ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n",
 518                  boot_params->default_trace_level);
 519         ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n",
 520                  boot_params->tracing_buff_message_format_mask);
 521         ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n",
 522                  boot_params->trace_destination_mask);
 523         ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n",
 524                  boot_params->trace_hw_component_mask);
 525         ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n",
 526                  boot_params->boot_type);
 527         ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n",
 528                  boot_params->punit_telemetry_sram_base);
 529         ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n",
 530                  boot_params->punit_telemetry_sram_size);
 531         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
 532                  boot_params->vpu_telemetry_enable);
 533         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n",
 534                  boot_params->vpu_scheduling_mode);
 535         ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
 536                  boot_params->dvfs_mode);
 537         ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
 538                  boot_params->d0i3_delayed_entry);
 539         ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
 540                  boot_params->d0i3_residency_time_us);
 541         ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
 542                  boot_params->d0i3_entry_vpu_ts);
 543         ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
 544                  boot_params->system_time_us);
 545 }
 546
 547 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
 548 {
 549         struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx;
 550
 551         /* In case of warm boot only update variable params */
 552         if (!ivpu_fw_is_cold_boot(vdev)) {
 553                 boot_params->d0i3_residency_time_us =
 554                         ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts);
 555                 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts;
 556                 boot_params->system_time_us = ktime_to_us(ktime_get_real());
 557
 558                 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
 559                          boot_params->d0i3_residency_time_us);
 560                 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
 561                          boot_params->d0i3_entry_vpu_ts);
 562                 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
 563                          boot_params->system_time_us);
 564
 565                 boot_params->save_restore_ret_address = 0;
 566                 vdev->pm->is_warmboot = true;
 567                 wmb(); /* Flush WC buffers after writing save_restore_ret_address */
 568                 return;
 569         }
 570
 571         vdev->pm->is_warmboot = false;
 572
 573         boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
 574         boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
 575         boot_params->frequency = ivpu_hw_pll_freq_get(vdev);
 576
 577         /*
 578          * This param is a debug firmware feature.  It switches default clock
 579          * to higher resolution one for fine-grained and more accurate firmware
 580          * task profiling.
 581          */
 582         boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev);
 583
 584         /*
 585          * Uncached region of VPU address space, covers IPC buffers, job queues
 586          * and log buffers, programmable to L2$ Uncached by VPU MTRR
 587          */
 588         boot_params->shared_region_base = vdev->hw->ranges.global.start;
 589         boot_params->shared_region_size = vdev->hw->ranges.global.end -
 590                                           vdev->hw->ranges.global.start;
 591
 592         boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
 593         boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
 594
 595         boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2;
 596         boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
 597
 598         if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
 599                 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
 600                 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
 601         }
 602
 603         /* Allow configuration for L2C_PAGE_TABLE with boot param value */
 604         boot_params->autoconfig = 1;
 605
 606         /* Enable L2 cache for first 2GB of high memory */
 607         boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
 608         boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
 609                 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
 610
 611         if (vdev->fw->mem_shave_nn)
 612                 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
 613
 614         boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT;
 615         boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT;
 616         boot_params->si_stepping = ivpu_revision(vdev);
 617         boot_params->device_id = ivpu_device_id(vdev);
 618         boot_params->feature_exclusion = vdev->hw->tile_fuse;
 619         boot_params->sku = vdev->hw->sku;
 620
 621         boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio;
 622         boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio;
 623         boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio;
 624
 625         boot_params->default_trace_level = vdev->fw->trace_level;
 626         boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING);
 627         boot_params->trace_destination_mask = vdev->fw->trace_destination_mask;
 628         boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask;
 629         boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr;
 630         boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit);
 631         boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;
 632         boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);
 633
 634         boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
 635         boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
 636         boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
 637         boot_params->vpu_scheduling_mode = vdev->fw->sched_mode;
 638         if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
 639                 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
 640         boot_params->dvfs_mode = vdev->fw->dvfs_mode;
 641         if (!IVPU_WA(disable_d0i3_msg))
 642                 boot_params->d0i3_delayed_entry = 1;
 643         boot_params->d0i3_residency_time_us = 0;
 644         boot_params->d0i3_entry_vpu_ts = 0;
 645
 646         boot_params->system_time_us = ktime_to_us(ktime_get_real());
 647         wmb(); /* Flush WC buffers after writing bootparams */
 648
 649         ivpu_fw_boot_params_print(vdev, boot_params);
 650 }