1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom Corporation
7 * DESCRIPTION: The Broadcom iProc RNG200 Driver
10 #include <linux/hw_random.h>
11 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
20 #define RNG_CTRL_OFFSET 0x00
21 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
22 #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
24 #define RNG_SOFT_RESET_OFFSET 0x04
25 #define RNG_SOFT_RESET 0x00000001
27 #define RBG_SOFT_RESET_OFFSET 0x08
28 #define RBG_SOFT_RESET 0x00000001
30 #define RNG_INT_STATUS_OFFSET 0x18
31 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
32 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
33 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
34 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
36 #define RNG_FIFO_DATA_OFFSET 0x20
38 #define RNG_FIFO_COUNT_OFFSET 0x24
39 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
41 struct iproc_rng200_dev
{
46 #define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
48 static void iproc_rng200_enable_set(void __iomem
*rng_base
, bool enable
)
52 val
= ioread32(rng_base
+ RNG_CTRL_OFFSET
);
53 val
&= ~RNG_CTRL_RNG_RBGEN_MASK
;
56 val
|= RNG_CTRL_RNG_RBGEN_ENABLE
;
58 iowrite32(val
, rng_base
+ RNG_CTRL_OFFSET
);
61 static void iproc_rng200_restart(void __iomem
*rng_base
)
65 iproc_rng200_enable_set(rng_base
, false);
67 /* Clear all interrupt status */
68 iowrite32(0xFFFFFFFFUL
, rng_base
+ RNG_INT_STATUS_OFFSET
);
70 /* Reset RNG and RBG */
71 val
= ioread32(rng_base
+ RBG_SOFT_RESET_OFFSET
);
72 val
|= RBG_SOFT_RESET
;
73 iowrite32(val
, rng_base
+ RBG_SOFT_RESET_OFFSET
);
75 val
= ioread32(rng_base
+ RNG_SOFT_RESET_OFFSET
);
76 val
|= RNG_SOFT_RESET
;
77 iowrite32(val
, rng_base
+ RNG_SOFT_RESET_OFFSET
);
79 val
= ioread32(rng_base
+ RNG_SOFT_RESET_OFFSET
);
80 val
&= ~RNG_SOFT_RESET
;
81 iowrite32(val
, rng_base
+ RNG_SOFT_RESET_OFFSET
);
83 val
= ioread32(rng_base
+ RBG_SOFT_RESET_OFFSET
);
84 val
&= ~RBG_SOFT_RESET
;
85 iowrite32(val
, rng_base
+ RBG_SOFT_RESET_OFFSET
);
87 iproc_rng200_enable_set(rng_base
, true);
90 static int iproc_rng200_read(struct hwrng
*rng
, void *buf
, size_t max
,
93 struct iproc_rng200_dev
*priv
= to_rng_priv(rng
);
94 uint32_t num_remaining
= max
;
97 #define MAX_RESETS_PER_READ 1
98 uint32_t num_resets
= 0;
100 #define MAX_IDLE_TIME (1 * HZ)
101 unsigned long idle_endtime
= jiffies
+ MAX_IDLE_TIME
;
103 while ((num_remaining
> 0) && time_before(jiffies
, idle_endtime
)) {
105 /* Is RNG sane? If not, reset it. */
106 status
= ioread32(priv
->base
+ RNG_INT_STATUS_OFFSET
);
107 if ((status
& (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK
|
108 RNG_INT_STATUS_NIST_FAIL_IRQ_MASK
)) != 0) {
110 if (num_resets
>= MAX_RESETS_PER_READ
)
111 return max
- num_remaining
;
113 iproc_rng200_restart(priv
->base
);
117 /* Are there any random numbers available? */
118 if ((ioread32(priv
->base
+ RNG_FIFO_COUNT_OFFSET
) &
119 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK
) > 0) {
121 if (num_remaining
>= sizeof(uint32_t)) {
122 /* Buffer has room to store entire word */
123 *(uint32_t *)buf
= ioread32(priv
->base
+
124 RNG_FIFO_DATA_OFFSET
);
125 buf
+= sizeof(uint32_t);
126 num_remaining
-= sizeof(uint32_t);
128 /* Buffer can only store partial word */
129 uint32_t rnd_number
= ioread32(priv
->base
+
130 RNG_FIFO_DATA_OFFSET
);
131 memcpy(buf
, &rnd_number
, num_remaining
);
132 buf
+= num_remaining
;
136 /* Reset the IDLE timeout */
137 idle_endtime
= jiffies
+ MAX_IDLE_TIME
;
140 /* Cannot wait, return immediately */
141 return max
- num_remaining
;
143 /* Can wait, give others chance to run */
144 usleep_range(min(num_remaining
* 10, 500U), 500);
148 return max
- num_remaining
;
151 static int iproc_rng200_init(struct hwrng
*rng
)
153 struct iproc_rng200_dev
*priv
= to_rng_priv(rng
);
155 iproc_rng200_enable_set(priv
->base
, true);
160 static void iproc_rng200_cleanup(struct hwrng
*rng
)
162 struct iproc_rng200_dev
*priv
= to_rng_priv(rng
);
164 iproc_rng200_enable_set(priv
->base
, false);
167 static int iproc_rng200_probe(struct platform_device
*pdev
)
169 struct iproc_rng200_dev
*priv
;
170 struct device
*dev
= &pdev
->dev
;
173 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
178 priv
->base
= devm_platform_ioremap_resource(pdev
, 0);
179 if (IS_ERR(priv
->base
)) {
180 dev_err(dev
, "failed to remap rng regs\n");
181 return PTR_ERR(priv
->base
);
184 dev_set_drvdata(dev
, priv
);
186 priv
->rng
.name
= "iproc-rng200";
187 priv
->rng
.read
= iproc_rng200_read
;
188 priv
->rng
.init
= iproc_rng200_init
;
189 priv
->rng
.cleanup
= iproc_rng200_cleanup
;
191 /* Register driver */
192 ret
= devm_hwrng_register(dev
, &priv
->rng
);
194 dev_err(dev
, "hwrng registration failed\n");
198 dev_info(dev
, "hwrng registered\n");
203 static int __maybe_unused
iproc_rng200_suspend(struct device
*dev
)
205 struct iproc_rng200_dev
*priv
= dev_get_drvdata(dev
);
207 iproc_rng200_cleanup(&priv
->rng
);
212 static int __maybe_unused
iproc_rng200_resume(struct device
*dev
)
214 struct iproc_rng200_dev
*priv
= dev_get_drvdata(dev
);
216 iproc_rng200_init(&priv
->rng
);
221 static const struct dev_pm_ops iproc_rng200_pm_ops
= {
222 SET_SYSTEM_SLEEP_PM_OPS(iproc_rng200_suspend
, iproc_rng200_resume
)
225 static const struct of_device_id iproc_rng200_of_match
[] = {
226 { .compatible
= "brcm,bcm2711-rng200", },
227 { .compatible
= "brcm,bcm7211-rng200", },
228 { .compatible
= "brcm,bcm7278-rng200", },
229 { .compatible
= "brcm,iproc-rng200", },
232 MODULE_DEVICE_TABLE(of
, iproc_rng200_of_match
);
234 static struct platform_driver iproc_rng200_driver
= {
236 .name
= "iproc-rng200",
237 .of_match_table
= iproc_rng200_of_match
,
238 .pm
= &iproc_rng200_pm_ops
,
240 .probe
= iproc_rng200_probe
,
242 module_platform_driver(iproc_rng200_driver
);
244 MODULE_AUTHOR("Broadcom");
245 MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
246 MODULE_LICENSE("GPL v2");