drivers/clk/mediatek/clk-mt7622-infracfg.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 MediaTek Inc.
   4  * Copyright (c) 2023 Collabora, Ltd.
   5  *               AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt7622-clk.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11
  12 #include "clk-cpumux.h"
  13 #include "clk-gate.h"
  14 #include "clk-mtk.h"
  15 #include "reset.h"
  16
  17 #define GATE_INFRA(_id, _name, _parent, _shift)                         \
  18         GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  19
  20 static const struct mtk_gate_regs infra_cg_regs = {
  21         .set_ofs = 0x40,
  22         .clr_ofs = 0x44,
  23         .sta_ofs = 0x48,
  24 };
  25
  26 static const char * const infra_mux1_parents[] = {
  27         "clkxtal",
  28         "armpll",
  29         "main_core_en",
  30         "armpll"
  31 };
  32
  33 static const struct mtk_composite cpu_muxes[] = {
  34         MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),
  35 };
  36
  37 static const struct mtk_gate infra_clks[] = {
  38         GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
  39         GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
  40         GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
  41         GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
  42         GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
  43         GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
  44 };
  45
  46 static u16 infrasys_rst_ofs[] = { 0x30 };
  47
  48 static const struct mtk_clk_rst_desc clk_rst_desc = {
  49         .version = MTK_RST_SIMPLE,
  50         .rst_bank_ofs = infrasys_rst_ofs,
  51         .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
  52 };
  53
  54 static const struct of_device_id of_match_clk_mt7622_infracfg[] = {
  55         { .compatible = "mediatek,mt7622-infracfg" },
  56         { /* sentinel */ }
  57 };
  58 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg);
  59
  60 static int clk_mt7622_infracfg_probe(struct platform_device *pdev)
  61 {
  62         struct clk_hw_onecell_data *clk_data;
  63         struct device_node *node = pdev->dev.of_node;
  64         void __iomem *base;
  65         int ret;
  66
  67         base = devm_platform_ioremap_resource(pdev, 0);
  68         if (IS_ERR(base))
  69                 return PTR_ERR(base);
  70
  71         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  72         if (!clk_data)
  73                 return -ENOMEM;
  74
  75         ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
  76         if (ret)
  77                 goto free_clk_data;
  78
  79         ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  80                                      ARRAY_SIZE(infra_clks), clk_data);
  81         if (ret)
  82                 goto free_clk_data;
  83
  84         ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
  85                                         ARRAY_SIZE(cpu_muxes), clk_data);
  86         if (ret)
  87                 goto unregister_gates;
  88
  89         ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  90         if (ret)
  91                 goto unregister_cpumuxes;
  92
  93         return 0;
  94
  95 unregister_cpumuxes:
  96         mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
  97 unregister_gates:
  98         mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
  99 free_clk_data:
 100         mtk_free_clk_data(clk_data);
 101         return ret;
 102 }
 103
 104 static void clk_mt7622_infracfg_remove(struct platform_device *pdev)
 105 {
 106         struct device_node *node = pdev->dev.of_node;
 107         struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
 108
 109         of_clk_del_provider(node);
 110         mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
 111         mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
 112         mtk_free_clk_data(clk_data);
 113 }
 114
 115 static struct platform_driver clk_mt7622_infracfg_drv = {
 116         .driver = {
 117                 .name = "clk-mt7622-infracfg",
 118                 .of_match_table = of_match_clk_mt7622_infracfg,
 119         },
 120         .probe = clk_mt7622_infracfg_probe,
 121         .remove = clk_mt7622_infracfg_remove,
 122 };
 123 module_platform_driver(clk_mt7622_infracfg_drv);
 124
 125 MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
 126 MODULE_LICENSE("GPL");