drivers/clk/mediatek/clk-mt8167-mm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Copyright (c) 2020 BayLibre, SAS
   5  * Author: James Liao <jamesjj.liao@mediatek.com>
   6  *         Fabien Parent <fparent@baylibre.com>
   7  */
   8
   9 #include <linux/clk-provider.h>
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/platform_device.h>
  12
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15
  16 #include <dt-bindings/clock/mt8167-clk.h>
  17
  18 static const struct mtk_gate_regs mm0_cg_regs = {
  19         .set_ofs = 0x104,
  20         .clr_ofs = 0x108,
  21         .sta_ofs = 0x100,
  22 };
  23
  24 static const struct mtk_gate_regs mm1_cg_regs = {
  25         .set_ofs = 0x114,
  26         .clr_ofs = 0x118,
  27         .sta_ofs = 0x110,
  28 };
  29
  30 #define GATE_MM0(_id, _name, _parent, _shift)   \
  31         GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  32
  33 #define GATE_MM1(_id, _name, _parent, _shift)   \
  34         GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  35
  36 static const struct mtk_gate mm_clks[] = {
  37         /* MM0 */
  38         GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
  39         GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
  40         GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
  41         GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
  42         GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
  43         GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
  44         GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
  45         GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
  46         GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
  47         GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
  48         GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
  49         GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
  50         GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
  51         GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
  52         GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
  53         GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
  54         GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
  55         GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
  56         GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
  57         GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
  58         /* MM1 */
  59         GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
  60         GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
  61         GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
  62         GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
  63         GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
  64         GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
  65         GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
  66         GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
  67         GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
  68         GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
  69         GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
  70         GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
  71         GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
  72         GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
  73 };
  74
  75 static const struct mtk_clk_desc mm_desc = {
  76         .clks = mm_clks,
  77         .num_clks = ARRAY_SIZE(mm_clks),
  78 };
  79
  80 static const struct platform_device_id clk_mt8167_mm_id_table[] = {
  81         { .name = "clk-mt8167-mm", .driver_data = (kernel_ulong_t)&mm_desc },
  82         { /* sentinel */ }
  83 };
  84 MODULE_DEVICE_TABLE(platform, clk_mt8167_mm_id_table);
  85
  86 static struct platform_driver clk_mt8167_mm_drv = {
  87         .probe = mtk_clk_pdev_probe,
  88         .remove = mtk_clk_pdev_remove,
  89         .driver = {
  90                 .name = "clk-mt8167-mm",
  91         },
  92         .id_table = clk_mt8167_mm_id_table,
  93 };
  94 module_platform_driver(clk_mt8167_mm_drv);
  95
  96 MODULE_DESCRIPTION("MediaTek MT8167 MultiMedia clocks driver");
  97 MODULE_LICENSE("GPL");