drivers/clk/mediatek/clk-mt8188-vdo1.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Garmin Chang <garmin.chang@mediatek.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/platform_device.h>
  10
  11 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
  12
  13 #include "clk-gate.h"
  14 #include "clk-mtk.h"
  15
  16 static const struct mtk_gate_regs vdo1_0_cg_regs = {
  17         .set_ofs = 0x104,
  18         .clr_ofs = 0x108,
  19         .sta_ofs = 0x100,
  20 };
  21
  22 static const struct mtk_gate_regs vdo1_1_cg_regs = {
  23         .set_ofs = 0x114,
  24         .clr_ofs = 0x118,
  25         .sta_ofs = 0x110,
  26 };
  27
  28 static const struct mtk_gate_regs vdo1_2_cg_regs = {
  29         .set_ofs = 0x124,
  30         .clr_ofs = 0x128,
  31         .sta_ofs = 0x120,
  32 };
  33
  34 static const struct mtk_gate_regs vdo1_3_cg_regs = {
  35         .set_ofs = 0x134,
  36         .clr_ofs = 0x138,
  37         .sta_ofs = 0x130,
  38 };
  39
  40 static const struct mtk_gate_regs vdo1_4_cg_regs = {
  41         .set_ofs = 0x144,
  42         .clr_ofs = 0x148,
  43         .sta_ofs = 0x140,
  44 };
  45
  46 #define GATE_VDO1_0(_id, _name, _parent, _shift)                        \
  47         GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  48
  49 #define GATE_VDO1_1(_id, _name, _parent, _shift)                        \
  50         GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  51
  52 #define GATE_VDO1_2(_id, _name, _parent, _shift)                        \
  53         GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  54
  55 #define GATE_VDO1_3(_id, _name, _parent, _shift)                        \
  56         GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  57
  58 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags)          \
  59         GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift,    \
  60                        &mtk_clk_gate_ops_setclr, _flags)
  61
  62 #define GATE_VDO1_4(_id, _name, _parent, _shift)                        \
  63         GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  64
  65 static const struct mtk_gate vdo1_clks[] = {
  66         /* VDO1_0 */
  67         GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
  68         GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
  69         GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
  70         GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
  71         GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, "vdo1_fake_eng1", "top_vpp", 4),
  72         GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
  73         GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
  74         GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
  75         GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
  76         GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
  77         GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
  78         GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
  79         /* VDO1_1 */
  80         GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 0),
  81         GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 1),
  82         GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 2),
  83         GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 3),
  84         GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 4),
  85         GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 5),
  86         GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 6),
  87         GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 7),
  88         GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 8),
  89         GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, "vdo1_dp_intf0_mmck", "top_vpp", 9),
  90         GATE_VDO1_1(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm_ck", "top_vpp", 10),
  91         GATE_VDO1_1(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm_ck", "top_vpp", 11),
  92         GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 13),
  93         GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 14),
  94         GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 15),
  95         GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 16),
  96         GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 17),
  97         GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, "vdo1_dsc_vdo1_dl_async", "top_vpp", 18),
  98         GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, "vdo1_merge_vdo1_dl_async", "top_vpp", 19),
  99         GATE_VDO1_1(CLK_VDO1_PADDING0, "vdo1_padding0", "top_vpp", 20),
 100         GATE_VDO1_1(CLK_VDO1_PADDING1, "vdo1_padding1", "top_vpp", 21),
 101         GATE_VDO1_1(CLK_VDO1_PADDING2, "vdo1_padding2", "top_vpp", 22),
 102         GATE_VDO1_1(CLK_VDO1_PADDING3, "vdo1_padding3", "top_vpp", 23),
 103         GATE_VDO1_1(CLK_VDO1_PADDING4, "vdo1_padding4", "top_vpp", 24),
 104         GATE_VDO1_1(CLK_VDO1_PADDING5, "vdo1_padding5", "top_vpp", 25),
 105         GATE_VDO1_1(CLK_VDO1_PADDING6, "vdo1_padding6", "top_vpp", 26),
 106         GATE_VDO1_1(CLK_VDO1_PADDING7, "vdo1_padding7", "top_vpp", 27),
 107         GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, "vdo1_disp_rsz0", "top_vpp", 28),
 108         GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, "vdo1_disp_rsz1", "top_vpp", 29),
 109         GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, "vdo1_disp_rsz2", "top_vpp", 30),
 110         GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, "vdo1_disp_rsz3", "top_vpp", 31),
 111         /* VDO1_2 */
 112         GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
 113         GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
 114         GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
 115         GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
 116         GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
 117         GATE_VDO1_2(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
 118         GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
 119         GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
 120         GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
 121         GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
 122         GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
 123         /* VDO1_3 */
 124         GATE_VDO1_3(CLK_VDO1_DPI0, "vdo1_dpi0_ck", "top_vpp", 0),
 125         GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0_ck", "top_vpp", 1),
 126         GATE_VDO1_3(CLK_VDO1_DPI1, "vdo1_dpi1_ck", "top_vpp", 8),
 127         GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1_ck", "top_vpp", 9),
 128         GATE_VDO1_3_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT),
 129         GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17),
 130         /* VDO1_4 */
 131         GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8),
 132 };
 133
 134 static const struct mtk_clk_desc vdo1_desc = {
 135         .clks = vdo1_clks,
 136         .num_clks = ARRAY_SIZE(vdo1_clks),
 137 };
 138
 139 static const struct platform_device_id clk_mt8188_vdo1_id_table[] = {
 140         { .name = "clk-mt8188-vdo1", .driver_data = (kernel_ulong_t)&vdo1_desc },
 141         { /* sentinel */ }
 142 };
 143 MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo1_id_table);
 144
 145 static struct platform_driver clk_mt8188_vdo1_drv = {
 146         .probe = mtk_clk_pdev_probe,
 147         .remove = mtk_clk_pdev_remove,
 148         .driver = {
 149                 .name = "clk-mt8188-vdo1",
 150         },
 151         .id_table = clk_mt8188_vdo1_id_table,
 152 };
 153 module_platform_driver(clk_mt8188_vdo1_drv);
 154
 155 MODULE_DESCRIPTION("MediaTek MT8188 Video Output 1 clocks driver");
 156 MODULE_LICENSE("GPL");