1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023, Linaro Ltd.
8 #include <linux/clk-provider.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/pm_runtime.h>
17 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
20 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
24 #include "clk-regmap.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-regmap-mux.h"
30 /* Need to match the order of clocks in DT binding */
37 DT_DSI0_PHY_PLL_OUT_BYTECLK
,
38 DT_DSI0_PHY_PLL_OUT_DSICLK
,
39 DT_DSI1_PHY_PLL_OUT_BYTECLK
,
40 DT_DSI1_PHY_PLL_OUT_DSICLK
,
42 DT_DP0_PHY_PLL_LINK_CLK
,
43 DT_DP0_PHY_PLL_VCO_DIV_CLK
,
44 DT_DP1_PHY_PLL_LINK_CLK
,
45 DT_DP1_PHY_PLL_VCO_DIV_CLK
,
46 DT_DP2_PHY_PLL_LINK_CLK
,
47 DT_DP2_PHY_PLL_VCO_DIV_CLK
,
48 DT_DP3_PHY_PLL_LINK_CLK
,
49 DT_DP3_PHY_PLL_VCO_DIV_CLK
,
52 #define DISP_CC_MISC_CMD 0xF000
56 P_DISP_CC_PLL0_OUT_MAIN
,
57 P_DISP_CC_PLL1_OUT_EVEN
,
58 P_DISP_CC_PLL1_OUT_MAIN
,
59 P_DP0_PHY_PLL_LINK_CLK
,
60 P_DP0_PHY_PLL_VCO_DIV_CLK
,
61 P_DP1_PHY_PLL_LINK_CLK
,
62 P_DP1_PHY_PLL_VCO_DIV_CLK
,
63 P_DP2_PHY_PLL_LINK_CLK
,
64 P_DP2_PHY_PLL_VCO_DIV_CLK
,
65 P_DP3_PHY_PLL_LINK_CLK
,
66 P_DP3_PHY_PLL_VCO_DIV_CLK
,
67 P_DSI0_PHY_PLL_OUT_BYTECLK
,
68 P_DSI0_PHY_PLL_OUT_DSICLK
,
69 P_DSI1_PHY_PLL_OUT_BYTECLK
,
70 P_DSI1_PHY_PLL_OUT_DSICLK
,
74 static struct pll_vco lucid_ole_vco
[] = {
75 { 249600000, 2000000000, 0 },
78 static struct alpha_pll_config disp_cc_pll0_config
= {
81 .config_ctl_val
= 0x20485699,
82 .config_ctl_hi_val
= 0x00182261,
83 .config_ctl_hi1_val
= 0x82aa299c,
84 .test_ctl_val
= 0x00000000,
85 .test_ctl_hi_val
= 0x00000003,
86 .test_ctl_hi1_val
= 0x00009000,
87 .test_ctl_hi2_val
= 0x00000034,
88 .user_ctl_val
= 0x00000000,
89 .user_ctl_hi_val
= 0x00000005,
92 static struct clk_alpha_pll disp_cc_pll0
= {
94 .vco_table
= lucid_ole_vco
,
95 .num_vco
= ARRAY_SIZE(lucid_ole_vco
),
96 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_LUCID_OLE
],
98 .hw
.init
= &(const struct clk_init_data
) {
99 .name
= "disp_cc_pll0",
100 .parent_data
= &(const struct clk_parent_data
) {
104 .ops
= &clk_alpha_pll_reset_lucid_ole_ops
,
109 static struct alpha_pll_config disp_cc_pll1_config
= {
112 .config_ctl_val
= 0x20485699,
113 .config_ctl_hi_val
= 0x00182261,
114 .config_ctl_hi1_val
= 0x82aa299c,
115 .test_ctl_val
= 0x00000000,
116 .test_ctl_hi_val
= 0x00000003,
117 .test_ctl_hi1_val
= 0x00009000,
118 .test_ctl_hi2_val
= 0x00000034,
119 .user_ctl_val
= 0x00000000,
120 .user_ctl_hi_val
= 0x00000005,
123 static struct clk_alpha_pll disp_cc_pll1
= {
125 .vco_table
= lucid_ole_vco
,
126 .num_vco
= ARRAY_SIZE(lucid_ole_vco
),
127 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_LUCID_OLE
],
129 .hw
.init
= &(const struct clk_init_data
) {
130 .name
= "disp_cc_pll1",
131 .parent_data
= &(const struct clk_parent_data
) {
135 .ops
= &clk_alpha_pll_reset_lucid_ole_ops
,
140 static const struct parent_map disp_cc_parent_map_0
[] = {
144 static const struct clk_parent_data disp_cc_parent_data_0
[] = {
145 { .index
= DT_BI_TCXO
},
148 static const struct clk_parent_data disp_cc_parent_data_0_ao
[] = {
149 { .index
= DT_BI_TCXO_AO
},
152 static const struct parent_map disp_cc_parent_map_1
[] = {
154 { P_DP3_PHY_PLL_VCO_DIV_CLK
, 3 },
155 { P_DP1_PHY_PLL_VCO_DIV_CLK
, 4 },
156 { P_DP2_PHY_PLL_VCO_DIV_CLK
, 6 },
159 static const struct clk_parent_data disp_cc_parent_data_1
[] = {
160 { .index
= DT_BI_TCXO
},
161 { .index
= DT_DP3_PHY_PLL_VCO_DIV_CLK
},
162 { .index
= DT_DP1_PHY_PLL_VCO_DIV_CLK
},
163 { .index
= DT_DP2_PHY_PLL_VCO_DIV_CLK
},
166 static const struct parent_map disp_cc_parent_map_2
[] = {
168 { P_DSI0_PHY_PLL_OUT_DSICLK
, 1 },
169 { P_DSI0_PHY_PLL_OUT_BYTECLK
, 2 },
170 { P_DSI1_PHY_PLL_OUT_DSICLK
, 3 },
171 { P_DSI1_PHY_PLL_OUT_BYTECLK
, 4 },
174 static const struct clk_parent_data disp_cc_parent_data_2
[] = {
175 { .index
= DT_BI_TCXO
},
176 { .index
= DT_DSI0_PHY_PLL_OUT_DSICLK
},
177 { .index
= DT_DSI0_PHY_PLL_OUT_BYTECLK
},
178 { .index
= DT_DSI1_PHY_PLL_OUT_DSICLK
},
179 { .index
= DT_DSI1_PHY_PLL_OUT_BYTECLK
},
182 static const struct parent_map disp_cc_parent_map_3
[] = {
184 { P_DP1_PHY_PLL_LINK_CLK
, 2 },
185 { P_DP2_PHY_PLL_LINK_CLK
, 3 },
186 { P_DP3_PHY_PLL_LINK_CLK
, 4 },
189 static const struct clk_parent_data disp_cc_parent_data_3
[] = {
190 { .index
= DT_BI_TCXO
},
191 { .index
= DT_DP1_PHY_PLL_LINK_CLK
},
192 { .index
= DT_DP2_PHY_PLL_LINK_CLK
},
193 { .index
= DT_DP3_PHY_PLL_LINK_CLK
},
196 static const struct parent_map disp_cc_parent_map_4
[] = {
198 { P_DP0_PHY_PLL_LINK_CLK
, 1 },
199 { P_DP0_PHY_PLL_VCO_DIV_CLK
, 2 },
200 { P_DP3_PHY_PLL_VCO_DIV_CLK
, 3 },
201 { P_DP1_PHY_PLL_VCO_DIV_CLK
, 4 },
202 { P_DP2_PHY_PLL_VCO_DIV_CLK
, 6 },
205 static const struct clk_parent_data disp_cc_parent_data_4
[] = {
206 { .index
= DT_BI_TCXO
},
207 { .index
= DT_DP0_PHY_PLL_LINK_CLK
},
208 { .index
= DT_DP0_PHY_PLL_VCO_DIV_CLK
},
209 { .index
= DT_DP3_PHY_PLL_VCO_DIV_CLK
},
210 { .index
= DT_DP1_PHY_PLL_VCO_DIV_CLK
},
211 { .index
= DT_DP2_PHY_PLL_VCO_DIV_CLK
},
214 static const struct parent_map disp_cc_parent_map_5
[] = {
216 { P_DSI0_PHY_PLL_OUT_BYTECLK
, 2 },
217 { P_DSI1_PHY_PLL_OUT_BYTECLK
, 4 },
220 static const struct clk_parent_data disp_cc_parent_data_5
[] = {
221 { .index
= DT_BI_TCXO
},
222 { .index
= DT_DSI0_PHY_PLL_OUT_BYTECLK
},
223 { .index
= DT_DSI1_PHY_PLL_OUT_BYTECLK
},
226 static const struct parent_map disp_cc_parent_map_6
[] = {
228 { P_DISP_CC_PLL1_OUT_MAIN
, 4 },
229 { P_DISP_CC_PLL1_OUT_EVEN
, 6 },
232 static const struct clk_parent_data disp_cc_parent_data_6
[] = {
233 { .index
= DT_BI_TCXO
},
234 { .hw
= &disp_cc_pll1
.clkr
.hw
},
235 { .hw
= &disp_cc_pll1
.clkr
.hw
},
238 static const struct parent_map disp_cc_parent_map_7
[] = {
240 { P_DP0_PHY_PLL_LINK_CLK
, 1 },
241 { P_DP1_PHY_PLL_LINK_CLK
, 2 },
242 { P_DP2_PHY_PLL_LINK_CLK
, 3 },
243 { P_DP3_PHY_PLL_LINK_CLK
, 4 },
246 static const struct clk_parent_data disp_cc_parent_data_7
[] = {
247 { .index
= DT_BI_TCXO
},
248 { .index
= DT_DP0_PHY_PLL_LINK_CLK
},
249 { .index
= DT_DP1_PHY_PLL_LINK_CLK
},
250 { .index
= DT_DP2_PHY_PLL_LINK_CLK
},
251 { .index
= DT_DP3_PHY_PLL_LINK_CLK
},
254 static const struct parent_map disp_cc_parent_map_8
[] = {
256 { P_DISP_CC_PLL0_OUT_MAIN
, 1 },
257 { P_DISP_CC_PLL1_OUT_MAIN
, 4 },
258 { P_DISP_CC_PLL1_OUT_EVEN
, 6 },
261 static const struct clk_parent_data disp_cc_parent_data_8
[] = {
262 { .index
= DT_BI_TCXO
},
263 { .hw
= &disp_cc_pll0
.clkr
.hw
},
264 { .hw
= &disp_cc_pll1
.clkr
.hw
},
265 { .hw
= &disp_cc_pll1
.clkr
.hw
},
268 static const struct parent_map disp_cc_parent_map_9
[] = {
272 static const struct clk_parent_data disp_cc_parent_data_9
[] = {
273 { .index
= DT_SLEEP_CLK
},
276 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src
[] = {
277 F(19200000, P_BI_TCXO
, 1, 0, 0),
278 F(37500000, P_DISP_CC_PLL1_OUT_MAIN
, 16, 0, 0),
279 F(75000000, P_DISP_CC_PLL1_OUT_MAIN
, 8, 0, 0),
283 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src
= {
287 .parent_map
= disp_cc_parent_map_6
,
288 .freq_tbl
= ftbl_disp_cc_mdss_ahb_clk_src
,
289 .clkr
.hw
.init
= &(const struct clk_init_data
) {
290 .name
= "disp_cc_mdss_ahb_clk_src",
291 .parent_data
= disp_cc_parent_data_6
,
292 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_6
),
293 .flags
= CLK_SET_RATE_PARENT
,
294 .ops
= &clk_rcg2_shared_ops
,
298 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src
[] = {
299 F(19200000, P_BI_TCXO
, 1, 0, 0),
303 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src
= {
307 .parent_map
= disp_cc_parent_map_2
,
308 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
309 .clkr
.hw
.init
= &(const struct clk_init_data
) {
310 .name
= "disp_cc_mdss_byte0_clk_src",
311 .parent_data
= disp_cc_parent_data_2
,
312 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_2
),
313 .flags
= CLK_SET_RATE_PARENT
,
314 .ops
= &clk_byte2_ops
,
318 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src
= {
322 .parent_map
= disp_cc_parent_map_2
,
323 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
324 .clkr
.hw
.init
= &(const struct clk_init_data
) {
325 .name
= "disp_cc_mdss_byte1_clk_src",
326 .parent_data
= disp_cc_parent_data_2
,
327 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_2
),
328 .flags
= CLK_SET_RATE_PARENT
,
329 .ops
= &clk_byte2_ops
,
333 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src
= {
337 .parent_map
= disp_cc_parent_map_0
,
338 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
339 .clkr
.hw
.init
= &(const struct clk_init_data
) {
340 .name
= "disp_cc_mdss_dptx0_aux_clk_src",
341 .parent_data
= disp_cc_parent_data_0
,
342 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_0
),
343 .flags
= CLK_SET_RATE_PARENT
,
344 .ops
= &clk_rcg2_ops
,
348 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src
= {
352 .parent_map
= disp_cc_parent_map_7
,
353 .clkr
.hw
.init
= &(const struct clk_init_data
) {
354 .name
= "disp_cc_mdss_dptx0_link_clk_src",
355 .parent_data
= disp_cc_parent_data_7
,
356 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_7
),
357 .flags
= CLK_SET_RATE_PARENT
,
358 .ops
= &clk_byte2_ops
,
362 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src
= {
366 .parent_map
= disp_cc_parent_map_4
,
367 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
368 .clkr
.hw
.init
= &(const struct clk_init_data
) {
369 .name
= "disp_cc_mdss_dptx0_pixel0_clk_src",
370 .parent_data
= disp_cc_parent_data_4
,
371 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_4
),
372 .flags
= CLK_SET_RATE_PARENT
,
377 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src
= {
381 .parent_map
= disp_cc_parent_map_4
,
382 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
383 .clkr
.hw
.init
= &(const struct clk_init_data
) {
384 .name
= "disp_cc_mdss_dptx0_pixel1_clk_src",
385 .parent_data
= disp_cc_parent_data_4
,
386 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_4
),
387 .flags
= CLK_SET_RATE_PARENT
,
392 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src
= {
396 .parent_map
= disp_cc_parent_map_0
,
397 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
398 .clkr
.hw
.init
= &(const struct clk_init_data
) {
399 .name
= "disp_cc_mdss_dptx1_aux_clk_src",
400 .parent_data
= disp_cc_parent_data_0
,
401 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_0
),
402 .flags
= CLK_SET_RATE_PARENT
,
403 .ops
= &clk_rcg2_ops
,
407 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src
= {
411 .parent_map
= disp_cc_parent_map_3
,
412 .clkr
.hw
.init
= &(const struct clk_init_data
) {
413 .name
= "disp_cc_mdss_dptx1_link_clk_src",
414 .parent_data
= disp_cc_parent_data_3
,
415 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_3
),
416 .flags
= CLK_SET_RATE_PARENT
,
417 .ops
= &clk_byte2_ops
,
421 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src
= {
425 .parent_map
= disp_cc_parent_map_1
,
426 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
427 .clkr
.hw
.init
= &(const struct clk_init_data
) {
428 .name
= "disp_cc_mdss_dptx1_pixel0_clk_src",
429 .parent_data
= disp_cc_parent_data_1
,
430 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_1
),
431 .flags
= CLK_SET_RATE_PARENT
,
436 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src
= {
440 .parent_map
= disp_cc_parent_map_1
,
441 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
442 .clkr
.hw
.init
= &(const struct clk_init_data
) {
443 .name
= "disp_cc_mdss_dptx1_pixel1_clk_src",
444 .parent_data
= disp_cc_parent_data_1
,
445 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_1
),
446 .flags
= CLK_SET_RATE_PARENT
,
451 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src
= {
455 .parent_map
= disp_cc_parent_map_0
,
456 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
457 .clkr
.hw
.init
= &(const struct clk_init_data
) {
458 .name
= "disp_cc_mdss_dptx2_aux_clk_src",
459 .parent_data
= disp_cc_parent_data_0
,
460 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_0
),
461 .flags
= CLK_SET_RATE_PARENT
,
462 .ops
= &clk_rcg2_ops
,
466 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src
= {
470 .parent_map
= disp_cc_parent_map_3
,
471 .clkr
.hw
.init
= &(const struct clk_init_data
) {
472 .name
= "disp_cc_mdss_dptx2_link_clk_src",
473 .parent_data
= disp_cc_parent_data_3
,
474 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_3
),
475 .flags
= CLK_SET_RATE_PARENT
,
476 .ops
= &clk_byte2_ops
,
480 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src
= {
484 .parent_map
= disp_cc_parent_map_1
,
485 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
486 .clkr
.hw
.init
= &(const struct clk_init_data
) {
487 .name
= "disp_cc_mdss_dptx2_pixel0_clk_src",
488 .parent_data
= disp_cc_parent_data_1
,
489 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_1
),
490 .flags
= CLK_SET_RATE_PARENT
,
495 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src
= {
499 .parent_map
= disp_cc_parent_map_1
,
500 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
501 .clkr
.hw
.init
= &(const struct clk_init_data
) {
502 .name
= "disp_cc_mdss_dptx2_pixel1_clk_src",
503 .parent_data
= disp_cc_parent_data_1
,
504 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_1
),
505 .flags
= CLK_SET_RATE_PARENT
,
510 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src
= {
514 .parent_map
= disp_cc_parent_map_0
,
515 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
516 .clkr
.hw
.init
= &(const struct clk_init_data
) {
517 .name
= "disp_cc_mdss_dptx3_aux_clk_src",
518 .parent_data
= disp_cc_parent_data_0
,
519 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_0
),
520 .flags
= CLK_SET_RATE_PARENT
,
521 .ops
= &clk_rcg2_ops
,
525 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src
= {
529 .parent_map
= disp_cc_parent_map_3
,
530 .clkr
.hw
.init
= &(const struct clk_init_data
) {
531 .name
= "disp_cc_mdss_dptx3_link_clk_src",
532 .parent_data
= disp_cc_parent_data_3
,
533 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_3
),
534 .flags
= CLK_SET_RATE_PARENT
,
535 .ops
= &clk_byte2_ops
,
539 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src
= {
543 .parent_map
= disp_cc_parent_map_1
,
544 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
545 .clkr
.hw
.init
= &(const struct clk_init_data
) {
546 .name
= "disp_cc_mdss_dptx3_pixel0_clk_src",
547 .parent_data
= disp_cc_parent_data_1
,
548 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_1
),
549 .flags
= CLK_SET_RATE_PARENT
,
554 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src
= {
558 .parent_map
= disp_cc_parent_map_5
,
559 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
560 .clkr
.hw
.init
= &(const struct clk_init_data
) {
561 .name
= "disp_cc_mdss_esc0_clk_src",
562 .parent_data
= disp_cc_parent_data_5
,
563 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_5
),
564 .flags
= CLK_SET_RATE_PARENT
,
565 .ops
= &clk_rcg2_shared_ops
,
569 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src
= {
573 .parent_map
= disp_cc_parent_map_5
,
574 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
575 .clkr
.hw
.init
= &(const struct clk_init_data
) {
576 .name
= "disp_cc_mdss_esc1_clk_src",
577 .parent_data
= disp_cc_parent_data_5
,
578 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_5
),
579 .flags
= CLK_SET_RATE_PARENT
,
580 .ops
= &clk_rcg2_shared_ops
,
584 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src
[] = {
585 F(19200000, P_BI_TCXO
, 1, 0, 0),
586 F(85714286, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
587 F(100000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
588 F(150000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
589 F(172000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
590 F(200000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
591 F(325000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
592 F(375000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
593 F(514000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
597 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p
[] = {
598 F(200000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
599 F(325000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
600 F(514000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
604 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650
[] = {
605 F(19200000, P_BI_TCXO
, 1, 0, 0),
606 F(85714286, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
607 F(100000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
608 F(150000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
609 F(200000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
610 F(325000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
611 F(402000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
612 F(514000000, P_DISP_CC_PLL0_OUT_MAIN
, 3, 0, 0),
616 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src
= {
620 .parent_map
= disp_cc_parent_map_8
,
621 .freq_tbl
= ftbl_disp_cc_mdss_mdp_clk_src
,
622 .clkr
.hw
.init
= &(const struct clk_init_data
) {
623 .name
= "disp_cc_mdss_mdp_clk_src",
624 .parent_data
= disp_cc_parent_data_8
,
625 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_8
),
626 .flags
= CLK_SET_RATE_PARENT
,
627 .ops
= &clk_rcg2_shared_ops
,
631 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src
= {
635 .parent_map
= disp_cc_parent_map_2
,
636 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
637 .clkr
.hw
.init
= &(const struct clk_init_data
) {
638 .name
= "disp_cc_mdss_pclk0_clk_src",
639 .parent_data
= disp_cc_parent_data_2
,
640 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_2
),
641 .flags
= CLK_SET_RATE_PARENT
,
642 .ops
= &clk_pixel_ops
,
646 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src
= {
650 .parent_map
= disp_cc_parent_map_2
,
651 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
652 .clkr
.hw
.init
= &(const struct clk_init_data
) {
653 .name
= "disp_cc_mdss_pclk1_clk_src",
654 .parent_data
= disp_cc_parent_data_2
,
655 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_2
),
656 .flags
= CLK_SET_RATE_PARENT
,
657 .ops
= &clk_pixel_ops
,
661 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src
= {
665 .parent_map
= disp_cc_parent_map_0
,
666 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
667 .clkr
.hw
.init
= &(const struct clk_init_data
) {
668 .name
= "disp_cc_mdss_vsync_clk_src",
669 .parent_data
= disp_cc_parent_data_0
,
670 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_0
),
671 .flags
= CLK_SET_RATE_PARENT
,
672 .ops
= &clk_rcg2_ops
,
676 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src
[] = {
677 F(32000, P_SLEEP_CLK
, 1, 0, 0),
681 static struct clk_rcg2 disp_cc_sleep_clk_src
= {
685 .parent_map
= disp_cc_parent_map_9
,
686 .freq_tbl
= ftbl_disp_cc_sleep_clk_src
,
687 .clkr
.hw
.init
= &(const struct clk_init_data
) {
688 .name
= "disp_cc_sleep_clk_src",
689 .parent_data
= disp_cc_parent_data_9
,
690 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_9
),
691 .flags
= CLK_SET_RATE_PARENT
,
692 .ops
= &clk_rcg2_ops
,
696 static struct clk_rcg2 disp_cc_xo_clk_src
= {
700 .parent_map
= disp_cc_parent_map_0
,
701 .freq_tbl
= ftbl_disp_cc_mdss_byte0_clk_src
,
702 .clkr
.hw
.init
= &(const struct clk_init_data
) {
703 .name
= "disp_cc_xo_clk_src",
704 .parent_data
= disp_cc_parent_data_0_ao
,
705 .num_parents
= ARRAY_SIZE(disp_cc_parent_data_0_ao
),
706 .flags
= CLK_SET_RATE_PARENT
,
707 .ops
= &clk_rcg2_ops
,
711 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src
= {
715 .clkr
.hw
.init
= &(const struct clk_init_data
) {
716 .name
= "disp_cc_mdss_byte0_div_clk_src",
717 .parent_hws
= (const struct clk_hw
*[]) {
718 &disp_cc_mdss_byte0_clk_src
.clkr
.hw
,
721 .ops
= &clk_regmap_div_ops
,
725 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src
= {
729 .clkr
.hw
.init
= &(const struct clk_init_data
) {
730 .name
= "disp_cc_mdss_byte1_div_clk_src",
731 .parent_hws
= (const struct clk_hw
*[]) {
732 &disp_cc_mdss_byte1_clk_src
.clkr
.hw
,
735 .ops
= &clk_regmap_div_ops
,
739 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src
= {
743 .clkr
.hw
.init
= &(const struct clk_init_data
) {
744 .name
= "disp_cc_mdss_dptx0_link_div_clk_src",
745 .parent_hws
= (const struct clk_hw
*[]) {
746 &disp_cc_mdss_dptx0_link_clk_src
.clkr
.hw
,
749 .flags
= CLK_SET_RATE_PARENT
,
750 .ops
= &clk_regmap_div_ro_ops
,
754 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src
= {
758 .clkr
.hw
.init
= &(const struct clk_init_data
) {
759 .name
= "disp_cc_mdss_dptx1_link_div_clk_src",
760 .parent_hws
= (const struct clk_hw
*[]) {
761 &disp_cc_mdss_dptx1_link_clk_src
.clkr
.hw
,
764 .flags
= CLK_SET_RATE_PARENT
,
765 .ops
= &clk_regmap_div_ro_ops
,
769 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src
= {
773 .clkr
.hw
.init
= &(const struct clk_init_data
) {
774 .name
= "disp_cc_mdss_dptx2_link_div_clk_src",
775 .parent_hws
= (const struct clk_hw
*[]) {
776 &disp_cc_mdss_dptx2_link_clk_src
.clkr
.hw
,
779 .flags
= CLK_SET_RATE_PARENT
,
780 .ops
= &clk_regmap_div_ro_ops
,
784 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src
= {
788 .clkr
.hw
.init
= &(const struct clk_init_data
) {
789 .name
= "disp_cc_mdss_dptx3_link_div_clk_src",
790 .parent_hws
= (const struct clk_hw
*[]) {
791 &disp_cc_mdss_dptx3_link_clk_src
.clkr
.hw
,
794 .flags
= CLK_SET_RATE_PARENT
,
795 .ops
= &clk_regmap_div_ro_ops
,
799 static struct clk_branch disp_cc_mdss_accu_clk
= {
801 .halt_check
= BRANCH_HALT_VOTED
,
803 .enable_reg
= 0xe058,
804 .enable_mask
= BIT(0),
805 .hw
.init
= &(const struct clk_init_data
) {
806 .name
= "disp_cc_mdss_accu_clk",
807 .parent_hws
= (const struct clk_hw
*[]) {
808 &disp_cc_xo_clk_src
.clkr
.hw
,
811 .flags
= CLK_SET_RATE_PARENT
,
812 .ops
= &clk_branch2_ops
,
817 static struct clk_branch disp_cc_mdss_ahb1_clk
= {
819 .halt_check
= BRANCH_HALT
,
821 .enable_reg
= 0xa020,
822 .enable_mask
= BIT(0),
823 .hw
.init
= &(const struct clk_init_data
) {
824 .name
= "disp_cc_mdss_ahb1_clk",
825 .parent_hws
= (const struct clk_hw
*[]) {
826 &disp_cc_mdss_ahb_clk_src
.clkr
.hw
,
829 .flags
= CLK_SET_RATE_PARENT
,
830 .ops
= &clk_branch2_ops
,
835 static struct clk_branch disp_cc_mdss_ahb_clk
= {
837 .halt_check
= BRANCH_HALT
,
839 .enable_reg
= 0x80a4,
840 .enable_mask
= BIT(0),
841 .hw
.init
= &(const struct clk_init_data
) {
842 .name
= "disp_cc_mdss_ahb_clk",
843 .parent_hws
= (const struct clk_hw
*[]) {
844 &disp_cc_mdss_ahb_clk_src
.clkr
.hw
,
847 .flags
= CLK_SET_RATE_PARENT
,
848 .ops
= &clk_branch2_ops
,
853 static struct clk_branch disp_cc_mdss_byte0_clk
= {
855 .halt_check
= BRANCH_HALT
,
857 .enable_reg
= 0x8028,
858 .enable_mask
= BIT(0),
859 .hw
.init
= &(const struct clk_init_data
) {
860 .name
= "disp_cc_mdss_byte0_clk",
861 .parent_hws
= (const struct clk_hw
*[]) {
862 &disp_cc_mdss_byte0_clk_src
.clkr
.hw
,
865 .flags
= CLK_SET_RATE_PARENT
,
866 .ops
= &clk_branch2_ops
,
871 static struct clk_branch disp_cc_mdss_byte0_intf_clk
= {
873 .halt_check
= BRANCH_HALT
,
875 .enable_reg
= 0x802c,
876 .enable_mask
= BIT(0),
877 .hw
.init
= &(const struct clk_init_data
) {
878 .name
= "disp_cc_mdss_byte0_intf_clk",
879 .parent_hws
= (const struct clk_hw
*[]) {
880 &disp_cc_mdss_byte0_div_clk_src
.clkr
.hw
,
883 .flags
= CLK_SET_RATE_PARENT
,
884 .ops
= &clk_branch2_ops
,
889 static struct clk_branch disp_cc_mdss_byte1_clk
= {
891 .halt_check
= BRANCH_HALT
,
893 .enable_reg
= 0x8030,
894 .enable_mask
= BIT(0),
895 .hw
.init
= &(const struct clk_init_data
) {
896 .name
= "disp_cc_mdss_byte1_clk",
897 .parent_hws
= (const struct clk_hw
*[]) {
898 &disp_cc_mdss_byte1_clk_src
.clkr
.hw
,
901 .flags
= CLK_SET_RATE_PARENT
,
902 .ops
= &clk_branch2_ops
,
907 static struct clk_branch disp_cc_mdss_byte1_intf_clk
= {
909 .halt_check
= BRANCH_HALT
,
911 .enable_reg
= 0x8034,
912 .enable_mask
= BIT(0),
913 .hw
.init
= &(const struct clk_init_data
) {
914 .name
= "disp_cc_mdss_byte1_intf_clk",
915 .parent_hws
= (const struct clk_hw
*[]) {
916 &disp_cc_mdss_byte1_div_clk_src
.clkr
.hw
,
919 .flags
= CLK_SET_RATE_PARENT
,
920 .ops
= &clk_branch2_ops
,
925 static struct clk_branch disp_cc_mdss_dptx0_aux_clk
= {
927 .halt_check
= BRANCH_HALT
,
929 .enable_reg
= 0x8058,
930 .enable_mask
= BIT(0),
931 .hw
.init
= &(const struct clk_init_data
) {
932 .name
= "disp_cc_mdss_dptx0_aux_clk",
933 .parent_hws
= (const struct clk_hw
*[]) {
934 &disp_cc_mdss_dptx0_aux_clk_src
.clkr
.hw
,
937 .flags
= CLK_SET_RATE_PARENT
,
938 .ops
= &clk_branch2_ops
,
943 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk
= {
945 .halt_check
= BRANCH_HALT
,
947 .enable_reg
= 0x804c,
948 .enable_mask
= BIT(0),
949 .hw
.init
= &(const struct clk_init_data
) {
950 .name
= "disp_cc_mdss_dptx0_crypto_clk",
951 .parent_hws
= (const struct clk_hw
*[]) {
952 &disp_cc_mdss_dptx0_link_clk_src
.clkr
.hw
,
955 .flags
= CLK_SET_RATE_PARENT
,
956 .ops
= &clk_branch2_ops
,
961 static struct clk_branch disp_cc_mdss_dptx0_link_clk
= {
963 .halt_check
= BRANCH_HALT
,
965 .enable_reg
= 0x8040,
966 .enable_mask
= BIT(0),
967 .hw
.init
= &(const struct clk_init_data
) {
968 .name
= "disp_cc_mdss_dptx0_link_clk",
969 .parent_hws
= (const struct clk_hw
*[]) {
970 &disp_cc_mdss_dptx0_link_clk_src
.clkr
.hw
,
973 .flags
= CLK_SET_RATE_PARENT
,
974 .ops
= &clk_branch2_ops
,
979 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk
= {
981 .halt_check
= BRANCH_HALT
,
983 .enable_reg
= 0x8048,
984 .enable_mask
= BIT(0),
985 .hw
.init
= &(const struct clk_init_data
) {
986 .name
= "disp_cc_mdss_dptx0_link_intf_clk",
987 .parent_hws
= (const struct clk_hw
*[]) {
988 &disp_cc_mdss_dptx0_link_div_clk_src
.clkr
.hw
,
991 .flags
= CLK_SET_RATE_PARENT
,
992 .ops
= &clk_branch2_ops
,
997 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk
= {
999 .halt_check
= BRANCH_HALT
,
1001 .enable_reg
= 0x8050,
1002 .enable_mask
= BIT(0),
1003 .hw
.init
= &(const struct clk_init_data
) {
1004 .name
= "disp_cc_mdss_dptx0_pixel0_clk",
1005 .parent_hws
= (const struct clk_hw
*[]) {
1006 &disp_cc_mdss_dptx0_pixel0_clk_src
.clkr
.hw
,
1009 .flags
= CLK_SET_RATE_PARENT
,
1010 .ops
= &clk_branch2_ops
,
1015 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk
= {
1017 .halt_check
= BRANCH_HALT
,
1019 .enable_reg
= 0x8054,
1020 .enable_mask
= BIT(0),
1021 .hw
.init
= &(const struct clk_init_data
) {
1022 .name
= "disp_cc_mdss_dptx0_pixel1_clk",
1023 .parent_hws
= (const struct clk_hw
*[]) {
1024 &disp_cc_mdss_dptx0_pixel1_clk_src
.clkr
.hw
,
1027 .flags
= CLK_SET_RATE_PARENT
,
1028 .ops
= &clk_branch2_ops
,
1033 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk
= {
1035 .halt_check
= BRANCH_HALT
,
1037 .enable_reg
= 0x8044,
1038 .enable_mask
= BIT(0),
1039 .hw
.init
= &(const struct clk_init_data
) {
1040 .name
= "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1041 .parent_hws
= (const struct clk_hw
*[]) {
1042 &disp_cc_mdss_dptx0_link_div_clk_src
.clkr
.hw
,
1045 .flags
= CLK_SET_RATE_PARENT
,
1046 .ops
= &clk_branch2_ops
,
1051 static struct clk_branch disp_cc_mdss_dptx1_aux_clk
= {
1053 .halt_check
= BRANCH_HALT
,
1055 .enable_reg
= 0x8074,
1056 .enable_mask
= BIT(0),
1057 .hw
.init
= &(const struct clk_init_data
) {
1058 .name
= "disp_cc_mdss_dptx1_aux_clk",
1059 .parent_hws
= (const struct clk_hw
*[]) {
1060 &disp_cc_mdss_dptx1_aux_clk_src
.clkr
.hw
,
1063 .flags
= CLK_SET_RATE_PARENT
,
1064 .ops
= &clk_branch2_ops
,
1069 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk
= {
1071 .halt_check
= BRANCH_HALT
,
1073 .enable_reg
= 0x8070,
1074 .enable_mask
= BIT(0),
1075 .hw
.init
= &(const struct clk_init_data
) {
1076 .name
= "disp_cc_mdss_dptx1_crypto_clk",
1077 .parent_hws
= (const struct clk_hw
*[]) {
1078 &disp_cc_mdss_dptx1_link_clk_src
.clkr
.hw
,
1081 .flags
= CLK_SET_RATE_PARENT
,
1082 .ops
= &clk_branch2_ops
,
1087 static struct clk_branch disp_cc_mdss_dptx1_link_clk
= {
1089 .halt_check
= BRANCH_HALT
,
1091 .enable_reg
= 0x8064,
1092 .enable_mask
= BIT(0),
1093 .hw
.init
= &(const struct clk_init_data
) {
1094 .name
= "disp_cc_mdss_dptx1_link_clk",
1095 .parent_hws
= (const struct clk_hw
*[]) {
1096 &disp_cc_mdss_dptx1_link_clk_src
.clkr
.hw
,
1099 .flags
= CLK_SET_RATE_PARENT
,
1100 .ops
= &clk_branch2_ops
,
1105 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk
= {
1107 .halt_check
= BRANCH_HALT
,
1109 .enable_reg
= 0x806c,
1110 .enable_mask
= BIT(0),
1111 .hw
.init
= &(const struct clk_init_data
) {
1112 .name
= "disp_cc_mdss_dptx1_link_intf_clk",
1113 .parent_hws
= (const struct clk_hw
*[]) {
1114 &disp_cc_mdss_dptx1_link_div_clk_src
.clkr
.hw
,
1117 .flags
= CLK_SET_RATE_PARENT
,
1118 .ops
= &clk_branch2_ops
,
1123 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk
= {
1125 .halt_check
= BRANCH_HALT
,
1127 .enable_reg
= 0x805c,
1128 .enable_mask
= BIT(0),
1129 .hw
.init
= &(const struct clk_init_data
) {
1130 .name
= "disp_cc_mdss_dptx1_pixel0_clk",
1131 .parent_hws
= (const struct clk_hw
*[]) {
1132 &disp_cc_mdss_dptx1_pixel0_clk_src
.clkr
.hw
,
1135 .flags
= CLK_SET_RATE_PARENT
,
1136 .ops
= &clk_branch2_ops
,
1141 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk
= {
1143 .halt_check
= BRANCH_HALT
,
1145 .enable_reg
= 0x8060,
1146 .enable_mask
= BIT(0),
1147 .hw
.init
= &(const struct clk_init_data
) {
1148 .name
= "disp_cc_mdss_dptx1_pixel1_clk",
1149 .parent_hws
= (const struct clk_hw
*[]) {
1150 &disp_cc_mdss_dptx1_pixel1_clk_src
.clkr
.hw
,
1153 .flags
= CLK_SET_RATE_PARENT
,
1154 .ops
= &clk_branch2_ops
,
1159 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk
= {
1161 .halt_check
= BRANCH_HALT
,
1163 .enable_reg
= 0x8068,
1164 .enable_mask
= BIT(0),
1165 .hw
.init
= &(const struct clk_init_data
) {
1166 .name
= "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1167 .parent_hws
= (const struct clk_hw
*[]) {
1168 &disp_cc_mdss_dptx0_link_div_clk_src
.clkr
.hw
,
1171 .flags
= CLK_SET_RATE_PARENT
,
1172 .ops
= &clk_branch2_ops
,
1177 static struct clk_branch disp_cc_mdss_dptx2_aux_clk
= {
1179 .halt_check
= BRANCH_HALT
,
1181 .enable_reg
= 0x808c,
1182 .enable_mask
= BIT(0),
1183 .hw
.init
= &(const struct clk_init_data
) {
1184 .name
= "disp_cc_mdss_dptx2_aux_clk",
1185 .parent_hws
= (const struct clk_hw
*[]) {
1186 &disp_cc_mdss_dptx2_aux_clk_src
.clkr
.hw
,
1189 .flags
= CLK_SET_RATE_PARENT
,
1190 .ops
= &clk_branch2_ops
,
1195 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk
= {
1197 .halt_check
= BRANCH_HALT
,
1199 .enable_reg
= 0x8088,
1200 .enable_mask
= BIT(0),
1201 .hw
.init
= &(const struct clk_init_data
) {
1202 .name
= "disp_cc_mdss_dptx2_crypto_clk",
1203 .parent_hws
= (const struct clk_hw
*[]) {
1204 &disp_cc_mdss_dptx2_link_clk_src
.clkr
.hw
,
1207 .flags
= CLK_SET_RATE_PARENT
,
1208 .ops
= &clk_branch2_ops
,
1213 static struct clk_branch disp_cc_mdss_dptx2_link_clk
= {
1215 .halt_check
= BRANCH_HALT
,
1217 .enable_reg
= 0x8080,
1218 .enable_mask
= BIT(0),
1219 .hw
.init
= &(const struct clk_init_data
) {
1220 .name
= "disp_cc_mdss_dptx2_link_clk",
1221 .parent_hws
= (const struct clk_hw
*[]) {
1222 &disp_cc_mdss_dptx2_link_clk_src
.clkr
.hw
,
1225 .flags
= CLK_SET_RATE_PARENT
,
1226 .ops
= &clk_branch2_ops
,
1231 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk
= {
1233 .halt_check
= BRANCH_HALT
,
1235 .enable_reg
= 0x8084,
1236 .enable_mask
= BIT(0),
1237 .hw
.init
= &(const struct clk_init_data
) {
1238 .name
= "disp_cc_mdss_dptx2_link_intf_clk",
1239 .parent_hws
= (const struct clk_hw
*[]) {
1240 &disp_cc_mdss_dptx2_link_div_clk_src
.clkr
.hw
,
1243 .flags
= CLK_SET_RATE_PARENT
,
1244 .ops
= &clk_branch2_ops
,
1249 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk
= {
1251 .halt_check
= BRANCH_HALT
,
1253 .enable_reg
= 0x8078,
1254 .enable_mask
= BIT(0),
1255 .hw
.init
= &(const struct clk_init_data
) {
1256 .name
= "disp_cc_mdss_dptx2_pixel0_clk",
1257 .parent_hws
= (const struct clk_hw
*[]) {
1258 &disp_cc_mdss_dptx2_pixel0_clk_src
.clkr
.hw
,
1261 .flags
= CLK_SET_RATE_PARENT
,
1262 .ops
= &clk_branch2_ops
,
1267 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk
= {
1269 .halt_check
= BRANCH_HALT
,
1271 .enable_reg
= 0x807c,
1272 .enable_mask
= BIT(0),
1273 .hw
.init
= &(const struct clk_init_data
) {
1274 .name
= "disp_cc_mdss_dptx2_pixel1_clk",
1275 .parent_hws
= (const struct clk_hw
*[]) {
1276 &disp_cc_mdss_dptx2_pixel1_clk_src
.clkr
.hw
,
1279 .flags
= CLK_SET_RATE_PARENT
,
1280 .ops
= &clk_branch2_ops
,
1285 static struct clk_branch disp_cc_mdss_dptx3_aux_clk
= {
1287 .halt_check
= BRANCH_HALT
,
1289 .enable_reg
= 0x809c,
1290 .enable_mask
= BIT(0),
1291 .hw
.init
= &(const struct clk_init_data
) {
1292 .name
= "disp_cc_mdss_dptx3_aux_clk",
1293 .parent_hws
= (const struct clk_hw
*[]) {
1294 &disp_cc_mdss_dptx3_aux_clk_src
.clkr
.hw
,
1297 .flags
= CLK_SET_RATE_PARENT
,
1298 .ops
= &clk_branch2_ops
,
1303 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk
= {
1305 .halt_check
= BRANCH_HALT
,
1307 .enable_reg
= 0x80a0,
1308 .enable_mask
= BIT(0),
1309 .hw
.init
= &(const struct clk_init_data
) {
1310 .name
= "disp_cc_mdss_dptx3_crypto_clk",
1311 .parent_hws
= (const struct clk_hw
*[]) {
1312 &disp_cc_mdss_dptx3_link_clk_src
.clkr
.hw
,
1315 .flags
= CLK_SET_RATE_PARENT
,
1316 .ops
= &clk_branch2_ops
,
1321 static struct clk_branch disp_cc_mdss_dptx3_link_clk
= {
1323 .halt_check
= BRANCH_HALT
,
1325 .enable_reg
= 0x8094,
1326 .enable_mask
= BIT(0),
1327 .hw
.init
= &(const struct clk_init_data
) {
1328 .name
= "disp_cc_mdss_dptx3_link_clk",
1329 .parent_hws
= (const struct clk_hw
*[]) {
1330 &disp_cc_mdss_dptx3_link_clk_src
.clkr
.hw
,
1333 .flags
= CLK_SET_RATE_PARENT
,
1334 .ops
= &clk_branch2_ops
,
1339 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk
= {
1341 .halt_check
= BRANCH_HALT
,
1343 .enable_reg
= 0x8098,
1344 .enable_mask
= BIT(0),
1345 .hw
.init
= &(const struct clk_init_data
) {
1346 .name
= "disp_cc_mdss_dptx3_link_intf_clk",
1347 .parent_hws
= (const struct clk_hw
*[]) {
1348 &disp_cc_mdss_dptx3_link_div_clk_src
.clkr
.hw
,
1351 .flags
= CLK_SET_RATE_PARENT
,
1352 .ops
= &clk_branch2_ops
,
1357 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk
= {
1359 .halt_check
= BRANCH_HALT
,
1361 .enable_reg
= 0x8090,
1362 .enable_mask
= BIT(0),
1363 .hw
.init
= &(const struct clk_init_data
) {
1364 .name
= "disp_cc_mdss_dptx3_pixel0_clk",
1365 .parent_hws
= (const struct clk_hw
*[]) {
1366 &disp_cc_mdss_dptx3_pixel0_clk_src
.clkr
.hw
,
1369 .flags
= CLK_SET_RATE_PARENT
,
1370 .ops
= &clk_branch2_ops
,
1375 static struct clk_branch disp_cc_mdss_esc0_clk
= {
1377 .halt_check
= BRANCH_HALT
,
1379 .enable_reg
= 0x8038,
1380 .enable_mask
= BIT(0),
1381 .hw
.init
= &(const struct clk_init_data
) {
1382 .name
= "disp_cc_mdss_esc0_clk",
1383 .parent_hws
= (const struct clk_hw
*[]) {
1384 &disp_cc_mdss_esc0_clk_src
.clkr
.hw
,
1387 .flags
= CLK_SET_RATE_PARENT
,
1388 .ops
= &clk_branch2_ops
,
1393 static struct clk_branch disp_cc_mdss_esc1_clk
= {
1395 .halt_check
= BRANCH_HALT
,
1397 .enable_reg
= 0x803c,
1398 .enable_mask
= BIT(0),
1399 .hw
.init
= &(const struct clk_init_data
) {
1400 .name
= "disp_cc_mdss_esc1_clk",
1401 .parent_hws
= (const struct clk_hw
*[]) {
1402 &disp_cc_mdss_esc1_clk_src
.clkr
.hw
,
1405 .flags
= CLK_SET_RATE_PARENT
,
1406 .ops
= &clk_branch2_ops
,
1411 static struct clk_branch disp_cc_mdss_mdp1_clk
= {
1413 .halt_check
= BRANCH_HALT
,
1415 .enable_reg
= 0xa004,
1416 .enable_mask
= BIT(0),
1417 .hw
.init
= &(const struct clk_init_data
) {
1418 .name
= "disp_cc_mdss_mdp1_clk",
1419 .parent_hws
= (const struct clk_hw
*[]) {
1420 &disp_cc_mdss_mdp_clk_src
.clkr
.hw
,
1423 .flags
= CLK_SET_RATE_PARENT
,
1424 .ops
= &clk_branch2_ops
,
1429 static struct clk_branch disp_cc_mdss_mdp_clk
= {
1431 .halt_check
= BRANCH_HALT
,
1433 .enable_reg
= 0x800c,
1434 .enable_mask
= BIT(0),
1435 .hw
.init
= &(const struct clk_init_data
) {
1436 .name
= "disp_cc_mdss_mdp_clk",
1437 .parent_hws
= (const struct clk_hw
*[]) {
1438 &disp_cc_mdss_mdp_clk_src
.clkr
.hw
,
1441 .flags
= CLK_SET_RATE_PARENT
,
1442 .ops
= &clk_branch2_ops
,
1447 static struct clk_branch disp_cc_mdss_mdp_lut1_clk
= {
1449 .halt_check
= BRANCH_HALT
,
1451 .enable_reg
= 0xa010,
1452 .enable_mask
= BIT(0),
1453 .hw
.init
= &(const struct clk_init_data
) {
1454 .name
= "disp_cc_mdss_mdp_lut1_clk",
1455 .parent_hws
= (const struct clk_hw
*[]) {
1456 &disp_cc_mdss_mdp_clk_src
.clkr
.hw
,
1459 .flags
= CLK_SET_RATE_PARENT
,
1460 .ops
= &clk_branch2_ops
,
1465 static struct clk_branch disp_cc_mdss_mdp_lut_clk
= {
1467 .halt_check
= BRANCH_HALT_VOTED
,
1469 .enable_reg
= 0x8018,
1470 .enable_mask
= BIT(0),
1471 .hw
.init
= &(const struct clk_init_data
) {
1472 .name
= "disp_cc_mdss_mdp_lut_clk",
1473 .parent_hws
= (const struct clk_hw
*[]) {
1474 &disp_cc_mdss_mdp_clk_src
.clkr
.hw
,
1477 .flags
= CLK_SET_RATE_PARENT
,
1478 .ops
= &clk_branch2_ops
,
1483 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk
= {
1485 .halt_check
= BRANCH_HALT_VOTED
,
1487 .enable_reg
= 0xc004,
1488 .enable_mask
= BIT(0),
1489 .hw
.init
= &(const struct clk_init_data
) {
1490 .name
= "disp_cc_mdss_non_gdsc_ahb_clk",
1491 .parent_hws
= (const struct clk_hw
*[]) {
1492 &disp_cc_mdss_ahb_clk_src
.clkr
.hw
,
1495 .flags
= CLK_SET_RATE_PARENT
,
1496 .ops
= &clk_branch2_ops
,
1501 static struct clk_branch disp_cc_mdss_pclk0_clk
= {
1503 .halt_check
= BRANCH_HALT
,
1505 .enable_reg
= 0x8004,
1506 .enable_mask
= BIT(0),
1507 .hw
.init
= &(const struct clk_init_data
) {
1508 .name
= "disp_cc_mdss_pclk0_clk",
1509 .parent_hws
= (const struct clk_hw
*[]) {
1510 &disp_cc_mdss_pclk0_clk_src
.clkr
.hw
,
1513 .flags
= CLK_SET_RATE_PARENT
,
1514 .ops
= &clk_branch2_ops
,
1519 static struct clk_branch disp_cc_mdss_pclk1_clk
= {
1521 .halt_check
= BRANCH_HALT
,
1523 .enable_reg
= 0x8008,
1524 .enable_mask
= BIT(0),
1525 .hw
.init
= &(const struct clk_init_data
) {
1526 .name
= "disp_cc_mdss_pclk1_clk",
1527 .parent_hws
= (const struct clk_hw
*[]) {
1528 &disp_cc_mdss_pclk1_clk_src
.clkr
.hw
,
1531 .flags
= CLK_SET_RATE_PARENT
,
1532 .ops
= &clk_branch2_ops
,
1537 static struct clk_branch disp_cc_mdss_rscc_ahb_clk
= {
1539 .halt_check
= BRANCH_HALT
,
1541 .enable_reg
= 0xc00c,
1542 .enable_mask
= BIT(0),
1543 .hw
.init
= &(const struct clk_init_data
) {
1544 .name
= "disp_cc_mdss_rscc_ahb_clk",
1545 .parent_hws
= (const struct clk_hw
*[]) {
1546 &disp_cc_mdss_ahb_clk_src
.clkr
.hw
,
1549 .flags
= CLK_SET_RATE_PARENT
,
1550 .ops
= &clk_branch2_ops
,
1555 static struct clk_branch disp_cc_mdss_rscc_vsync_clk
= {
1557 .halt_check
= BRANCH_HALT
,
1559 .enable_reg
= 0xc008,
1560 .enable_mask
= BIT(0),
1561 .hw
.init
= &(const struct clk_init_data
) {
1562 .name
= "disp_cc_mdss_rscc_vsync_clk",
1563 .parent_hws
= (const struct clk_hw
*[]) {
1564 &disp_cc_mdss_vsync_clk_src
.clkr
.hw
,
1567 .flags
= CLK_SET_RATE_PARENT
,
1568 .ops
= &clk_branch2_ops
,
1573 static struct clk_branch disp_cc_mdss_vsync1_clk
= {
1575 .halt_check
= BRANCH_HALT
,
1577 .enable_reg
= 0xa01c,
1578 .enable_mask
= BIT(0),
1579 .hw
.init
= &(const struct clk_init_data
) {
1580 .name
= "disp_cc_mdss_vsync1_clk",
1581 .parent_hws
= (const struct clk_hw
*[]) {
1582 &disp_cc_mdss_vsync_clk_src
.clkr
.hw
,
1585 .flags
= CLK_SET_RATE_PARENT
,
1586 .ops
= &clk_branch2_ops
,
1591 static struct clk_branch disp_cc_mdss_vsync_clk
= {
1593 .halt_check
= BRANCH_HALT
,
1595 .enable_reg
= 0x8024,
1596 .enable_mask
= BIT(0),
1597 .hw
.init
= &(const struct clk_init_data
) {
1598 .name
= "disp_cc_mdss_vsync_clk",
1599 .parent_hws
= (const struct clk_hw
*[]) {
1600 &disp_cc_mdss_vsync_clk_src
.clkr
.hw
,
1603 .flags
= CLK_SET_RATE_PARENT
,
1604 .ops
= &clk_branch2_ops
,
1609 static struct clk_branch disp_cc_sleep_clk
= {
1611 .halt_check
= BRANCH_HALT
,
1613 .enable_reg
= 0xe074,
1614 .enable_mask
= BIT(0),
1615 .hw
.init
= &(const struct clk_init_data
) {
1616 .name
= "disp_cc_sleep_clk",
1617 .parent_hws
= (const struct clk_hw
*[]) {
1618 &disp_cc_sleep_clk_src
.clkr
.hw
,
1621 .flags
= CLK_SET_RATE_PARENT
,
1622 .ops
= &clk_branch2_ops
,
1627 static struct gdsc mdss_gdsc
= {
1630 .name
= "mdss_gdsc",
1632 .pwrsts
= PWRSTS_OFF_ON
,
1633 .flags
= POLL_CFG_GDSCR
| HW_CTRL
| RETAIN_FF_ENABLE
,
1636 static struct gdsc mdss_int2_gdsc
= {
1639 .name
= "mdss_int2_gdsc",
1641 .pwrsts
= PWRSTS_OFF_ON
,
1642 .flags
= POLL_CFG_GDSCR
| HW_CTRL
| RETAIN_FF_ENABLE
,
1645 static struct clk_regmap
*disp_cc_sm8550_clocks
[] = {
1646 [DISP_CC_MDSS_ACCU_CLK
] = &disp_cc_mdss_accu_clk
.clkr
,
1647 [DISP_CC_MDSS_AHB1_CLK
] = &disp_cc_mdss_ahb1_clk
.clkr
,
1648 [DISP_CC_MDSS_AHB_CLK
] = &disp_cc_mdss_ahb_clk
.clkr
,
1649 [DISP_CC_MDSS_AHB_CLK_SRC
] = &disp_cc_mdss_ahb_clk_src
.clkr
,
1650 [DISP_CC_MDSS_BYTE0_CLK
] = &disp_cc_mdss_byte0_clk
.clkr
,
1651 [DISP_CC_MDSS_BYTE0_CLK_SRC
] = &disp_cc_mdss_byte0_clk_src
.clkr
,
1652 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC
] = &disp_cc_mdss_byte0_div_clk_src
.clkr
,
1653 [DISP_CC_MDSS_BYTE0_INTF_CLK
] = &disp_cc_mdss_byte0_intf_clk
.clkr
,
1654 [DISP_CC_MDSS_BYTE1_CLK
] = &disp_cc_mdss_byte1_clk
.clkr
,
1655 [DISP_CC_MDSS_BYTE1_CLK_SRC
] = &disp_cc_mdss_byte1_clk_src
.clkr
,
1656 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC
] = &disp_cc_mdss_byte1_div_clk_src
.clkr
,
1657 [DISP_CC_MDSS_BYTE1_INTF_CLK
] = &disp_cc_mdss_byte1_intf_clk
.clkr
,
1658 [DISP_CC_MDSS_DPTX0_AUX_CLK
] = &disp_cc_mdss_dptx0_aux_clk
.clkr
,
1659 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC
] = &disp_cc_mdss_dptx0_aux_clk_src
.clkr
,
1660 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK
] = &disp_cc_mdss_dptx0_crypto_clk
.clkr
,
1661 [DISP_CC_MDSS_DPTX0_LINK_CLK
] = &disp_cc_mdss_dptx0_link_clk
.clkr
,
1662 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC
] = &disp_cc_mdss_dptx0_link_clk_src
.clkr
,
1663 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC
] = &disp_cc_mdss_dptx0_link_div_clk_src
.clkr
,
1664 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK
] = &disp_cc_mdss_dptx0_link_intf_clk
.clkr
,
1665 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK
] = &disp_cc_mdss_dptx0_pixel0_clk
.clkr
,
1666 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC
] = &disp_cc_mdss_dptx0_pixel0_clk_src
.clkr
,
1667 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK
] = &disp_cc_mdss_dptx0_pixel1_clk
.clkr
,
1668 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC
] = &disp_cc_mdss_dptx0_pixel1_clk_src
.clkr
,
1669 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK
] =
1670 &disp_cc_mdss_dptx0_usb_router_link_intf_clk
.clkr
,
1671 [DISP_CC_MDSS_DPTX1_AUX_CLK
] = &disp_cc_mdss_dptx1_aux_clk
.clkr
,
1672 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC
] = &disp_cc_mdss_dptx1_aux_clk_src
.clkr
,
1673 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK
] = &disp_cc_mdss_dptx1_crypto_clk
.clkr
,
1674 [DISP_CC_MDSS_DPTX1_LINK_CLK
] = &disp_cc_mdss_dptx1_link_clk
.clkr
,
1675 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC
] = &disp_cc_mdss_dptx1_link_clk_src
.clkr
,
1676 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC
] = &disp_cc_mdss_dptx1_link_div_clk_src
.clkr
,
1677 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK
] = &disp_cc_mdss_dptx1_link_intf_clk
.clkr
,
1678 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK
] = &disp_cc_mdss_dptx1_pixel0_clk
.clkr
,
1679 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC
] = &disp_cc_mdss_dptx1_pixel0_clk_src
.clkr
,
1680 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK
] = &disp_cc_mdss_dptx1_pixel1_clk
.clkr
,
1681 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC
] = &disp_cc_mdss_dptx1_pixel1_clk_src
.clkr
,
1682 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK
] =
1683 &disp_cc_mdss_dptx1_usb_router_link_intf_clk
.clkr
,
1684 [DISP_CC_MDSS_DPTX2_AUX_CLK
] = &disp_cc_mdss_dptx2_aux_clk
.clkr
,
1685 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC
] = &disp_cc_mdss_dptx2_aux_clk_src
.clkr
,
1686 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK
] = &disp_cc_mdss_dptx2_crypto_clk
.clkr
,
1687 [DISP_CC_MDSS_DPTX2_LINK_CLK
] = &disp_cc_mdss_dptx2_link_clk
.clkr
,
1688 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC
] = &disp_cc_mdss_dptx2_link_clk_src
.clkr
,
1689 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC
] = &disp_cc_mdss_dptx2_link_div_clk_src
.clkr
,
1690 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK
] = &disp_cc_mdss_dptx2_link_intf_clk
.clkr
,
1691 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK
] = &disp_cc_mdss_dptx2_pixel0_clk
.clkr
,
1692 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC
] = &disp_cc_mdss_dptx2_pixel0_clk_src
.clkr
,
1693 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK
] = &disp_cc_mdss_dptx2_pixel1_clk
.clkr
,
1694 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC
] = &disp_cc_mdss_dptx2_pixel1_clk_src
.clkr
,
1695 [DISP_CC_MDSS_DPTX3_AUX_CLK
] = &disp_cc_mdss_dptx3_aux_clk
.clkr
,
1696 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC
] = &disp_cc_mdss_dptx3_aux_clk_src
.clkr
,
1697 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK
] = &disp_cc_mdss_dptx3_crypto_clk
.clkr
,
1698 [DISP_CC_MDSS_DPTX3_LINK_CLK
] = &disp_cc_mdss_dptx3_link_clk
.clkr
,
1699 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC
] = &disp_cc_mdss_dptx3_link_clk_src
.clkr
,
1700 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC
] = &disp_cc_mdss_dptx3_link_div_clk_src
.clkr
,
1701 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK
] = &disp_cc_mdss_dptx3_link_intf_clk
.clkr
,
1702 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK
] = &disp_cc_mdss_dptx3_pixel0_clk
.clkr
,
1703 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC
] = &disp_cc_mdss_dptx3_pixel0_clk_src
.clkr
,
1704 [DISP_CC_MDSS_ESC0_CLK
] = &disp_cc_mdss_esc0_clk
.clkr
,
1705 [DISP_CC_MDSS_ESC0_CLK_SRC
] = &disp_cc_mdss_esc0_clk_src
.clkr
,
1706 [DISP_CC_MDSS_ESC1_CLK
] = &disp_cc_mdss_esc1_clk
.clkr
,
1707 [DISP_CC_MDSS_ESC1_CLK_SRC
] = &disp_cc_mdss_esc1_clk_src
.clkr
,
1708 [DISP_CC_MDSS_MDP1_CLK
] = &disp_cc_mdss_mdp1_clk
.clkr
,
1709 [DISP_CC_MDSS_MDP_CLK
] = &disp_cc_mdss_mdp_clk
.clkr
,
1710 [DISP_CC_MDSS_MDP_CLK_SRC
] = &disp_cc_mdss_mdp_clk_src
.clkr
,
1711 [DISP_CC_MDSS_MDP_LUT1_CLK
] = &disp_cc_mdss_mdp_lut1_clk
.clkr
,
1712 [DISP_CC_MDSS_MDP_LUT_CLK
] = &disp_cc_mdss_mdp_lut_clk
.clkr
,
1713 [DISP_CC_MDSS_NON_GDSC_AHB_CLK
] = &disp_cc_mdss_non_gdsc_ahb_clk
.clkr
,
1714 [DISP_CC_MDSS_PCLK0_CLK
] = &disp_cc_mdss_pclk0_clk
.clkr
,
1715 [DISP_CC_MDSS_PCLK0_CLK_SRC
] = &disp_cc_mdss_pclk0_clk_src
.clkr
,
1716 [DISP_CC_MDSS_PCLK1_CLK
] = &disp_cc_mdss_pclk1_clk
.clkr
,
1717 [DISP_CC_MDSS_PCLK1_CLK_SRC
] = &disp_cc_mdss_pclk1_clk_src
.clkr
,
1718 [DISP_CC_MDSS_RSCC_AHB_CLK
] = &disp_cc_mdss_rscc_ahb_clk
.clkr
,
1719 [DISP_CC_MDSS_RSCC_VSYNC_CLK
] = &disp_cc_mdss_rscc_vsync_clk
.clkr
,
1720 [DISP_CC_MDSS_VSYNC1_CLK
] = &disp_cc_mdss_vsync1_clk
.clkr
,
1721 [DISP_CC_MDSS_VSYNC_CLK
] = &disp_cc_mdss_vsync_clk
.clkr
,
1722 [DISP_CC_MDSS_VSYNC_CLK_SRC
] = &disp_cc_mdss_vsync_clk_src
.clkr
,
1723 [DISP_CC_PLL0
] = &disp_cc_pll0
.clkr
,
1724 [DISP_CC_PLL1
] = &disp_cc_pll1
.clkr
,
1725 [DISP_CC_SLEEP_CLK
] = &disp_cc_sleep_clk
.clkr
,
1726 [DISP_CC_SLEEP_CLK_SRC
] = &disp_cc_sleep_clk_src
.clkr
,
1727 [DISP_CC_XO_CLK_SRC
] = &disp_cc_xo_clk_src
.clkr
,
1730 static const struct qcom_reset_map disp_cc_sm8550_resets
[] = {
1731 [DISP_CC_MDSS_CORE_BCR
] = { 0x8000 },
1732 [DISP_CC_MDSS_CORE_INT2_BCR
] = { 0xa000 },
1733 [DISP_CC_MDSS_RSCC_BCR
] = { 0xc000 },
1736 static struct gdsc
*disp_cc_sm8550_gdscs
[] = {
1737 [MDSS_GDSC
] = &mdss_gdsc
,
1738 [MDSS_INT2_GDSC
] = &mdss_int2_gdsc
,
1741 static const struct regmap_config disp_cc_sm8550_regmap_config
= {
1745 .max_register
= 0x11008,
1749 static struct qcom_cc_desc disp_cc_sm8550_desc
= {
1750 .config
= &disp_cc_sm8550_regmap_config
,
1751 .clks
= disp_cc_sm8550_clocks
,
1752 .num_clks
= ARRAY_SIZE(disp_cc_sm8550_clocks
),
1753 .resets
= disp_cc_sm8550_resets
,
1754 .num_resets
= ARRAY_SIZE(disp_cc_sm8550_resets
),
1755 .gdscs
= disp_cc_sm8550_gdscs
,
1756 .num_gdscs
= ARRAY_SIZE(disp_cc_sm8550_gdscs
),
1759 static const struct of_device_id disp_cc_sm8550_match_table
[] = {
1760 { .compatible
= "qcom,sar2130p-dispcc" },
1761 { .compatible
= "qcom,sm8550-dispcc" },
1762 { .compatible
= "qcom,sm8650-dispcc" },
1765 MODULE_DEVICE_TABLE(of
, disp_cc_sm8550_match_table
);
1767 static int disp_cc_sm8550_probe(struct platform_device
*pdev
)
1769 struct regmap
*regmap
;
1772 ret
= devm_pm_runtime_enable(&pdev
->dev
);
1776 ret
= pm_runtime_resume_and_get(&pdev
->dev
);
1780 regmap
= qcom_cc_map(pdev
, &disp_cc_sm8550_desc
);
1781 if (IS_ERR(regmap
)) {
1782 ret
= PTR_ERR(regmap
);
1786 if (of_device_is_compatible(pdev
->dev
.of_node
, "qcom,sm8650-dispcc")) {
1787 lucid_ole_vco
[0].max_freq
= 2100000000;
1788 disp_cc_mdss_mdp_clk_src
.freq_tbl
= ftbl_disp_cc_mdss_mdp_clk_src_sm8650
;
1789 disp_cc_mdss_dptx1_usb_router_link_intf_clk
.clkr
.hw
.init
->parent_hws
[0] =
1790 &disp_cc_mdss_dptx1_link_div_clk_src
.clkr
.hw
;
1791 } else if (of_device_is_compatible(pdev
->dev
.of_node
, "qcom,sar2130p-dispcc")) {
1792 disp_cc_pll0_config
.l
= 0x1f;
1793 disp_cc_pll0_config
.alpha
= 0x4000;
1794 disp_cc_pll0_config
.user_ctl_val
= 0x1;
1795 disp_cc_pll1_config
.user_ctl_val
= 0x1;
1796 disp_cc_mdss_mdp_clk_src
.freq_tbl
= ftbl_disp_cc_mdss_mdp_clk_src_sar2130p
;
1799 clk_lucid_ole_pll_configure(&disp_cc_pll0
, regmap
, &disp_cc_pll0_config
);
1800 clk_lucid_ole_pll_configure(&disp_cc_pll1
, regmap
, &disp_cc_pll1_config
);
1802 /* Enable clock gating for MDP clocks */
1803 regmap_update_bits(regmap
, DISP_CC_MISC_CMD
, 0x10, 0x10);
1805 /* Keep some clocks always-on */
1806 qcom_branch_set_clk_en(regmap
, 0xe054); /* DISP_CC_XO_CLK */
1808 ret
= qcom_cc_really_probe(&pdev
->dev
, &disp_cc_sm8550_desc
, regmap
);
1812 pm_runtime_put(&pdev
->dev
);
1817 pm_runtime_put_sync(&pdev
->dev
);
1822 static struct platform_driver disp_cc_sm8550_driver
= {
1823 .probe
= disp_cc_sm8550_probe
,
1825 .name
= "disp_cc-sm8550",
1826 .of_match_table
= disp_cc_sm8550_match_table
,
1830 module_platform_driver(disp_cc_sm8550_driver
);
1832 MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650 Driver");
1833 MODULE_LICENSE("GPL");