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drm/panel: panel-himax-hx83102: support for csot-pna957qt1-1 MIPI-DSI panel
[drm/drm-misc.git] / drivers / clk / renesas / r9a06g032-clocks.c
blobdcda19318b2a9a73e01b66d33124d3485450c511
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R9A06G032 clock driver
4 *
5 * Copyright (C) 2018 Renesas Electronics Europe Limited
6 *
7 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/math64.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_clock.h>
22 #include <linux/pm_domain.h>
23 #include <linux/reboot.h>
24 #include <linux/slab.h>
25 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
26 #include <linux/spinlock.h>
27 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
28
29 #define R9A06G032_SYSCTRL_USB 0x00
30 #define R9A06G032_SYSCTRL_USB_H2MODE BIT(1)
31 #define R9A06G032_SYSCTRL_DMAMUX 0xA0
32
33 #define R9A06G032_SYSCTRL_RSTEN 0x120
34 #define R9A06G032_SYSCTRL_RSTEN_MRESET_EN BIT(0)
35 #define R9A06G032_SYSCTRL_RSTCTRL 0x198
36 /* These work for both reset registers */
37 #define R9A06G032_SYSCTRL_SWRST BIT(6)
38 #define R9A06G032_SYSCTRL_WDA7RST_1 BIT(2)
39 #define R9A06G032_SYSCTRL_WDA7RST_0 BIT(1)
40
41 /**
42 * struct regbit - describe one bit in a register
43 * @reg: offset of register relative to base address,
44 * expressed in units of 32-bit words (not bytes),
45 * @bit: which bit (0 to 31) in the register
46 *
47 * This structure is used to compactly encode the location
48 * of a single bit in a register. Five bits are needed to
49 * encode the bit number. With uint16_t data type, this
50 * leaves 11 bits to encode a register offset up to 2047.
51 *
52 * Since registers are aligned on 32-bit boundaries, the
53 * offset will be specified in 32-bit words rather than bytes.
54 * This allows encoding an offset up to 0x1FFC (8188) bytes.
55 *
56 * Helper macro RB() takes care of converting the register
57 * offset from bytes to 32-bit words.
58 */
59 struct regbit {
60 u16 bit:5;
61 u16 reg:11;
62 };
63
64 #define RB(_reg, _bit) ((struct regbit) { \
65 .reg = (_reg) / 4, \
66 .bit = (_bit) \
67 })
68
69 /**
70 * struct r9a06g032_gate - clock-related control bits
71 * @gate: clock enable/disable
72 * @reset: clock module reset (active low)
73 * @ready: enables NoC forwarding of read/write requests to device,
74 * (eg. device is ready to handle read/write requests)
75 * @midle: request to idle the NoC interconnect
76 *
77 * Each of these fields describes a single bit in a register,
78 * which controls some aspect of clock gating. The @gate field
79 * is mandatory, this one enables/disables the clock. The
80 * other fields are optional, with zero indicating "not used".
81 *
82 * In most cases there is a @reset bit which needs to be
83 * de-asserted to bring the module out of reset.
84 *
85 * Modules may also need to signal when they are @ready to
86 * handle requests (read/writes) from the NoC interconnect.
87 *
88 * Similarly, the @midle bit is used to idle the master.
89 */
90 struct r9a06g032_gate {
91 struct regbit gate, reset, ready, midle;
92 /* Unused fields omitted to save space */
93 /* struct regbit scon, mirack, mistat */;
94 };
95
96 enum gate_type {
97 K_GATE = 0, /* gate which enable/disable */
98 K_FFC, /* fixed factor clock */
99 K_DIV, /* divisor */
100 K_BITSEL, /* special for UARTs */
101 K_DUALGATE /* special for UARTs */
102 };
103
104 /**
105 * struct r9a06g032_clkdesc - describe a single clock
106 * @name: string describing this clock
107 * @managed: boolean indicating if this clock should be
108 * started/stopped as part of power management
109 * @type: see enum @gate_type
110 * @index: the ID of this clock element
111 * @source: the ID+1 of the parent clock element.
112 * Root clock uses ID of ~0 (PARENT_ID);
113 * @gate: clock enable/disable
114 * @div: substructure for clock divider
115 * @div.min: smallest permitted clock divider
116 * @div.max: largest permitted clock divider
117 * @div.reg: clock divider register offset, in 32-bit words
118 * @div.table: optional list of fixed clock divider values;
119 * must be in ascending order, zero for unused
120 * @ffc: substructure for fixed-factor clocks
121 * @ffc.div: divisor for fixed-factor clock
122 * @ffc.mul: multiplier for fixed-factor clock
123 * @dual: substructure for dual clock gates
124 * @dual.group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7
125 * @dual.sel: select either g1/r1 or g2/r2 as clock source
126 * @dual.g1: 1st source gate (clock enable/disable)
127 * @dual.r1: 1st source reset (module reset)
128 * @dual.g2: 2nd source gate (clock enable/disable)
129 * @dual.r2: 2nd source reset (module reset)
130 *
131 * Describes a single element in the clock tree hierarchy.
132 * As there are quite a large number of clock elements, this
133 * structure is packed tightly to conserve space.
134 */
135 struct r9a06g032_clkdesc {
136 const char *name;
137 uint32_t managed:1;
138 enum gate_type type:3;
139 uint32_t index:8;
140 uint32_t source:8; /* source index + 1 (0 == none) */
141 union {
142 /* type = K_GATE */
143 struct r9a06g032_gate gate;
144 /* type = K_DIV */
145 struct {
146 unsigned int min:10, max:10, reg:10;
147 u16 table[4];
148 } div;
149 /* type = K_FFC */
150 struct {
151 u16 div, mul;
152 } ffc;
153 /* type = K_DUALGATE */
154 struct {
155 uint16_t group:1;
156 struct regbit sel, g1, r1, g2, r2;
157 } dual;
158 };
159 };
160
161 /*
162 * The last three arguments are not currently used,
163 * but are kept in the r9a06g032_clocks table below.
164 */
165 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
166 .gate = _clk, \
167 .reset = _rst, \
168 .ready = _rdy, \
169 .midle = _midle, \
170 /* .scon = _scon, */ \
171 /* .mirack = _mirack, */ \
172 /* .mistat = _mistat */ \
173 }
174 #define D_GATE(_idx, _n, _src, ...) { \
175 .type = K_GATE, \
176 .index = R9A06G032_##_idx, \
177 .source = 1 + R9A06G032_##_src, \
178 .name = _n, \
179 .gate = I_GATE(__VA_ARGS__) \
180 }
181 #define D_MODULE(_idx, _n, _src, ...) { \
182 .type = K_GATE, \
183 .index = R9A06G032_##_idx, \
184 .source = 1 + R9A06G032_##_src, \
185 .name = _n, \
186 .managed = 1, \
187 .gate = I_GATE(__VA_ARGS__) \
188 }
189 #define D_ROOT(_idx, _n, _mul, _div) { \
190 .type = K_FFC, \
191 .index = R9A06G032_##_idx, \
192 .name = _n, \
193 .ffc.div = _div, \
194 .ffc.mul = _mul \
195 }
196 #define D_FFC(_idx, _n, _src, _div) { \
197 .type = K_FFC, \
198 .index = R9A06G032_##_idx, \
199 .source = 1 + R9A06G032_##_src, \
200 .name = _n, \
201 .ffc.div = _div, \
202 .ffc.mul = 1 \
203 }
204 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
205 .type = K_DIV, \
206 .index = R9A06G032_##_idx, \
207 .source = 1 + R9A06G032_##_src, \
208 .name = _n, \
209 .div.reg = _reg, \
210 .div.min = _min, \
211 .div.max = _max, \
212 .div.table = { __VA_ARGS__ } \
213 }
214 #define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
215 .type = K_DUALGATE, \
216 .index = R9A06G032_##_idx, \
217 .source = 1 + R9A06G032_##_src, \
218 .name = _n, \
219 .dual = { \
220 .group = _g, \
221 .g1 = _g1, \
222 .r1 = _r1, \
223 .g2 = _g2, \
224 .r2 = _r2 \
225 }, \
226 }
227
228 /* Internal clock IDs */
229 #define R9A06G032_CLKOUT 0
230 #define R9A06G032_CLKOUT_D10 2
231 #define R9A06G032_CLKOUT_D16 3
232 #define R9A06G032_CLKOUT_D160 4
233 #define R9A06G032_CLKOUT_D1OR2 5
234 #define R9A06G032_CLKOUT_D20 6
235 #define R9A06G032_CLKOUT_D40 7
236 #define R9A06G032_CLKOUT_D5 8
237 #define R9A06G032_CLKOUT_D8 9
238 #define R9A06G032_DIV_ADC 10
239 #define R9A06G032_DIV_I2C 11
240 #define R9A06G032_DIV_NAND 12
241 #define R9A06G032_DIV_P1_PG 13
242 #define R9A06G032_DIV_P2_PG 14
243 #define R9A06G032_DIV_P3_PG 15
244 #define R9A06G032_DIV_P4_PG 16
245 #define R9A06G032_DIV_P5_PG 17
246 #define R9A06G032_DIV_P6_PG 18
247 #define R9A06G032_DIV_QSPI0 19
248 #define R9A06G032_DIV_QSPI1 20
249 #define R9A06G032_DIV_REF_SYNC 21
250 #define R9A06G032_DIV_SDIO0 22
251 #define R9A06G032_DIV_SDIO1 23
252 #define R9A06G032_DIV_SWITCH 24
253 #define R9A06G032_DIV_UART 25
254 #define R9A06G032_DIV_MOTOR 64
255 #define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78
256 #define R9A06G032_CLK_ECAT100_D4 79
257 #define R9A06G032_CLK_HSR100_D2 80
258 #define R9A06G032_CLK_REF_SYNC_D4 81
259 #define R9A06G032_CLK_REF_SYNC_D8 82
260 #define R9A06G032_CLK_SERCOS100_D2 83
261 #define R9A06G032_DIV_CA7 84
262
263 #define R9A06G032_UART_GROUP_012 154
264 #define R9A06G032_UART_GROUP_34567 155
265
266 #define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1)
267
268 static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
269 D_ROOT(CLKOUT, "clkout", 25, 1),
270 D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
271 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
272 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
273 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
274 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
275 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
276 D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
277 D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
278 D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
279 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
280 D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
281 D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
282 D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
283 D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
284 D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
285 D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
286 D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
287 D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
288 D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
289 D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
290 D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
291 D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
292 D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
293 D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
294 D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
295 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),
296 RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),
297 RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),
298 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),
299 RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),
300 RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),
301 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),
302 RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),
303 RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),
304 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),
305 RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),
306 RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),
307 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),
308 RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),
309 RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),
310 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),
311 RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),
312 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
313 D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),
314 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
315 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
316 D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),
317 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
318 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
319 D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
320 RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),
321 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
322 D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
323 RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),
324 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
325 D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),
326 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
327 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
328 D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),
329 RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),
330 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
331 D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),
332 RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),
333 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
334 D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),
335 RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),
336 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
337 D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),
338 RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),
339 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
340 D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),
341 RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),
342 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
343 D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),
344 RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),
345 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
346 D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),
347 RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),
348 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
349 D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),
350 RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),
351 RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),
352 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),
353 RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),
354 RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),
355 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),
356 RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),
357 RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),
358 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),
359 RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),
360 RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),
361 D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),
362 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
363 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
364 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),
365 RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),
366 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
367 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),
368 RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
369 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
370 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),
371 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
372 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
373 D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),
374 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
375 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
376 D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),
377 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
378 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
379 D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),
380 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
381 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
382 D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),
383 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
384 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
385 D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),
386 RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),
387 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
388 D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
389 RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),
390 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
391 D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
392 RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),
393 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
394 D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),
395 RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),
396 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
397 D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),
398 RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),
399 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
400 D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),
401 RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),
402 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
403 D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),
404 RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),
405 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
406 D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),
407 RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),
408 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
409 D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
410 D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),
411 RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),
412 RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),
413 D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),
414 RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),
415 RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),
416 D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),
417 RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),
418 RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),
419 D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),
420 RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),
421 RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),
422 D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),
423 RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),
424 RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),
425 D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),
426 RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),
427 RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),
428 D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),
429 RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),
430 RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),
431 D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),
432 RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),
433 RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),
434 D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),
435 RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),
436 RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),
437 D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),
438 RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),
439 RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),
440 D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),
441 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
442 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
443 D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
444 RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),
445 RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),
446 D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
447 RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),
448 RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),
449 D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
450 D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
451 D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
452 D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
453 D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
454 D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
455 D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
456 D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
457 RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),
458 RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),
459 D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
460 RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),
461 RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),
462 D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),
463 RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),
464 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
465 D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),
466 RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),
467 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
468 D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
469 RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),
470 RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),
471 D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),
472 RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),
473 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
474 D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),
475 RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),
476 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
477 D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
478 D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),
479 RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),
480 RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),
481 D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),
482 RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),
483 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
484 D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),
485 RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),
486 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
487 D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),
488 RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
489 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
490 D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),
491 RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),
492 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
493 D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),
494 RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),
495 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
496 D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),
497 RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),
498 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
499 D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),
500 RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),
501 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
502 D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),
503 RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),
504 RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),
505 D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),
506 RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),
507 RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),
508 D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),
509 RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),
510 RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),
511 D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),
512 RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),
513 RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),
514 D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),
515 RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),
516 RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),
517 D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),
518 RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),
519 RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),
520 D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),
521 RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),
522 RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),
523 D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),
524 RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),
525 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
526 D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),
527 RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),
528 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
529 D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),
530 RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),
531 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
532 D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),
533 RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),
534 RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),
535 D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),
536 RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),
537 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
538 D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),
539 RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),
540 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
541 D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),
542 RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),
543 RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),
544 D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),
545 RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),
546 RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),
547 D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),
548 RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),
549 RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),
550 D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),
551 RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),
552 RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),
553 D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),
554 RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),
555 RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),
556 D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),
557 RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),
558 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
559 D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),
560 RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),
561 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
562 D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),
563 RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),
564 RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),
565 D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),
566 RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),
567 RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),
568 D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),
569 RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),
570 RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),
571 D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),
572 RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),
573 RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),
574 D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),
575 RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),
576 RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),
577 D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),
578 RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),
579 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
580 D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
581 RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),
582 RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),
583 D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
584 RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),
585 RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),
586 D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),
587 RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),
588 RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),
589 D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),
590 RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),
591 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
592 D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),
593 RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),
594 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
595 D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),
596 RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),
597 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
598 D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),
599 RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),
600 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
601 D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),
602 RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),
603 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
604 D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),
605 RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),
606 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
607 D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),
608 RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),
609 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
610 D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),
611 RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),
612 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
613 D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),
614 RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),
615 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
616 D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),
617 RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),
618 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
619 D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),
620 RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),
621 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
622 D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),
623 RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),
624 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
625 D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),
626 RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),
627 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
628 D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),
629 RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),
630 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
631 D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),
632 RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),
633 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
634 D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),
635 RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),
636 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
637 /*
638 * These are not hardware clocks, but are needed to handle the special
639 * case where we have a 'selector bit' that doesn't just change the
640 * parent for a clock, but also the gate it's supposed to use.
641 */
642 {
643 .index = R9A06G032_UART_GROUP_012,
644 .name = "uart_group_012",
645 .type = K_BITSEL,
646 .source = 1 + R9A06G032_DIV_UART,
647 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
648 .dual.sel = RB(0x34, 30),
649 .dual.group = 0,
650 },
651 {
652 .index = R9A06G032_UART_GROUP_34567,
653 .name = "uart_group_34567",
654 .type = K_BITSEL,
655 .source = 1 + R9A06G032_DIV_P2_PG,
656 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
657 .dual.sel = RB(0xec, 24),
658 .dual.group = 1,
659 },
660 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0,
661 RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),
662 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0,
663 RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),
664 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0,
665 RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),
666 D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1,
667 RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),
668 D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1,
669 RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),
670 D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1,
671 RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),
672 D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1,
673 RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),
674 D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1,
675 RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),
676 };
677
678 struct r9a06g032_priv {
679 struct clk_onecell_data data;
680 spinlock_t lock; /* protects concurrent access to gates */
681 void __iomem *reg;
682 };
683
684 static struct r9a06g032_priv *sysctrl_priv;
685
686 /* Exported helper to access the DMAMUX register */
687 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
688 {
689 unsigned long flags;
690 u32 dmamux;
691
692 if (!sysctrl_priv)
693 return -EPROBE_DEFER;
694
695 spin_lock_irqsave(&sysctrl_priv->lock, flags);
696
697 dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
698 dmamux &= ~mask;
699 dmamux |= val & mask;
700 writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
701
702 spin_unlock_irqrestore(&sysctrl_priv->lock, flags);
703
704 return 0;
705 }
706 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
707
708 static void clk_rdesc_set(struct r9a06g032_priv *clocks,
709 struct regbit rb, unsigned int on)
710 {
711 u32 __iomem *reg = clocks->reg + (rb.reg * 4);
712 u32 val;
713
714 if (!rb.reg && !rb.bit)
715 return;
716
717 val = readl(reg);
718 val = (val & ~BIT(rb.bit)) | ((!!on) << rb.bit);
719 writel(val, reg);
720 }
721
722 static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb)
723 {
724 u32 __iomem *reg = clocks->reg + (rb.reg * 4);
725 u32 val = readl(reg);
726
727 return !!(val & BIT(rb.bit));
728 }
729
730 /*
731 * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
732 * clock gate framework as the gates on the R9A06G032 have a special enabling
733 * sequence, therefore we use this little proxy.
734 */
735 struct r9a06g032_clk_gate {
736 struct clk_hw hw;
737 struct r9a06g032_priv *clocks;
738 u16 index;
739
740 struct r9a06g032_gate gate;
741 };
742
743 #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
744
745 static int create_add_module_clock(struct of_phandle_args *clkspec,
746 struct device *dev)
747 {
748 struct clk *clk;
749 int error;
750
751 clk = of_clk_get_from_provider(clkspec);
752 if (IS_ERR(clk))
753 return PTR_ERR(clk);
754
755 error = pm_clk_create(dev);
756 if (error) {
757 clk_put(clk);
758 return error;
759 }
760
761 error = pm_clk_add_clk(dev, clk);
762 if (error) {
763 pm_clk_destroy(dev);
764 clk_put(clk);
765 }
766
767 return error;
768 }
769
770 static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
771 struct device *dev)
772 {
773 struct device_node *np = dev->of_node;
774 struct of_phandle_args clkspec;
775 int i = 0;
776 int error;
777 int index;
778
779 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,
780 &clkspec)) {
781 if (clkspec.np != pd->dev.of_node)
782 continue;
783
784 index = clkspec.args[0];
785 if (index < R9A06G032_CLOCK_COUNT &&
786 r9a06g032_clocks[index].managed) {
787 error = create_add_module_clock(&clkspec, dev);
788 of_node_put(clkspec.np);
789 if (error)
790 return error;
791 }
792 }
793
794 return 0;
795 }
796
797 static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev)
798 {
799 if (!pm_clk_no_clocks(dev))
800 pm_clk_destroy(dev);
801 }
802
803 static int r9a06g032_add_clk_domain(struct device *dev)
804 {
805 struct device_node *np = dev->of_node;
806 struct generic_pm_domain *pd;
807
808 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
809 if (!pd)
810 return -ENOMEM;
811
812 pd->name = np->name;
813 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
814 GENPD_FLAG_ACTIVE_WAKEUP;
815 pd->attach_dev = r9a06g032_attach_dev;
816 pd->detach_dev = r9a06g032_detach_dev;
817 pm_genpd_init(pd, &pm_domain_always_on_gov, false);
818
819 of_genpd_add_provider_simple(np, pd);
820 return 0;
821 }
822
823 static void
824 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
825 struct r9a06g032_gate *g, int on)
826 {
827 unsigned long flags;
828
829 WARN_ON(!g->gate.reg && !g->gate.bit);
830
831 spin_lock_irqsave(&clocks->lock, flags);
832 clk_rdesc_set(clocks, g->gate, on);
833 /* De-assert reset */
834 clk_rdesc_set(clocks, g->reset, 1);
835 spin_unlock_irqrestore(&clocks->lock, flags);
836
837 /* Hardware manual recommends 5us delay after enabling clock & reset */
838 udelay(5);
839
840 /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
841 * associated SLVRDY bit in the System Controller that needs to be set
842 * so that the FlexWAY bus fabric passes on the read/write requests.
843 */
844 spin_lock_irqsave(&clocks->lock, flags);
845 clk_rdesc_set(clocks, g->ready, on);
846 /* Clear 'Master Idle Request' bit */
847 clk_rdesc_set(clocks, g->midle, !on);
848 spin_unlock_irqrestore(&clocks->lock, flags);
849
850 /* Note: We don't wait for FlexWAY Socket Connection signal */
851 }
852
853 static int r9a06g032_clk_gate_enable(struct clk_hw *hw)
854 {
855 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
856
857 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
858 return 0;
859 }
860
861 static void r9a06g032_clk_gate_disable(struct clk_hw *hw)
862 {
863 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
864
865 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
866 }
867
868 static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
869 {
870 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
871
872 /* if clock is in reset, the gate might be on, and still not 'be' on */
873 if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
874 return 0;
875
876 return clk_rdesc_get(g->clocks, g->gate.gate);
877 }
878
879 static const struct clk_ops r9a06g032_clk_gate_ops = {
880 .enable = r9a06g032_clk_gate_enable,
881 .disable = r9a06g032_clk_gate_disable,
882 .is_enabled = r9a06g032_clk_gate_is_enabled,
883 };
884
885 static struct clk *
886 r9a06g032_register_gate(struct r9a06g032_priv *clocks,
887 const char *parent_name,
888 const struct r9a06g032_clkdesc *desc)
889 {
890 struct clk *clk;
891 struct r9a06g032_clk_gate *g;
892 struct clk_init_data init = {};
893
894 g = kzalloc(sizeof(*g), GFP_KERNEL);
895 if (!g)
896 return NULL;
897
898 init.name = desc->name;
899 init.ops = &r9a06g032_clk_gate_ops;
900 init.flags = CLK_SET_RATE_PARENT;
901 init.parent_names = parent_name ? &parent_name : NULL;
902 init.num_parents = parent_name ? 1 : 0;
903
904 g->clocks = clocks;
905 g->index = desc->index;
906 g->gate = desc->gate;
907 g->hw.init = &init;
908
909 /*
910 * important here, some clocks are already in use by the CM3, we
911 * have to assume they are not Linux's to play with and try to disable
912 * at the end of the boot!
913 */
914 if (r9a06g032_clk_gate_is_enabled(&g->hw)) {
915 init.flags |= CLK_IS_CRITICAL;
916 pr_debug("%s was enabled, making read-only\n", desc->name);
917 }
918
919 clk = clk_register(NULL, &g->hw);
920 if (IS_ERR(clk)) {
921 kfree(g);
922 return NULL;
923 }
924 return clk;
925 }
926
927 struct r9a06g032_clk_div {
928 struct clk_hw hw;
929 struct r9a06g032_priv *clocks;
930 u16 index;
931 u16 reg;
932 u16 min, max;
933 u8 table_size;
934 u16 table[8]; /* we know there are no more than 8 */
935 };
936
937 #define to_r9a06g032_div(_hw) \
938 container_of(_hw, struct r9a06g032_clk_div, hw)
939
940 static unsigned long
941 r9a06g032_div_recalc_rate(struct clk_hw *hw,
942 unsigned long parent_rate)
943 {
944 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
945 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
946 u32 div = readl(reg);
947
948 if (div < clk->min)
949 div = clk->min;
950 else if (div > clk->max)
951 div = clk->max;
952 return DIV_ROUND_UP(parent_rate, div);
953 }
954
955 /*
956 * Attempts to find a value that is in range of min,max,
957 * and if a table of set dividers was specified for this
958 * register, try to find the fixed divider that is the closest
959 * to the target frequency
960 */
961 static long
962 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
963 unsigned long rate, unsigned long prate)
964 {
965 /* + 1 to cope with rates that have the remainder dropped */
966 u32 div = DIV_ROUND_UP(prate, rate + 1);
967 int i;
968
969 if (div <= clk->min)
970 return clk->min;
971 if (div >= clk->max)
972 return clk->max;
973
974 for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
975 if (div >= clk->table[i] && div <= clk->table[i + 1]) {
976 unsigned long m = rate -
977 DIV_ROUND_UP(prate, clk->table[i]);
978 unsigned long p =
979 DIV_ROUND_UP(prate, clk->table[i + 1]) -
980 rate;
981 /*
982 * select the divider that generates
983 * the value closest to the ideal frequency
984 */
985 div = p >= m ? clk->table[i] : clk->table[i + 1];
986 return div;
987 }
988 }
989 return div;
990 }
991
992 static int
993 r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
994 {
995 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
996 u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
997
998 pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
999 hw->clk, req->rate, req->best_parent_rate, div);
1000 pr_devel(" min %d (%ld) max %d (%ld)\n",
1001 clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
1002 clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
1003
1004 div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
1005 /*
1006 * this is a hack. Currently the serial driver asks for a clock rate
1007 * that is 16 times the baud rate -- and that is wildly outside the
1008 * range of the UART divider, somehow there is no provision for that
1009 * case of 'let the divider as is if outside range'.
1010 * The serial driver *shouldn't* play with these clocks anyway, there's
1011 * several uarts attached to this divider, and changing this impacts
1012 * everyone.
1013 */
1014 if (clk->index == R9A06G032_DIV_UART ||
1015 clk->index == R9A06G032_DIV_P2_PG) {
1016 pr_devel("%s div uart hack!\n", __func__);
1017 req->rate = clk_get_rate(hw->clk);
1018 return 0;
1019 }
1020 req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
1021 pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
1022 req->best_parent_rate, div, req->rate);
1023 return 0;
1024 }
1025
1026 static int
1027 r9a06g032_div_set_rate(struct clk_hw *hw,
1028 unsigned long rate, unsigned long parent_rate)
1029 {
1030 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
1031 /* + 1 to cope with rates that have the remainder dropped */
1032 u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
1033 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
1034
1035 pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
1036 rate, parent_rate, div);
1037
1038 /*
1039 * Need to write the bit 31 with the divider value to
1040 * latch it. Technically we should wait until it has been
1041 * cleared too.
1042 * TODO: Find whether this callback is sleepable, in case
1043 * the hardware /does/ require some sort of spinloop here.
1044 */
1045 writel(div | BIT(31), reg);
1046
1047 return 0;
1048 }
1049
1050 static const struct clk_ops r9a06g032_clk_div_ops = {
1051 .recalc_rate = r9a06g032_div_recalc_rate,
1052 .determine_rate = r9a06g032_div_determine_rate,
1053 .set_rate = r9a06g032_div_set_rate,
1054 };
1055
1056 static struct clk *
1057 r9a06g032_register_div(struct r9a06g032_priv *clocks,
1058 const char *parent_name,
1059 const struct r9a06g032_clkdesc *desc)
1060 {
1061 struct r9a06g032_clk_div *div;
1062 struct clk *clk;
1063 struct clk_init_data init = {};
1064 unsigned int i;
1065
1066 div = kzalloc(sizeof(*div), GFP_KERNEL);
1067 if (!div)
1068 return NULL;
1069
1070 init.name = desc->name;
1071 init.ops = &r9a06g032_clk_div_ops;
1072 init.flags = CLK_SET_RATE_PARENT;
1073 init.parent_names = parent_name ? &parent_name : NULL;
1074 init.num_parents = parent_name ? 1 : 0;
1075
1076 div->clocks = clocks;
1077 div->index = desc->index;
1078 div->reg = desc->div.reg;
1079 div->hw.init = &init;
1080 div->min = desc->div.min;
1081 div->max = desc->div.max;
1082 /* populate (optional) divider table fixed values */
1083 for (i = 0; i < ARRAY_SIZE(div->table) &&
1084 i < ARRAY_SIZE(desc->div.table) && desc->div.table[i]; i++) {
1085 div->table[div->table_size++] = desc->div.table[i];
1086 }
1087
1088 clk = clk_register(NULL, &div->hw);
1089 if (IS_ERR(clk)) {
1090 kfree(div);
1091 return NULL;
1092 }
1093 return clk;
1094 }
1095
1096 /*
1097 * This clock provider handles the case of the R9A06G032 where you have
1098 * peripherals that have two potential clock source and two gates, one for
1099 * each of the clock source - the used clock source (for all sub clocks)
1100 * is selected by a single bit.
1101 * That single bit affects all sub-clocks, and therefore needs to change the
1102 * active gate (and turn the others off) and force a recalculation of the rates.
1103 *
1104 * This implements two clock providers, one 'bitselect' that
1105 * handles the switch between both parents, and another 'dualgate'
1106 * that knows which gate to poke at, depending on the parent's bit position.
1107 */
1108 struct r9a06g032_clk_bitsel {
1109 struct clk_hw hw;
1110 struct r9a06g032_priv *clocks;
1111 u16 index;
1112 struct regbit selector; /* selector register + bit */
1113 };
1114
1115 #define to_clk_bitselect(_hw) \
1116 container_of(_hw, struct r9a06g032_clk_bitsel, hw)
1117
1118 static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw)
1119 {
1120 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
1121
1122 return clk_rdesc_get(set->clocks, set->selector);
1123 }
1124
1125 static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index)
1126 {
1127 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
1128
1129 /* a single bit in the register selects one of two parent clocks */
1130 clk_rdesc_set(set->clocks, set->selector, !!index);
1131
1132 return 0;
1133 }
1134
1135 static const struct clk_ops clk_bitselect_ops = {
1136 .determine_rate = clk_hw_determine_rate_no_reparent,
1137 .get_parent = r9a06g032_clk_mux_get_parent,
1138 .set_parent = r9a06g032_clk_mux_set_parent,
1139 };
1140
1141 static struct clk *
1142 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
1143 const char *parent_name,
1144 const struct r9a06g032_clkdesc *desc)
1145 {
1146 struct clk *clk;
1147 struct r9a06g032_clk_bitsel *g;
1148 struct clk_init_data init = {};
1149 const char *names[2];
1150
1151 /* allocate the gate */
1152 g = kzalloc(sizeof(*g), GFP_KERNEL);
1153 if (!g)
1154 return NULL;
1155
1156 names[0] = parent_name;
1157 names[1] = "clk_pll_usb";
1158
1159 init.name = desc->name;
1160 init.ops = &clk_bitselect_ops;
1161 init.flags = CLK_SET_RATE_PARENT;
1162 init.parent_names = names;
1163 init.num_parents = 2;
1164
1165 g->clocks = clocks;
1166 g->index = desc->index;
1167 g->selector = desc->dual.sel;
1168 g->hw.init = &init;
1169
1170 clk = clk_register(NULL, &g->hw);
1171 if (IS_ERR(clk)) {
1172 kfree(g);
1173 return NULL;
1174 }
1175 return clk;
1176 }
1177
1178 struct r9a06g032_clk_dualgate {
1179 struct clk_hw hw;
1180 struct r9a06g032_priv *clocks;
1181 u16 index;
1182 struct regbit selector; /* selector register + bit */
1183 struct r9a06g032_gate gate[2];
1184 };
1185
1186 #define to_clk_dualgate(_hw) \
1187 container_of(_hw, struct r9a06g032_clk_dualgate, hw)
1188
1189 static int
1190 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)
1191 {
1192 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
1193
1194 /* we always turn off the 'other' gate, regardless */
1195 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
1196 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
1197
1198 return 0;
1199 }
1200
1201 static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw)
1202 {
1203 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
1204
1205 r9a06g032_clk_dualgate_setenable(gate, 1);
1206
1207 return 0;
1208 }
1209
1210 static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw)
1211 {
1212 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
1213
1214 r9a06g032_clk_dualgate_setenable(gate, 0);
1215 }
1216
1217 static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw)
1218 {
1219 struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);
1220 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
1221
1222 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
1223 }
1224
1225 static const struct clk_ops r9a06g032_clk_dualgate_ops = {
1226 .enable = r9a06g032_clk_dualgate_enable,
1227 .disable = r9a06g032_clk_dualgate_disable,
1228 .is_enabled = r9a06g032_clk_dualgate_is_enabled,
1229 };
1230
1231 static struct clk *
1232 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
1233 const char *parent_name,
1234 const struct r9a06g032_clkdesc *desc,
1235 struct regbit sel)
1236 {
1237 struct r9a06g032_clk_dualgate *g;
1238 struct clk *clk;
1239 struct clk_init_data init = {};
1240
1241 /* allocate the gate */
1242 g = kzalloc(sizeof(*g), GFP_KERNEL);
1243 if (!g)
1244 return NULL;
1245 g->clocks = clocks;
1246 g->index = desc->index;
1247 g->selector = sel;
1248 g->gate[0].gate = desc->dual.g1;
1249 g->gate[0].reset = desc->dual.r1;
1250 g->gate[1].gate = desc->dual.g2;
1251 g->gate[1].reset = desc->dual.r2;
1252
1253 init.name = desc->name;
1254 init.ops = &r9a06g032_clk_dualgate_ops;
1255 init.flags = CLK_SET_RATE_PARENT;
1256 init.parent_names = &parent_name;
1257 init.num_parents = 1;
1258 g->hw.init = &init;
1259 /*
1260 * important here, some clocks are already in use by the CM3, we
1261 * have to assume they are not Linux's to play with and try to disable
1262 * at the end of the boot!
1263 */
1264 if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {
1265 init.flags |= CLK_IS_CRITICAL;
1266 pr_debug("%s was enabled, making read-only\n", desc->name);
1267 }
1268
1269 clk = clk_register(NULL, &g->hw);
1270 if (IS_ERR(clk)) {
1271 kfree(g);
1272 return NULL;
1273 }
1274 return clk;
1275 }
1276
1277 static void r9a06g032_clocks_del_clk_provider(void *data)
1278 {
1279 of_clk_del_provider(data);
1280 }
1281
1282 static int r9a06g032_restart_handler(struct sys_off_data *data)
1283 {
1284 writel(R9A06G032_SYSCTRL_SWRST, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTCTRL);
1285 return NOTIFY_DONE;
1286 }
1287
1288 static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
1289 {
1290 struct device_node *usbf_np;
1291 u32 usb;
1292
1293 for_each_compatible_node(usbf_np, NULL, "renesas,rzn1-usbf") {
1294 if (of_device_is_available(usbf_np))
1295 break;
1296 }
1297
1298 usb = readl(clocks->reg + R9A06G032_SYSCTRL_USB);
1299 if (usbf_np) {
1300 /* 1 host and 1 device mode */
1301 usb &= ~R9A06G032_SYSCTRL_USB_H2MODE;
1302 of_node_put(usbf_np);
1303 } else {
1304 /* 2 hosts mode */
1305 usb |= R9A06G032_SYSCTRL_USB_H2MODE;
1306 }
1307 writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB);
1308 }
1309
1310 static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
1311 {
1312 struct device *dev = &pdev->dev;
1313 struct device_node *np = dev->of_node;
1314 struct r9a06g032_priv *clocks;
1315 struct clk **clks;
1316 struct clk *mclk;
1317 unsigned int i;
1318 struct regbit uart_group_sel[2];
1319 int error;
1320
1321 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
1322 clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *),
1323 GFP_KERNEL);
1324 if (!clocks || !clks)
1325 return -ENOMEM;
1326
1327 spin_lock_init(&clocks->lock);
1328
1329 clocks->data.clks = clks;
1330 clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
1331
1332 mclk = devm_clk_get(dev, "mclk");
1333 if (IS_ERR(mclk))
1334 return PTR_ERR(mclk);
1335
1336 clocks->reg = of_iomap(np, 0);
1337 if (WARN_ON(!clocks->reg))
1338 return -ENOMEM;
1339
1340 r9a06g032_init_h2mode(clocks);
1341
1342 /* Clear potentially pending resets */
1343 writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
1344 clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
1345 /* Allow software reset */
1346 writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1347 clocks->reg + R9A06G032_SYSCTRL_RSTEN);
1348
1349 error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
1350 r9a06g032_restart_handler, NULL);
1351 if (error)
1352 dev_warn(dev, "couldn't register restart handler (%d)\n", error);
1353
1354 for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
1355 const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
1356 const char *parent_name = d->source ?
1357 __clk_get_name(clocks->data.clks[d->source - 1]) :
1358 __clk_get_name(mclk);
1359 struct clk *clk = NULL;
1360
1361 switch (d->type) {
1362 case K_FFC:
1363 clk = clk_register_fixed_factor(NULL, d->name,
1364 parent_name, 0,
1365 d->ffc.mul,
1366 d->ffc.div);
1367 break;
1368 case K_GATE:
1369 clk = r9a06g032_register_gate(clocks, parent_name, d);
1370 break;
1371 case K_DIV:
1372 clk = r9a06g032_register_div(clocks, parent_name, d);
1373 break;
1374 case K_BITSEL:
1375 /* keep that selector register around */
1376 uart_group_sel[d->dual.group] = d->dual.sel;
1377 clk = r9a06g032_register_bitsel(clocks, parent_name, d);
1378 break;
1379 case K_DUALGATE:
1380 clk = r9a06g032_register_dualgate(clocks, parent_name,
1381 d,
1382 uart_group_sel[d->dual.group]);
1383 break;
1384 }
1385 clocks->data.clks[d->index] = clk;
1386 }
1387 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
1388 if (error)
1389 return error;
1390
1391 error = devm_add_action_or_reset(dev,
1392 r9a06g032_clocks_del_clk_provider, np);
1393 if (error)
1394 return error;
1395
1396 error = r9a06g032_add_clk_domain(dev);
1397 if (error)
1398 return error;
1399
1400 sysctrl_priv = clocks;
1401
1402 error = of_platform_populate(np, NULL, NULL, dev);
1403 if (error)
1404 dev_err(dev, "Failed to populate children (%d)\n", error);
1405
1406 return 0;
1407 }
1408
1409 static const struct of_device_id r9a06g032_match[] = {
1410 { .compatible = "renesas,r9a06g032-sysctrl" },
1411 { }
1412 };
1413
1414 static struct platform_driver r9a06g032_clock_driver = {
1415 .driver = {
1416 .name = "renesas,r9a06g032-sysctrl",
1417 .of_match_table = r9a06g032_match,
1418 },
1419 };
1420
1421 static int __init r9a06g032_clocks_init(void)
1422 {
1423 return platform_driver_probe(&r9a06g032_clock_driver,
1424 r9a06g032_clocks_probe);
1425 }
1426
1427 subsys_initcall(r9a06g032_clocks_init);
Kernel DRM miscellaneous fixes and cross-tree changes