drivers/clk/renesas/rzv2h-cpg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Renesas RZ/V2H(P) Clock Pulse Generator
   4  *
   5  * Copyright (C) 2024 Renesas Electronics Corp.
   6  */
   7
   8 #ifndef __RENESAS_RZV2H_CPG_H__
   9 #define __RENESAS_RZV2H_CPG_H__
  10
  11 #include <linux/bitfield.h>
  12
  13 /**
  14  * struct ddiv - Structure for dynamic switching divider
  15  *
  16  * @offset: register offset
  17  * @shift: position of the divider bit
  18  * @width: width of the divider
  19  * @monbit: monitor bit in CPG_CLKSTATUS0 register
  20  */
  21 struct ddiv {
  22         unsigned int offset:11;
  23         unsigned int shift:4;
  24         unsigned int width:4;
  25         unsigned int monbit:5;
  26 };
  27
  28 #define DDIV_PACK(_offset, _shift, _width, _monbit) \
  29         ((struct ddiv){ \
  30                 .offset = _offset, \
  31                 .shift = _shift, \
  32                 .width = _width, \
  33                 .monbit = _monbit \
  34         })
  35
  36 #define CPG_CDDIV0              (0x400)
  37 #define CPG_CDDIV1              (0x404)
  38 #define CPG_CDDIV3              (0x40C)
  39 #define CPG_CDDIV4              (0x410)
  40
  41 #define CDDIV0_DIVCTL2  DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
  42 #define CDDIV1_DIVCTL0  DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
  43 #define CDDIV1_DIVCTL1  DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
  44 #define CDDIV1_DIVCTL2  DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
  45 #define CDDIV1_DIVCTL3  DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
  46 #define CDDIV3_DIVCTL3  DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
  47 #define CDDIV4_DIVCTL0  DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
  48 #define CDDIV4_DIVCTL1  DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
  49 #define CDDIV4_DIVCTL2  DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
  50
  51 #define BUS_MSTOP_IDX_MASK      GENMASK(31, 16)
  52 #define BUS_MSTOP_BITS_MASK     GENMASK(15, 0)
  53 #define BUS_MSTOP(idx, mask)    (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
  54                                  FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
  55 #define BUS_MSTOP_NONE          GENMASK(31, 0)
  56
  57 /**
  58  * Definitions of CPG Core Clocks
  59  *
  60  * These include:
  61  *   - Clock outputs exported to DT
  62  *   - External input clocks
  63  *   - Internal CPG clocks
  64  */
  65 struct cpg_core_clk {
  66         const char *name;
  67         unsigned int id;
  68         unsigned int parent;
  69         unsigned int div;
  70         unsigned int mult;
  71         unsigned int type;
  72         union {
  73                 unsigned int conf;
  74                 struct ddiv ddiv;
  75         } cfg;
  76         const struct clk_div_table *dtable;
  77         u32 flag;
  78 };
  79
  80 enum clk_types {
  81         /* Generic */
  82         CLK_TYPE_IN,            /* External Clock Input */
  83         CLK_TYPE_FF,            /* Fixed Factor Clock */
  84         CLK_TYPE_PLL,
  85         CLK_TYPE_DDIV,          /* Dynamic Switching Divider */
  86 };
  87
  88 /* BIT(31) indicates if CLK1/2 are accessible or not */
  89 #define PLL_CONF(n)             (BIT(31) | ((n) & ~GENMASK(31, 16)))
  90 #define PLL_CLK_ACCESS(n)       ((n) & BIT(31) ? 1 : 0)
  91 #define PLL_CLK1_OFFSET(n)      ((n) & ~GENMASK(31, 16))
  92 #define PLL_CLK2_OFFSET(n)      (((n) & ~GENMASK(31, 16)) + (0x4))
  93
  94 #define DEF_TYPE(_name, _id, _type...) \
  95         { .name = _name, .id = _id, .type = _type }
  96 #define DEF_BASE(_name, _id, _type, _parent...) \
  97         DEF_TYPE(_name, _id, _type, .parent = _parent)
  98 #define DEF_PLL(_name, _id, _parent, _conf) \
  99         DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)
 100 #define DEF_INPUT(_name, _id) \
 101         DEF_TYPE(_name, _id, CLK_TYPE_IN)
 102 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
 103         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 104 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
 105         DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
 106                 .cfg.ddiv = _ddiv_packed, \
 107                 .parent = _parent, \
 108                 .dtable = _dtable, \
 109                 .flag = CLK_DIVIDER_HIWORD_MASK)
 110
 111 /**
 112  * struct rzv2h_mod_clk - Module Clocks definitions
 113  *
 114  * @name: handle between common and hardware-specific interfaces
 115  * @mstop_data: packed data mstop register offset and mask
 116  * @parent: id of parent clock
 117  * @critical: flag to indicate the clock is critical
 118  * @no_pm: flag to indicate PM is not supported
 119  * @on_index: control register index
 120  * @on_bit: ON bit
 121  * @mon_index: monitor register index
 122  * @mon_bit: monitor bit
 123  */
 124 struct rzv2h_mod_clk {
 125         const char *name;
 126         u32 mstop_data;
 127         u16 parent;
 128         bool critical;
 129         bool no_pm;
 130         u8 on_index;
 131         u8 on_bit;
 132         s8 mon_index;
 133         u8 mon_bit;
 134 };
 135
 136 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
 137         { \
 138                 .name = (_name), \
 139                 .mstop_data = (_mstop), \
 140                 .parent = (_parent), \
 141                 .critical = (_critical), \
 142                 .no_pm = (_no_pm), \
 143                 .on_index = (_onindex), \
 144                 .on_bit = (_onbit), \
 145                 .mon_index = (_monindex), \
 146                 .mon_bit = (_monbit), \
 147         }
 148
 149 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
 150         DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
 151
 152 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
 153         DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
 154
 155 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
 156         DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
 157
 158 /**
 159  * struct rzv2h_reset - Reset definitions
 160  *
 161  * @reset_index: reset register index
 162  * @reset_bit: reset bit
 163  * @mon_index: monitor register index
 164  * @mon_bit: monitor bit
 165  */
 166 struct rzv2h_reset {
 167         u8 reset_index;
 168         u8 reset_bit;
 169         u8 mon_index;
 170         u8 mon_bit;
 171 };
 172
 173 #define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)    \
 174         { \
 175                 .reset_index = (_resindex), \
 176                 .reset_bit = (_resbit), \
 177                 .mon_index = (_monindex), \
 178                 .mon_bit = (_monbit), \
 179         }
 180
 181 #define DEF_RST(_resindex, _resbit, _monindex, _monbit) \
 182         DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)
 183
 184 /**
 185  * struct rzv2h_cpg_info - SoC-specific CPG Description
 186  *
 187  * @core_clks: Array of Core Clock definitions
 188  * @num_core_clks: Number of entries in core_clks[]
 189  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 190  * @num_total_core_clks: Total number of Core Clocks (exported + internal)
 191  *
 192  * @mod_clks: Array of Module Clock definitions
 193  * @num_mod_clks: Number of entries in mod_clks[]
 194  * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
 195  *
 196  * @resets: Array of Module Reset definitions
 197  * @num_resets: Number of entries in resets[]
 198  *
 199  * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the
 200  *                  number of CPG_BUS_m_MSTOP registers multiplied by 16.
 201  */
 202 struct rzv2h_cpg_info {
 203         /* Core Clocks */
 204         const struct cpg_core_clk *core_clks;
 205         unsigned int num_core_clks;
 206         unsigned int last_dt_core_clk;
 207         unsigned int num_total_core_clks;
 208
 209         /* Module Clocks */
 210         const struct rzv2h_mod_clk *mod_clks;
 211         unsigned int num_mod_clks;
 212         unsigned int num_hw_mod_clks;
 213
 214         /* Resets */
 215         const struct rzv2h_reset *resets;
 216         unsigned int num_resets;
 217
 218         unsigned int num_mstop_bits;
 219 };
 220
 221 extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
 222 extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
 223
 224 #endif  /* __RENESAS_RZV2H_CPG_H__ */