drivers/dma/ppc4xx/dma.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * 440SPe's DMA engines support header file
   4  *
   5  * 2006-2009 (C) DENX Software Engineering.
   6  *
   7  * Author: Yuri Tikhonov <yur@emcraft.com>
   8  */
   9
  10 #ifndef _PPC440SPE_DMA_H
  11 #define _PPC440SPE_DMA_H
  12
  13 #include <linux/types.h>
  14
  15 /* Number of elements in the array with statical CDBs */
  16 #define MAX_STAT_DMA_CDBS       16
  17 /* Number of DMA engines available on the controller */
  18 #define DMA_ENGINES_NUM         2
  19
  20 /* Maximum h/w supported number of destinations */
  21 #define DMA_DEST_MAX_NUM        2
  22
  23 /* FIFO's params */
  24 #define DMA0_FIFO_SIZE          0x1000
  25 #define DMA1_FIFO_SIZE          0x1000
  26 #define DMA_FIFO_ENABLE         (1<<12)
  27
  28 /* DMA Configuration Register. Data Transfer Engine PLB Priority: */
  29 #define DMA_CFG_DXEPR_LP        (0<<26)
  30 #define DMA_CFG_DXEPR_HP        (3<<26)
  31 #define DMA_CFG_DXEPR_HHP       (2<<26)
  32 #define DMA_CFG_DXEPR_HHHP      (1<<26)
  33
  34 /* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
  35 #define DMA_CFG_DFMPP_LP        (0<<23)
  36 #define DMA_CFG_DFMPP_HP        (3<<23)
  37 #define DMA_CFG_DFMPP_HHP       (2<<23)
  38 #define DMA_CFG_DFMPP_HHHP      (1<<23)
  39
  40 /* DMA Configuration Register. Force 64-byte Alignment */
  41 #define DMA_CFG_FALGN           (1 << 19)
  42
  43 /*UIC0:*/
  44 #define D0CPF_INT               (1<<12)
  45 #define D0CSF_INT               (1<<11)
  46 #define D1CPF_INT               (1<<10)
  47 #define D1CSF_INT               (1<<9)
  48 /*UIC1:*/
  49 #define DMAE_INT                (1<<9)
  50
  51 /* I2O IOP Interrupt Mask Register */
  52 #define I2O_IOPIM_P0SNE         (1<<3)
  53 #define I2O_IOPIM_P0EM          (1<<5)
  54 #define I2O_IOPIM_P1SNE         (1<<6)
  55 #define I2O_IOPIM_P1EM          (1<<8)
  56
  57 /* DMA CDB fields */
  58 #define DMA_CDB_MSK             (0xF)
  59 #define DMA_CDB_64B_ADDR        (1<<2)
  60 #define DMA_CDB_NO_INT          (1<<3)
  61 #define DMA_CDB_STATUS_MSK      (0x3)
  62 #define DMA_CDB_ADDR_MSK        (0xFFFFFFF0)
  63
  64 /* DMA CDB OpCodes */
  65 #define DMA_CDB_OPC_NO_OP       (0x00)
  66 #define DMA_CDB_OPC_MV_SG1_SG2  (0x01)
  67 #define DMA_CDB_OPC_MULTICAST   (0x05)
  68 #define DMA_CDB_OPC_DFILL128    (0x24)
  69 #define DMA_CDB_OPC_DCHECK128   (0x23)
  70
  71 #define DMA_CUED_XOR_BASE       (0x10000000)
  72 #define DMA_CUED_XOR_HB         (0x00000008)
  73
  74 #ifdef CONFIG_440SP
  75 #define DMA_CUED_MULT1_OFF      0
  76 #define DMA_CUED_MULT2_OFF      8
  77 #define DMA_CUED_MULT3_OFF      16
  78 #define DMA_CUED_REGION_OFF     24
  79 #define DMA_CUED_XOR_WIN_MSK    (0xFC000000)
  80 #else
  81 #define DMA_CUED_MULT1_OFF      2
  82 #define DMA_CUED_MULT2_OFF      10
  83 #define DMA_CUED_MULT3_OFF      18
  84 #define DMA_CUED_REGION_OFF     26
  85 #define DMA_CUED_XOR_WIN_MSK    (0xF0000000)
  86 #endif
  87
  88 #define DMA_CUED_REGION_MSK     0x3
  89 #define DMA_RXOR123             0x0
  90 #define DMA_RXOR124             0x1
  91 #define DMA_RXOR125             0x2
  92 #define DMA_RXOR12              0x3
  93
  94 /* S/G addresses */
  95 #define DMA_CDB_SG_SRC          1
  96 #define DMA_CDB_SG_DST1         2
  97 #define DMA_CDB_SG_DST2         3
  98
  99 /*
 100  * DMAx engines Command Descriptor Block Type
 101  */
 102 struct dma_cdb {
 103         /*
 104          * Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
 105          */
 106         u8      pad0[2];        /* reserved */
 107         u8      attr;           /* attributes */
 108         u8      opc;            /* opcode */
 109         u32     sg1u;           /* upper SG1 address */
 110         u32     sg1l;           /* lower SG1 address */
 111         u32     cnt;            /* SG count, 3B used */
 112         u32     sg2u;           /* upper SG2 address */
 113         u32     sg2l;           /* lower SG2 address */
 114         u32     sg3u;           /* upper SG3 address */
 115         u32     sg3l;           /* lower SG3 address */
 116 };
 117
 118 /*
 119  * DMAx hardware registers (p.515 in 440SPe UM 1.22)
 120  */
 121 struct dma_regs {
 122         u32     cpfpl;
 123         u32     cpfph;
 124         u32     csfpl;
 125         u32     csfph;
 126         u32     dsts;
 127         u32     cfg;
 128         u8      pad0[0x8];
 129         u16     cpfhp;
 130         u16     cpftp;
 131         u16     csfhp;
 132         u16     csftp;
 133         u8      pad1[0x8];
 134         u32     acpl;
 135         u32     acph;
 136         u32     s1bpl;
 137         u32     s1bph;
 138         u32     s2bpl;
 139         u32     s2bph;
 140         u32     s3bpl;
 141         u32     s3bph;
 142         u8      pad2[0x10];
 143         u32     earl;
 144         u32     earh;
 145         u8      pad3[0x8];
 146         u32     seat;
 147         u32     sead;
 148         u32     op;
 149         u32     fsiz;
 150 };
 151
 152 /*
 153  * I2O hardware registers (p.528 in 440SPe UM 1.22)
 154  */
 155 struct i2o_regs {
 156         u32     ists;
 157         u32     iseat;
 158         u32     isead;
 159         u8      pad0[0x14];
 160         u32     idbel;
 161         u8      pad1[0xc];
 162         u32     ihis;
 163         u32     ihim;
 164         u8      pad2[0x8];
 165         u32     ihiq;
 166         u32     ihoq;
 167         u8      pad3[0x8];
 168         u32     iopis;
 169         u32     iopim;
 170         u32     iopiq;
 171         u8      iopoq;
 172         u8      pad4[3];
 173         u16     iiflh;
 174         u16     iiflt;
 175         u16     iiplh;
 176         u16     iiplt;
 177         u16     ioflh;
 178         u16     ioflt;
 179         u16     ioplh;
 180         u16     ioplt;
 181         u32     iidc;
 182         u32     ictl;
 183         u32     ifcpp;
 184         u8      pad5[0x4];
 185         u16     mfac0;
 186         u16     mfac1;
 187         u16     mfac2;
 188         u16     mfac3;
 189         u16     mfac4;
 190         u16     mfac5;
 191         u16     mfac6;
 192         u16     mfac7;
 193         u16     ifcfh;
 194         u16     ifcht;
 195         u8      pad6[0x4];
 196         u32     iifmc;
 197         u32     iodb;
 198         u32     iodbc;
 199         u32     ifbal;
 200         u32     ifbah;
 201         u32     ifsiz;
 202         u32     ispd0;
 203         u32     ispd1;
 204         u32     ispd2;
 205         u32     ispd3;
 206         u32     ihipl;
 207         u32     ihiph;
 208         u32     ihopl;
 209         u32     ihoph;
 210         u32     iiipl;
 211         u32     iiiph;
 212         u32     iiopl;
 213         u32     iioph;
 214         u32     ifcpl;
 215         u32     ifcph;
 216         u8      pad7[0x8];
 217         u32     iopt;
 218 };
 219
 220 #endif /* _PPC440SPE_DMA_H */