1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/string.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
15 /* Constant Definitions */
16 #define IXR_FPGA_DONE_MASK BIT(3)
19 * struct zynqmp_fpga_priv - Private data structure
20 * @dev: Device data structure
21 * @flags: flags which is used to identify the bitfile type
23 struct zynqmp_fpga_priv
{
28 static int zynqmp_fpga_ops_write_init(struct fpga_manager
*mgr
,
29 struct fpga_image_info
*info
,
30 const char *buf
, size_t size
)
32 struct zynqmp_fpga_priv
*priv
;
35 priv
->flags
= info
->flags
;
40 static int zynqmp_fpga_ops_write(struct fpga_manager
*mgr
,
41 const char *buf
, size_t size
)
43 struct zynqmp_fpga_priv
*priv
;
51 kbuf
= dma_alloc_coherent(priv
->dev
, size
, &dma_addr
, GFP_KERNEL
);
55 memcpy(kbuf
, buf
, size
);
57 wmb(); /* ensure all writes are done before initiate FW call */
59 if (priv
->flags
& FPGA_MGR_PARTIAL_RECONFIG
)
60 eemi_flags
|= XILINX_ZYNQMP_PM_FPGA_PARTIAL
;
62 ret
= zynqmp_pm_fpga_load(dma_addr
, size
, eemi_flags
);
64 dma_free_coherent(priv
->dev
, size
, kbuf
, dma_addr
);
69 static enum fpga_mgr_states
zynqmp_fpga_ops_state(struct fpga_manager
*mgr
)
73 zynqmp_pm_fpga_get_status(&status
);
74 if (status
& IXR_FPGA_DONE_MASK
)
75 return FPGA_MGR_STATE_OPERATING
;
77 return FPGA_MGR_STATE_UNKNOWN
;
80 static ssize_t
status_show(struct device
*dev
,
81 struct device_attribute
*attr
, char *buf
)
86 ret
= zynqmp_pm_fpga_get_config_status(&status
);
90 return sysfs_emit(buf
, "0x%x\n", status
);
92 static DEVICE_ATTR_RO(status
);
94 static struct attribute
*zynqmp_fpga_attrs
[] = {
95 &dev_attr_status
.attr
,
98 ATTRIBUTE_GROUPS(zynqmp_fpga
);
100 static const struct fpga_manager_ops zynqmp_fpga_ops
= {
101 .state
= zynqmp_fpga_ops_state
,
102 .write_init
= zynqmp_fpga_ops_write_init
,
103 .write
= zynqmp_fpga_ops_write
,
106 static int zynqmp_fpga_probe(struct platform_device
*pdev
)
108 struct device
*dev
= &pdev
->dev
;
109 struct zynqmp_fpga_priv
*priv
;
110 struct fpga_manager
*mgr
;
112 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
118 mgr
= devm_fpga_mgr_register(dev
, "Xilinx ZynqMP FPGA Manager",
119 &zynqmp_fpga_ops
, priv
);
120 return PTR_ERR_OR_ZERO(mgr
);
124 static const struct of_device_id zynqmp_fpga_of_match
[] = {
125 { .compatible
= "xlnx,zynqmp-pcap-fpga", },
128 MODULE_DEVICE_TABLE(of
, zynqmp_fpga_of_match
);
131 static struct platform_driver zynqmp_fpga_driver
= {
132 .probe
= zynqmp_fpga_probe
,
134 .name
= "zynqmp_fpga_manager",
135 .of_match_table
= of_match_ptr(zynqmp_fpga_of_match
),
136 .dev_groups
= zynqmp_fpga_groups
,
140 module_platform_driver(zynqmp_fpga_driver
);
142 MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
143 MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
144 MODULE_LICENSE("GPL");