drivers/gpio/gpio-mmio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Generic driver for memory-mapped GPIO controllers.
   4  *
   5  * Copyright 2008 MontaVista Software, Inc.
   6  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
   7  *
   8  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
   9  * ...``                                                         ```````..
  10  * ..The simplest form of a GPIO controller that the driver supports is``
  11  *  `.just a single "data" register, where GPIO state can be read and/or `
  12  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
  13  *        `````````
  14                                     ___
  15 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
  16 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
  17 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
  18                                                  `....trivial..'~`.```.```
  19  *                                                    ```````
  20  *  .```````~~~~`..`.``.``.
  21  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
  22  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
  23  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
  24  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
  25  *     ``.`.``...```                  ```.. output pins are also supported.`
  26  *                        ^^             `````.`````````.,``~``~``~~``````
  27  *                                                   .                  ^^
  28  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
  29  * .. The expectation is that in at least some cases .    ,-~~~-,
  30  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
  31  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
  32  *  ..````````......```````````                             \o_
  33  *                                                           |
  34  *                              ^^                          / \
  35  *
  36  *           ...`````~~`.....``.`..........``````.`.``.```........``.
  37  *            `  8, 16, 32 and 64 bits registers are supported, and``.
  38  *            . the number of GPIOs is determined by the width of   ~
  39  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
  40  *               `.......````.```
  41  */
  42
  43 #include <linux/bitops.h>
  44 #include <linux/compiler.h>
  45 #include <linux/err.h>
  46 #include <linux/init.h>
  47 #include <linux/io.h>
  48 #include <linux/ioport.h>
  49 #include <linux/log2.h>
  50 #include <linux/mod_devicetable.h>
  51 #include <linux/module.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/property.h>
  54 #include <linux/slab.h>
  55 #include <linux/spinlock.h>
  56 #include <linux/types.h>
  57
  58 #include <linux/gpio/driver.h>
  59
  60 #include "gpiolib.h"
  61
  62 static void bgpio_write8(void __iomem *reg, unsigned long data)
  63 {
  64         writeb(data, reg);
  65 }
  66
  67 static unsigned long bgpio_read8(void __iomem *reg)
  68 {
  69         return readb(reg);
  70 }
  71
  72 static void bgpio_write16(void __iomem *reg, unsigned long data)
  73 {
  74         writew(data, reg);
  75 }
  76
  77 static unsigned long bgpio_read16(void __iomem *reg)
  78 {
  79         return readw(reg);
  80 }
  81
  82 static void bgpio_write32(void __iomem *reg, unsigned long data)
  83 {
  84         writel(data, reg);
  85 }
  86
  87 static unsigned long bgpio_read32(void __iomem *reg)
  88 {
  89         return readl(reg);
  90 }
  91
  92 #if BITS_PER_LONG >= 64
  93 static void bgpio_write64(void __iomem *reg, unsigned long data)
  94 {
  95         writeq(data, reg);
  96 }
  97
  98 static unsigned long bgpio_read64(void __iomem *reg)
  99 {
 100         return readq(reg);
 101 }
 102 #endif /* BITS_PER_LONG >= 64 */
 103
 104 static void bgpio_write16be(void __iomem *reg, unsigned long data)
 105 {
 106         iowrite16be(data, reg);
 107 }
 108
 109 static unsigned long bgpio_read16be(void __iomem *reg)
 110 {
 111         return ioread16be(reg);
 112 }
 113
 114 static void bgpio_write32be(void __iomem *reg, unsigned long data)
 115 {
 116         iowrite32be(data, reg);
 117 }
 118
 119 static unsigned long bgpio_read32be(void __iomem *reg)
 120 {
 121         return ioread32be(reg);
 122 }
 123
 124 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
 125 {
 126         if (gc->be_bits)
 127                 return BIT(gc->bgpio_bits - 1 - line);
 128         return BIT(line);
 129 }
 130
 131 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
 132 {
 133         unsigned long pinmask = bgpio_line2mask(gc, gpio);
 134         bool dir = !!(gc->bgpio_dir & pinmask);
 135
 136         if (dir)
 137                 return !!(gc->read_reg(gc->reg_set) & pinmask);
 138         else
 139                 return !!(gc->read_reg(gc->reg_dat) & pinmask);
 140 }
 141
 142 /*
 143  * This assumes that the bits in the GPIO register are in native endianness.
 144  * We only assign the function pointer if we have that.
 145  */
 146 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 147                                   unsigned long *bits)
 148 {
 149         unsigned long get_mask = 0;
 150         unsigned long set_mask = 0;
 151
 152         /* Make sure we first clear any bits that are zero when we read the register */
 153         *bits &= ~*mask;
 154
 155         set_mask = *mask & gc->bgpio_dir;
 156         get_mask = *mask & ~gc->bgpio_dir;
 157
 158         if (set_mask)
 159                 *bits |= gc->read_reg(gc->reg_set) & set_mask;
 160         if (get_mask)
 161                 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
 162
 163         return 0;
 164 }
 165
 166 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
 167 {
 168         return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
 169 }
 170
 171 /*
 172  * This only works if the bits in the GPIO register are in native endianness.
 173  */
 174 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
 175                               unsigned long *bits)
 176 {
 177         /* Make sure we first clear any bits that are zero when we read the register */
 178         *bits &= ~*mask;
 179         *bits |= gc->read_reg(gc->reg_dat) & *mask;
 180         return 0;
 181 }
 182
 183 /*
 184  * With big endian mirrored bit order it becomes more tedious.
 185  */
 186 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
 187                                  unsigned long *bits)
 188 {
 189         unsigned long readmask = 0;
 190         unsigned long val;
 191         int bit;
 192
 193         /* Make sure we first clear any bits that are zero when we read the register */
 194         *bits &= ~*mask;
 195
 196         /* Create a mirrored mask */
 197         for_each_set_bit(bit, mask, gc->ngpio)
 198                 readmask |= bgpio_line2mask(gc, bit);
 199
 200         /* Read the register */
 201         val = gc->read_reg(gc->reg_dat) & readmask;
 202
 203         /*
 204          * Mirror the result into the "bits" result, this will give line 0
 205          * in bit 0 ... line 31 in bit 31 for a 32bit register.
 206          */
 207         for_each_set_bit(bit, &val, gc->ngpio)
 208                 *bits |= bgpio_line2mask(gc, bit);
 209
 210         return 0;
 211 }
 212
 213 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
 214 {
 215 }
 216
 217 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 218 {
 219         unsigned long mask = bgpio_line2mask(gc, gpio);
 220         unsigned long flags;
 221
 222         raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
 223
 224         if (val)
 225                 gc->bgpio_data |= mask;
 226         else
 227                 gc->bgpio_data &= ~mask;
 228
 229         gc->write_reg(gc->reg_dat, gc->bgpio_data);
 230
 231         raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 232 }
 233
 234 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
 235                                  int val)
 236 {
 237         unsigned long mask = bgpio_line2mask(gc, gpio);
 238
 239         if (val)
 240                 gc->write_reg(gc->reg_set, mask);
 241         else
 242                 gc->write_reg(gc->reg_clr, mask);
 243 }
 244
 245 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
 246 {
 247         unsigned long mask = bgpio_line2mask(gc, gpio);
 248         unsigned long flags;
 249
 250         raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
 251
 252         if (val)
 253                 gc->bgpio_data |= mask;
 254         else
 255                 gc->bgpio_data &= ~mask;
 256
 257         gc->write_reg(gc->reg_set, gc->bgpio_data);
 258
 259         raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 260 }
 261
 262 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
 263                                      unsigned long *mask, unsigned long *bits,
 264                                      unsigned long *set_mask,
 265                                      unsigned long *clear_mask)
 266 {
 267         int i;
 268
 269         *set_mask = 0;
 270         *clear_mask = 0;
 271
 272         for_each_set_bit(i, mask, gc->bgpio_bits) {
 273                 if (test_bit(i, bits))
 274                         *set_mask |= bgpio_line2mask(gc, i);
 275                 else
 276                         *clear_mask |= bgpio_line2mask(gc, i);
 277         }
 278 }
 279
 280 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
 281                                           unsigned long *mask,
 282                                           unsigned long *bits,
 283                                           void __iomem *reg)
 284 {
 285         unsigned long flags;
 286         unsigned long set_mask, clear_mask;
 287
 288         raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
 289
 290         bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 291
 292         gc->bgpio_data |= set_mask;
 293         gc->bgpio_data &= ~clear_mask;
 294
 295         gc->write_reg(reg, gc->bgpio_data);
 296
 297         raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 298 }
 299
 300 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 301                                unsigned long *bits)
 302 {
 303         bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
 304 }
 305
 306 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
 307                                    unsigned long *bits)
 308 {
 309         bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
 310 }
 311
 312 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
 313                                           unsigned long *mask,
 314                                           unsigned long *bits)
 315 {
 316         unsigned long set_mask, clear_mask;
 317
 318         bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 319
 320         if (set_mask)
 321                 gc->write_reg(gc->reg_set, set_mask);
 322         if (clear_mask)
 323                 gc->write_reg(gc->reg_clr, clear_mask);
 324 }
 325
 326 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
 327 {
 328         return 0;
 329 }
 330
 331 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
 332                                 int val)
 333 {
 334         return -EINVAL;
 335 }
 336
 337 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
 338                                 int val)
 339 {
 340         gc->set(gc, gpio, val);
 341
 342         return 0;
 343 }
 344
 345 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 346 {
 347         unsigned long flags;
 348
 349         raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
 350
 351         gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
 352
 353         if (gc->reg_dir_in)
 354                 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
 355         if (gc->reg_dir_out)
 356                 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
 357
 358         raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 359
 360         return 0;
 361 }
 362
 363 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
 364 {
 365         /* Return 0 if output, 1 if input */
 366         if (gc->bgpio_dir_unreadable) {
 367                 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
 368                         return GPIO_LINE_DIRECTION_OUT;
 369                 return GPIO_LINE_DIRECTION_IN;
 370         }
 371
 372         if (gc->reg_dir_out) {
 373                 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
 374                         return GPIO_LINE_DIRECTION_OUT;
 375                 return GPIO_LINE_DIRECTION_IN;
 376         }
 377
 378         if (gc->reg_dir_in)
 379                 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
 380                         return GPIO_LINE_DIRECTION_OUT;
 381
 382         return GPIO_LINE_DIRECTION_IN;
 383 }
 384
 385 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 386 {
 387         unsigned long flags;
 388
 389         raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
 390
 391         gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
 392
 393         if (gc->reg_dir_in)
 394                 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
 395         if (gc->reg_dir_out)
 396                 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
 397
 398         raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 399 }
 400
 401 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
 402                                    int val)
 403 {
 404         bgpio_dir_out(gc, gpio, val);
 405         gc->set(gc, gpio, val);
 406         return 0;
 407 }
 408
 409 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
 410                                    int val)
 411 {
 412         gc->set(gc, gpio, val);
 413         bgpio_dir_out(gc, gpio, val);
 414         return 0;
 415 }
 416
 417 static int bgpio_setup_accessors(struct device *dev,
 418                                  struct gpio_chip *gc,
 419                                  bool byte_be)
 420 {
 421
 422         switch (gc->bgpio_bits) {
 423         case 8:
 424                 gc->read_reg    = bgpio_read8;
 425                 gc->write_reg   = bgpio_write8;
 426                 break;
 427         case 16:
 428                 if (byte_be) {
 429                         gc->read_reg    = bgpio_read16be;
 430                         gc->write_reg   = bgpio_write16be;
 431                 } else {
 432                         gc->read_reg    = bgpio_read16;
 433                         gc->write_reg   = bgpio_write16;
 434                 }
 435                 break;
 436         case 32:
 437                 if (byte_be) {
 438                         gc->read_reg    = bgpio_read32be;
 439                         gc->write_reg   = bgpio_write32be;
 440                 } else {
 441                         gc->read_reg    = bgpio_read32;
 442                         gc->write_reg   = bgpio_write32;
 443                 }
 444                 break;
 445 #if BITS_PER_LONG >= 64
 446         case 64:
 447                 if (byte_be) {
 448                         dev_err(dev,
 449                                 "64 bit big endian byte order unsupported\n");
 450                         return -EINVAL;
 451                 } else {
 452                         gc->read_reg    = bgpio_read64;
 453                         gc->write_reg   = bgpio_write64;
 454                 }
 455                 break;
 456 #endif /* BITS_PER_LONG >= 64 */
 457         default:
 458                 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
 459                 return -EINVAL;
 460         }
 461
 462         return 0;
 463 }
 464
 465 /*
 466  * Create the device and allocate the resources.  For setting GPIO's there are
 467  * three supported configurations:
 468  *
 469  *      - single input/output register resource (named "dat").
 470  *      - set/clear pair (named "set" and "clr").
 471  *      - single output register resource and single input resource ("set" and
 472  *      dat").
 473  *
 474  * For the single output register, this drives a 1 by setting a bit and a zero
 475  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 476  * in the set register and clears it by setting a bit in the clear register.
 477  * The configuration is detected by which resources are present.
 478  *
 479  * For setting the GPIO direction, there are three supported configurations:
 480  *
 481  *      - simple bidirection GPIO that requires no configuration.
 482  *      - an output direction register (named "dirout") where a 1 bit
 483  *      indicates the GPIO is an output.
 484  *      - an input direction register (named "dirin") where a 1 bit indicates
 485  *      the GPIO is an input.
 486  */
 487 static int bgpio_setup_io(struct gpio_chip *gc,
 488                           void __iomem *dat,
 489                           void __iomem *set,
 490                           void __iomem *clr,
 491                           unsigned long flags)
 492 {
 493
 494         gc->reg_dat = dat;
 495         if (!gc->reg_dat)
 496                 return -EINVAL;
 497
 498         if (set && clr) {
 499                 gc->reg_set = set;
 500                 gc->reg_clr = clr;
 501                 gc->set = bgpio_set_with_clear;
 502                 gc->set_multiple = bgpio_set_multiple_with_clear;
 503         } else if (set && !clr) {
 504                 gc->reg_set = set;
 505                 gc->set = bgpio_set_set;
 506                 gc->set_multiple = bgpio_set_multiple_set;
 507         } else if (flags & BGPIOF_NO_OUTPUT) {
 508                 gc->set = bgpio_set_none;
 509                 gc->set_multiple = NULL;
 510         } else {
 511                 gc->set = bgpio_set;
 512                 gc->set_multiple = bgpio_set_multiple;
 513         }
 514
 515         if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
 516             (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
 517                 gc->get = bgpio_get_set;
 518                 if (!gc->be_bits)
 519                         gc->get_multiple = bgpio_get_set_multiple;
 520                 /*
 521                  * We deliberately avoid assigning the ->get_multiple() call
 522                  * for big endian mirrored registers which are ALSO reflecting
 523                  * their value in the set register when used as output. It is
 524                  * simply too much complexity, let the GPIO core fall back to
 525                  * reading each line individually in that fringe case.
 526                  */
 527         } else {
 528                 gc->get = bgpio_get;
 529                 if (gc->be_bits)
 530                         gc->get_multiple = bgpio_get_multiple_be;
 531                 else
 532                         gc->get_multiple = bgpio_get_multiple;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int bgpio_setup_direction(struct gpio_chip *gc,
 539                                  void __iomem *dirout,
 540                                  void __iomem *dirin,
 541                                  unsigned long flags)
 542 {
 543         if (dirout || dirin) {
 544                 gc->reg_dir_out = dirout;
 545                 gc->reg_dir_in = dirin;
 546                 if (flags & BGPIOF_NO_SET_ON_INPUT)
 547                         gc->direction_output = bgpio_dir_out_dir_first;
 548                 else
 549                         gc->direction_output = bgpio_dir_out_val_first;
 550                 gc->direction_input = bgpio_dir_in;
 551                 gc->get_direction = bgpio_get_dir;
 552         } else {
 553                 if (flags & BGPIOF_NO_OUTPUT)
 554                         gc->direction_output = bgpio_dir_out_err;
 555                 else
 556                         gc->direction_output = bgpio_simple_dir_out;
 557                 gc->direction_input = bgpio_simple_dir_in;
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
 564 {
 565         if (gpio_pin < chip->ngpio)
 566                 return 0;
 567
 568         return -EINVAL;
 569 }
 570
 571 /**
 572  * bgpio_init() - Initialize generic GPIO accessor functions
 573  * @gc: the GPIO chip to set up
 574  * @dev: the parent device of the new GPIO chip (compulsory)
 575  * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
 576  * @dat: MMIO address for the register to READ the value of the GPIO lines, it
 577  *      is expected that a 1 in the corresponding bit in this register means the
 578  *      line is asserted
 579  * @set: MMIO address for the register to SET the value of the GPIO lines, it is
 580  *      expected that we write the line with 1 in this register to drive the GPIO line
 581  *      high.
 582  * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
 583  *      expected that we write the line with 1 in this register to drive the GPIO line
 584  *      low. It is allowed to leave this address as NULL, in that case the SET register
 585  *      will be assumed to also clear the GPIO lines, by actively writing the line
 586  *      with 0.
 587  * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
 588  *      that setting a line to 1 in this register will turn that line into an
 589  *      output line. Conversely, setting the line to 0 will turn that line into
 590  *      an input.
 591  * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
 592  *      that setting a line to 1 in this register will turn that line into an
 593  *      input line. Conversely, setting the line to 0 will turn that line into
 594  *      an output.
 595  * @flags: Different flags that will affect the behaviour of the device, such as
 596  *      endianness etc.
 597  */
 598 int bgpio_init(struct gpio_chip *gc, struct device *dev,
 599                unsigned long sz, void __iomem *dat, void __iomem *set,
 600                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
 601                unsigned long flags)
 602 {
 603         int ret;
 604
 605         if (!is_power_of_2(sz))
 606                 return -EINVAL;
 607
 608         gc->bgpio_bits = sz * 8;
 609         if (gc->bgpio_bits > BITS_PER_LONG)
 610                 return -EINVAL;
 611
 612         raw_spin_lock_init(&gc->bgpio_lock);
 613         gc->parent = dev;
 614         gc->label = dev_name(dev);
 615         gc->base = -1;
 616         gc->request = bgpio_request;
 617         gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
 618
 619         ret = gpiochip_get_ngpios(gc, dev);
 620         if (ret)
 621                 gc->ngpio = gc->bgpio_bits;
 622
 623         ret = bgpio_setup_io(gc, dat, set, clr, flags);
 624         if (ret)
 625                 return ret;
 626
 627         ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 628         if (ret)
 629                 return ret;
 630
 631         ret = bgpio_setup_direction(gc, dirout, dirin, flags);
 632         if (ret)
 633                 return ret;
 634
 635         gc->bgpio_data = gc->read_reg(gc->reg_dat);
 636         if (gc->set == bgpio_set_set &&
 637                         !(flags & BGPIOF_UNREADABLE_REG_SET))
 638                 gc->bgpio_data = gc->read_reg(gc->reg_set);
 639
 640         if (flags & BGPIOF_UNREADABLE_REG_DIR)
 641                 gc->bgpio_dir_unreadable = true;
 642
 643         /*
 644          * Inspect hardware to find initial direction setting.
 645          */
 646         if ((gc->reg_dir_out || gc->reg_dir_in) &&
 647             !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
 648                 if (gc->reg_dir_out)
 649                         gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
 650                 else if (gc->reg_dir_in)
 651                         gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
 652                 /*
 653                  * If we have two direction registers, synchronise
 654                  * input setting to output setting, the library
 655                  * can not handle a line being input and output at
 656                  * the same time.
 657                  */
 658                 if (gc->reg_dir_out && gc->reg_dir_in)
 659                         gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
 660         }
 661
 662         return ret;
 663 }
 664 EXPORT_SYMBOL_GPL(bgpio_init);
 665
 666 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
 667
 668 static void __iomem *bgpio_map(struct platform_device *pdev,
 669                                const char *name,
 670                                resource_size_t sane_sz)
 671 {
 672         struct resource *r;
 673         resource_size_t sz;
 674
 675         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 676         if (!r)
 677                 return NULL;
 678
 679         sz = resource_size(r);
 680         if (sz != sane_sz)
 681                 return IOMEM_ERR_PTR(-EINVAL);
 682
 683         return devm_ioremap_resource(&pdev->dev, r);
 684 }
 685
 686 static const struct of_device_id bgpio_of_match[] = {
 687         { .compatible = "brcm,bcm6345-gpio" },
 688         { .compatible = "wd,mbl-gpio" },
 689         { .compatible = "ni,169445-nand-gpio" },
 690         { }
 691 };
 692 MODULE_DEVICE_TABLE(of, bgpio_of_match);
 693
 694 static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags)
 695 {
 696         struct bgpio_pdata *pdata;
 697
 698         if (!dev_fwnode(dev))
 699                 return NULL;
 700
 701         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 702         if (!pdata)
 703                 return ERR_PTR(-ENOMEM);
 704
 705         pdata->base = -1;
 706
 707         if (device_is_big_endian(dev))
 708                 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
 709
 710         if (device_property_read_bool(dev, "no-output"))
 711                 *flags |= BGPIOF_NO_OUTPUT;
 712
 713         return pdata;
 714 }
 715
 716 static int bgpio_pdev_probe(struct platform_device *pdev)
 717 {
 718         struct device *dev = &pdev->dev;
 719         struct resource *r;
 720         void __iomem *dat;
 721         void __iomem *set;
 722         void __iomem *clr;
 723         void __iomem *dirout;
 724         void __iomem *dirin;
 725         unsigned long sz;
 726         unsigned long flags = 0;
 727         int err;
 728         struct gpio_chip *gc;
 729         struct bgpio_pdata *pdata;
 730
 731         pdata = bgpio_parse_fw(dev, &flags);
 732         if (IS_ERR(pdata))
 733                 return PTR_ERR(pdata);
 734
 735         if (!pdata) {
 736                 pdata = dev_get_platdata(dev);
 737                 flags = pdev->id_entry->driver_data;
 738         }
 739
 740         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
 741         if (!r)
 742                 return -EINVAL;
 743
 744         sz = resource_size(r);
 745
 746         dat = bgpio_map(pdev, "dat", sz);
 747         if (IS_ERR(dat))
 748                 return PTR_ERR(dat);
 749
 750         set = bgpio_map(pdev, "set", sz);
 751         if (IS_ERR(set))
 752                 return PTR_ERR(set);
 753
 754         clr = bgpio_map(pdev, "clr", sz);
 755         if (IS_ERR(clr))
 756                 return PTR_ERR(clr);
 757
 758         dirout = bgpio_map(pdev, "dirout", sz);
 759         if (IS_ERR(dirout))
 760                 return PTR_ERR(dirout);
 761
 762         dirin = bgpio_map(pdev, "dirin", sz);
 763         if (IS_ERR(dirin))
 764                 return PTR_ERR(dirin);
 765
 766         gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
 767         if (!gc)
 768                 return -ENOMEM;
 769
 770         err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
 771         if (err)
 772                 return err;
 773
 774         if (pdata) {
 775                 if (pdata->label)
 776                         gc->label = pdata->label;
 777                 gc->base = pdata->base;
 778                 if (pdata->ngpio > 0)
 779                         gc->ngpio = pdata->ngpio;
 780         }
 781
 782         platform_set_drvdata(pdev, gc);
 783
 784         return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
 785 }
 786
 787 static const struct platform_device_id bgpio_id_table[] = {
 788         {
 789                 .name           = "basic-mmio-gpio",
 790                 .driver_data    = 0,
 791         }, {
 792                 .name           = "basic-mmio-gpio-be",
 793                 .driver_data    = BGPIOF_BIG_ENDIAN,
 794         },
 795         { }
 796 };
 797 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
 798
 799 static struct platform_driver bgpio_driver = {
 800         .driver = {
 801                 .name = "basic-mmio-gpio",
 802                 .of_match_table = bgpio_of_match,
 803         },
 804         .id_table = bgpio_id_table,
 805         .probe = bgpio_pdev_probe,
 806 };
 807
 808 module_platform_driver(bgpio_driver);
 809
 810 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
 811
 812 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
 813 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
 814 MODULE_LICENSE("GPL");