drivers/gpio/gpio-npcm-sgpio.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nuvoton NPCM Serial GPIO Driver
   4  *
   5  * Copyright (C) 2021 Nuvoton Technologies
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/gpio/driver.h>
  11 #include <linux/hashtable.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/string.h>
  18 #include <linux/units.h>
  19
  20 #define MAX_NR_HW_SGPIO         64
  21
  22 #define  NPCM_IOXCFG1           0x2A
  23 #define  NPCM_IOXCFG1_SFT_CLK   GENMASK(3, 0)
  24 #define  NPCM_IOXCFG1_SCLK_POL  BIT(4)
  25 #define  NPCM_IOXCFG1_LDSH_POL  BIT(5)
  26
  27 #define  NPCM_IOXCTS                    0x28
  28 #define  NPCM_IOXCTS_IOXIF_EN           BIT(7)
  29 #define  NPCM_IOXCTS_RD_MODE            GENMASK(2, 1)
  30 #define  NPCM_IOXCTS_RD_MODE_PERIODIC   BIT(2)
  31
  32 #define  NPCM_IOXCFG2           0x2B
  33 #define  NPCM_IOXCFG2_PORT      GENMASK(3, 0)
  34
  35 #define  NPCM_IXOEVCFG_MASK     GENMASK(1, 0)
  36 #define  NPCM_IXOEVCFG_FALLING  BIT(1)
  37 #define  NPCM_IXOEVCFG_RISING   BIT(0)
  38 #define  NPCM_IXOEVCFG_BOTH     (NPCM_IXOEVCFG_FALLING | NPCM_IXOEVCFG_RISING)
  39
  40 #define NPCM_CLK_MHZ    (8 * HZ_PER_MHZ)
  41 #define NPCM_750_OPT    6
  42 #define NPCM_845_OPT    5
  43
  44 #define GPIO_BANK(x)    ((x) / 8)
  45 #define GPIO_BIT(x)     ((x) % 8)
  46
  47 /*
  48  * Select the frequency of shift clock.
  49  * The shift clock is a division of the APB clock.
  50  */
  51 struct npcm_clk_cfg {
  52         unsigned int    *sft_clk;
  53         unsigned int    *clk_sel;
  54         unsigned int    cfg_opt;
  55 };
  56
  57 struct npcm_sgpio {
  58         struct gpio_chip chip;
  59         struct clk *pclk;
  60         struct irq_chip intc;
  61         raw_spinlock_t lock;
  62
  63         void __iomem *base;
  64         int irq;
  65         u8 nin_sgpio;
  66         u8 nout_sgpio;
  67         u8 in_port;
  68         u8 out_port;
  69         u8 int_type[MAX_NR_HW_SGPIO];
  70 };
  71
  72 struct npcm_sgpio_bank {
  73         u8 rdata_reg;
  74         u8 wdata_reg;
  75         u8 event_config;
  76         u8 event_status;
  77 };
  78
  79 enum npcm_sgpio_reg {
  80         READ_DATA,
  81         WRITE_DATA,
  82         EVENT_CFG,
  83         EVENT_STS,
  84 };
  85
  86 static const struct npcm_sgpio_bank npcm_sgpio_banks[] = {
  87         {
  88                 .wdata_reg = 0x00,
  89                 .rdata_reg = 0x08,
  90                 .event_config = 0x10,
  91                 .event_status = 0x20,
  92         },
  93         {
  94                 .wdata_reg = 0x01,
  95                 .rdata_reg = 0x09,
  96                 .event_config = 0x12,
  97                 .event_status = 0x21,
  98         },
  99         {
 100                 .wdata_reg = 0x02,
 101                 .rdata_reg = 0x0a,
 102                 .event_config = 0x14,
 103                 .event_status = 0x22,
 104         },
 105         {
 106                 .wdata_reg = 0x03,
 107                 .rdata_reg = 0x0b,
 108                 .event_config = 0x16,
 109                 .event_status = 0x23,
 110         },
 111         {
 112                 .wdata_reg = 0x04,
 113                 .rdata_reg = 0x0c,
 114                 .event_config = 0x18,
 115                 .event_status = 0x24,
 116         },
 117         {
 118                 .wdata_reg = 0x05,
 119                 .rdata_reg = 0x0d,
 120                 .event_config = 0x1a,
 121                 .event_status = 0x25,
 122         },
 123         {
 124                 .wdata_reg = 0x06,
 125                 .rdata_reg = 0x0e,
 126                 .event_config = 0x1c,
 127                 .event_status = 0x26,
 128         },
 129         {
 130                 .wdata_reg = 0x07,
 131                 .rdata_reg = 0x0f,
 132                 .event_config = 0x1e,
 133                 .event_status = 0x27,
 134         },
 135 };
 136
 137 static void __iomem *bank_reg(struct npcm_sgpio *gpio,
 138                               const struct npcm_sgpio_bank *bank,
 139                               const enum npcm_sgpio_reg reg)
 140 {
 141         switch (reg) {
 142         case READ_DATA:
 143                 return gpio->base + bank->rdata_reg;
 144         case WRITE_DATA:
 145                 return gpio->base + bank->wdata_reg;
 146         case EVENT_CFG:
 147                 return gpio->base + bank->event_config;
 148         case EVENT_STS:
 149                 return gpio->base + bank->event_status;
 150         default:
 151                 /* actually if code runs to here, it's an error case */
 152                 dev_WARN(gpio->chip.parent, "Getting here is an error condition");
 153                 return NULL;
 154         }
 155 }
 156
 157 static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset)
 158 {
 159         unsigned int bank = GPIO_BANK(offset);
 160
 161         return &npcm_sgpio_banks[bank];
 162 }
 163
 164 static void npcm_sgpio_irqd_to_data(struct irq_data *d,
 165                                     struct npcm_sgpio **gpio,
 166                                     const struct npcm_sgpio_bank **bank,
 167                                     u8 *bit, unsigned int *offset)
 168 {
 169         struct npcm_sgpio *internal;
 170
 171         *offset = irqd_to_hwirq(d);
 172         internal = irq_data_get_irq_chip_data(d);
 173
 174         *gpio = internal;
 175         *offset -= internal->nout_sgpio;
 176         *bank = offset_to_bank(*offset);
 177         *bit = GPIO_BIT(*offset);
 178 }
 179
 180 static int npcm_sgpio_init_port(struct npcm_sgpio *gpio)
 181 {
 182         u8 in_port, out_port, set_port, reg;
 183
 184         in_port = GPIO_BANK(gpio->nin_sgpio);
 185         if (GPIO_BIT(gpio->nin_sgpio) > 0)
 186                 in_port += 1;
 187
 188         out_port = GPIO_BANK(gpio->nout_sgpio);
 189         if (GPIO_BIT(gpio->nout_sgpio) > 0)
 190                 out_port += 1;
 191
 192         gpio->in_port = in_port;
 193         gpio->out_port = out_port;
 194         set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 |
 195                    (in_port & NPCM_IOXCFG2_PORT);
 196         iowrite8(set_port, gpio->base + NPCM_IOXCFG2);
 197
 198         reg = ioread8(gpio->base + NPCM_IOXCFG2);
 199
 200         return reg == set_port ? 0 : -EINVAL;
 201
 202 }
 203
 204 static int npcm_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 205 {
 206         struct npcm_sgpio *gpio = gpiochip_get_data(gc);
 207
 208         return offset < gpio->nout_sgpio ? -EINVAL : 0;
 209
 210 }
 211
 212 static int npcm_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
 213 {
 214         gc->set(gc, offset, val);
 215
 216         return 0;
 217 }
 218
 219 static int npcm_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 220 {
 221         struct npcm_sgpio *gpio = gpiochip_get_data(gc);
 222
 223         if (offset < gpio->nout_sgpio)
 224                 return GPIO_LINE_DIRECTION_OUT;
 225
 226         return GPIO_LINE_DIRECTION_IN;
 227 }
 228
 229 static void npcm_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 230 {
 231         struct npcm_sgpio *gpio = gpiochip_get_data(gc);
 232         const struct  npcm_sgpio_bank *bank = offset_to_bank(offset);
 233         void __iomem *addr;
 234         u8 reg = 0;
 235
 236         addr = bank_reg(gpio, bank, WRITE_DATA);
 237         reg = ioread8(addr);
 238
 239         if (val)
 240                 reg |= BIT(GPIO_BIT(offset));
 241         else
 242                 reg &= ~BIT(GPIO_BIT(offset));
 243
 244         iowrite8(reg, addr);
 245 }
 246
 247 static int npcm_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 248 {
 249         struct npcm_sgpio *gpio = gpiochip_get_data(gc);
 250         const struct  npcm_sgpio_bank *bank;
 251         void __iomem *addr;
 252         u8 reg;
 253
 254         if (offset < gpio->nout_sgpio) {
 255                 bank = offset_to_bank(offset);
 256                 addr = bank_reg(gpio, bank, WRITE_DATA);
 257         } else {
 258                 offset -= gpio->nout_sgpio;
 259                 bank = offset_to_bank(offset);
 260                 addr = bank_reg(gpio, bank, READ_DATA);
 261         }
 262
 263         reg = ioread8(addr);
 264
 265         return !!(reg & BIT(GPIO_BIT(offset)));
 266 }
 267
 268 static void npcm_sgpio_setup_enable(struct npcm_sgpio *gpio, bool enable)
 269 {
 270         u8 reg;
 271
 272         reg = ioread8(gpio->base + NPCM_IOXCTS);
 273         reg = (reg & ~NPCM_IOXCTS_RD_MODE) | NPCM_IOXCTS_RD_MODE_PERIODIC;
 274
 275         if (enable)
 276                 reg |= NPCM_IOXCTS_IOXIF_EN;
 277         else
 278                 reg &= ~NPCM_IOXCTS_IOXIF_EN;
 279
 280         iowrite8(reg, gpio->base + NPCM_IOXCTS);
 281 }
 282
 283 static int npcm_sgpio_setup_clk(struct npcm_sgpio *gpio,
 284                                 const struct npcm_clk_cfg *clk_cfg)
 285 {
 286         unsigned long apb_freq;
 287         u32 val;
 288         u8 tmp;
 289         int i;
 290
 291         apb_freq = clk_get_rate(gpio->pclk);
 292         tmp = ioread8(gpio->base + NPCM_IOXCFG1) & ~NPCM_IOXCFG1_SFT_CLK;
 293
 294         for (i = clk_cfg->cfg_opt-1; i > 0; i--) {
 295                 val = apb_freq / clk_cfg->sft_clk[i];
 296                 if (NPCM_CLK_MHZ > val) {
 297                         iowrite8(clk_cfg->clk_sel[i] | tmp,
 298                                  gpio->base + NPCM_IOXCFG1);
 299                         return 0;
 300                 }
 301         }
 302
 303         return -EINVAL;
 304 }
 305
 306 static void npcm_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
 307                                            unsigned long *valid_mask,
 308                                            unsigned int ngpios)
 309 {
 310         struct npcm_sgpio *gpio = gpiochip_get_data(gc);
 311
 312         /* input GPIOs in the high range */
 313         bitmap_set(valid_mask, gpio->nout_sgpio, gpio->nin_sgpio);
 314         bitmap_clear(valid_mask, 0, gpio->nout_sgpio);
 315 }
 316
 317 static void npcm_sgpio_irq_set_mask(struct irq_data *d, bool set)
 318 {
 319         const struct npcm_sgpio_bank *bank;
 320         struct npcm_sgpio *gpio;
 321         unsigned long flags;
 322         void __iomem *addr;
 323         unsigned int offset;
 324         u16 reg, type;
 325         u8 bit;
 326
 327         npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
 328         addr = bank_reg(gpio, bank, EVENT_CFG);
 329
 330         reg = ioread16(addr);
 331         if (set) {
 332                 reg &= ~(NPCM_IXOEVCFG_MASK << (bit * 2));
 333         } else {
 334                 type = gpio->int_type[offset];
 335                 reg |= (type << (bit * 2));
 336         }
 337
 338         raw_spin_lock_irqsave(&gpio->lock, flags);
 339
 340         npcm_sgpio_setup_enable(gpio, false);
 341
 342         iowrite16(reg, addr);
 343
 344         npcm_sgpio_setup_enable(gpio, true);
 345
 346         addr = bank_reg(gpio, bank, EVENT_STS);
 347         reg = ioread8(addr);
 348         reg |= BIT(bit);
 349         iowrite8(reg, addr);
 350
 351         raw_spin_unlock_irqrestore(&gpio->lock, flags);
 352 }
 353
 354 static void npcm_sgpio_irq_ack(struct irq_data *d)
 355 {
 356         const struct npcm_sgpio_bank *bank;
 357         struct npcm_sgpio *gpio;
 358         unsigned long flags;
 359         void __iomem *status_addr;
 360         unsigned int offset;
 361         u8 bit;
 362
 363         npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
 364         status_addr = bank_reg(gpio, bank, EVENT_STS);
 365         raw_spin_lock_irqsave(&gpio->lock, flags);
 366         iowrite8(BIT(bit), status_addr);
 367         raw_spin_unlock_irqrestore(&gpio->lock, flags);
 368 }
 369
 370 static void npcm_sgpio_irq_mask(struct irq_data *d)
 371 {
 372         npcm_sgpio_irq_set_mask(d, true);
 373 }
 374
 375 static void npcm_sgpio_irq_unmask(struct irq_data *d)
 376 {
 377         npcm_sgpio_irq_set_mask(d, false);
 378 }
 379
 380 static int npcm_sgpio_set_type(struct irq_data *d, unsigned int type)
 381 {
 382         const struct npcm_sgpio_bank *bank;
 383         irq_flow_handler_t handler;
 384         struct npcm_sgpio *gpio;
 385         unsigned long flags;
 386         void __iomem *addr;
 387         unsigned int offset;
 388         u16 reg, val;
 389         u8 bit;
 390
 391         npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
 392
 393         switch (type & IRQ_TYPE_SENSE_MASK) {
 394         case IRQ_TYPE_EDGE_BOTH:
 395                 val = NPCM_IXOEVCFG_BOTH;
 396                 break;
 397         case IRQ_TYPE_EDGE_RISING:
 398         case IRQ_TYPE_LEVEL_HIGH:
 399                 val = NPCM_IXOEVCFG_RISING;
 400                 break;
 401         case IRQ_TYPE_EDGE_FALLING:
 402         case IRQ_TYPE_LEVEL_LOW:
 403                 val = NPCM_IXOEVCFG_FALLING;
 404                 break;
 405         default:
 406                 return -EINVAL;
 407         }
 408
 409         if (type & IRQ_TYPE_LEVEL_MASK)
 410                 handler = handle_level_irq;
 411         else
 412                 handler = handle_edge_irq;
 413
 414         gpio->int_type[offset] = val;
 415
 416         raw_spin_lock_irqsave(&gpio->lock, flags);
 417         npcm_sgpio_setup_enable(gpio, false);
 418         addr = bank_reg(gpio, bank, EVENT_CFG);
 419         reg = ioread16(addr);
 420
 421         reg |= (val << (bit * 2));
 422
 423         iowrite16(reg, addr);
 424         npcm_sgpio_setup_enable(gpio, true);
 425         raw_spin_unlock_irqrestore(&gpio->lock, flags);
 426
 427         irq_set_handler_locked(d, handler);
 428
 429         return 0;
 430 }
 431
 432 static void npcm_sgpio_irq_handler(struct irq_desc *desc)
 433 {
 434         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 435         struct irq_chip *ic = irq_desc_get_chip(desc);
 436         struct npcm_sgpio *gpio = gpiochip_get_data(gc);
 437         unsigned int i, j;
 438         unsigned long reg;
 439
 440         chained_irq_enter(ic, desc);
 441
 442         for (i = 0; i < ARRAY_SIZE(npcm_sgpio_banks); i++) {
 443                 const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];
 444
 445                 reg = ioread8(bank_reg(gpio, bank, EVENT_STS));
 446                 for_each_set_bit(j, &reg, 8)
 447                         generic_handle_domain_irq(gc->irq.domain,
 448                                                   i * 8 + gpio->nout_sgpio + j);
 449         }
 450
 451         chained_irq_exit(ic, desc);
 452 }
 453
 454 static const struct irq_chip sgpio_irq_chip = {
 455         .name = "sgpio-irq",
 456         .irq_ack = npcm_sgpio_irq_ack,
 457         .irq_mask = npcm_sgpio_irq_mask,
 458         .irq_unmask = npcm_sgpio_irq_unmask,
 459         .irq_set_type = npcm_sgpio_set_type,
 460         .flags  = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
 461         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 462 };
 463
 464 static int npcm_sgpio_setup_irqs(struct npcm_sgpio *gpio,
 465                                  struct platform_device *pdev)
 466 {
 467         int rc, i;
 468         struct gpio_irq_chip *irq;
 469
 470         rc = platform_get_irq(pdev, 0);
 471         if (rc < 0)
 472                 return rc;
 473
 474         gpio->irq = rc;
 475
 476         npcm_sgpio_setup_enable(gpio, false);
 477
 478         /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
 479         for (i = 0; i < ARRAY_SIZE(npcm_sgpio_banks); i++) {
 480                 const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];
 481
 482                 iowrite16(0, bank_reg(gpio, bank, EVENT_CFG));
 483                 iowrite8(0xff, bank_reg(gpio, bank, EVENT_STS));
 484         }
 485
 486         irq = &gpio->chip.irq;
 487         gpio_irq_chip_set_chip(irq, &sgpio_irq_chip);
 488         irq->init_valid_mask = npcm_sgpio_irq_init_valid_mask;
 489         irq->handler = handle_bad_irq;
 490         irq->default_type = IRQ_TYPE_NONE;
 491         irq->parent_handler = npcm_sgpio_irq_handler;
 492         irq->parent_handler_data = gpio;
 493         irq->parents = &gpio->irq;
 494         irq->num_parents = 1;
 495
 496         return 0;
 497 }
 498
 499 static int npcm_sgpio_probe(struct platform_device *pdev)
 500 {
 501         struct npcm_sgpio *gpio;
 502         const struct npcm_clk_cfg *clk_cfg;
 503         int rc;
 504         u32 nin_gpios, nout_gpios;
 505
 506         gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 507         if (!gpio)
 508                 return -ENOMEM;
 509
 510         gpio->base = devm_platform_ioremap_resource(pdev, 0);
 511         if (IS_ERR(gpio->base))
 512                 return PTR_ERR(gpio->base);
 513
 514         clk_cfg = device_get_match_data(&pdev->dev);
 515         if (!clk_cfg)
 516                 return -EINVAL;
 517
 518         rc = device_property_read_u32(&pdev->dev, "nuvoton,input-ngpios",
 519                                       &nin_gpios);
 520         if (rc < 0)
 521                 return dev_err_probe(&pdev->dev, rc, "Could not read ngpios property\n");
 522
 523         rc = device_property_read_u32(&pdev->dev, "nuvoton,output-ngpios",
 524                                       &nout_gpios);
 525         if (rc < 0)
 526                 return dev_err_probe(&pdev->dev, rc, "Could not read ngpios property\n");
 527
 528         gpio->nin_sgpio = nin_gpios;
 529         gpio->nout_sgpio = nout_gpios;
 530         if (gpio->nin_sgpio > MAX_NR_HW_SGPIO ||
 531             gpio->nout_sgpio > MAX_NR_HW_SGPIO)
 532                 return dev_err_probe(&pdev->dev, -EINVAL, "Number of GPIOs exceeds the maximum of %d: input: %d output: %d\n", MAX_NR_HW_SGPIO, nin_gpios, nout_gpios);
 533
 534         gpio->pclk = devm_clk_get(&pdev->dev, NULL);
 535         if (IS_ERR(gpio->pclk))
 536                 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->pclk), "Could not get pclk\n");
 537
 538         rc = npcm_sgpio_setup_clk(gpio, clk_cfg);
 539         if (rc < 0)
 540                 return dev_err_probe(&pdev->dev, rc, "Failed to setup clock\n");
 541
 542         raw_spin_lock_init(&gpio->lock);
 543         gpio->chip.parent = &pdev->dev;
 544         gpio->chip.ngpio = gpio->nin_sgpio + gpio->nout_sgpio;
 545         gpio->chip.direction_input = npcm_sgpio_dir_in;
 546         gpio->chip.direction_output = npcm_sgpio_dir_out;
 547         gpio->chip.get_direction = npcm_sgpio_get_direction;
 548         gpio->chip.get = npcm_sgpio_get;
 549         gpio->chip.set = npcm_sgpio_set;
 550         gpio->chip.label = dev_name(&pdev->dev);
 551         gpio->chip.base = -1;
 552
 553         rc = npcm_sgpio_init_port(gpio);
 554         if (rc < 0)
 555                 return rc;
 556
 557         rc = npcm_sgpio_setup_irqs(gpio, pdev);
 558         if (rc < 0)
 559                 return rc;
 560
 561         rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
 562         if (rc)
 563                 return dev_err_probe(&pdev->dev, rc, "GPIO registering failed\n");
 564
 565         npcm_sgpio_setup_enable(gpio, true);
 566
 567         return 0;
 568 }
 569
 570 static unsigned int npcm750_SFT_CLK[NPCM_750_OPT] = {
 571         1024, 32, 8, 4, 3, 2,
 572 };
 573
 574 static unsigned int npcm750_CLK_SEL[NPCM_750_OPT] = {
 575         0x00, 0x05, 0x07, 0x0C, 0x0D, 0x0E,
 576 };
 577
 578 static unsigned int npcm845_SFT_CLK[NPCM_845_OPT] = {
 579         1024, 32, 16, 8, 4,
 580 };
 581
 582 static unsigned int npcm845_CLK_SEL[NPCM_845_OPT] = {
 583         0x00, 0x05, 0x06, 0x07, 0x0C,
 584 };
 585
 586 static struct npcm_clk_cfg npcm750_sgpio_pdata = {
 587         .sft_clk = npcm750_SFT_CLK,
 588         .clk_sel = npcm750_CLK_SEL,
 589         .cfg_opt = NPCM_750_OPT,
 590 };
 591
 592 static const struct npcm_clk_cfg npcm845_sgpio_pdata = {
 593         .sft_clk = npcm845_SFT_CLK,
 594         .clk_sel = npcm845_CLK_SEL,
 595         .cfg_opt = NPCM_845_OPT,
 596 };
 597
 598 static const struct of_device_id npcm_sgpio_of_table[] = {
 599         { .compatible = "nuvoton,npcm750-sgpio", .data = &npcm750_sgpio_pdata, },
 600         { .compatible = "nuvoton,npcm845-sgpio", .data = &npcm845_sgpio_pdata, },
 601         {}
 602 };
 603 MODULE_DEVICE_TABLE(of, npcm_sgpio_of_table);
 604
 605 static struct platform_driver npcm_sgpio_driver = {
 606         .driver = {
 607                 .name = KBUILD_MODNAME,
 608                 .of_match_table = npcm_sgpio_of_table,
 609         },
 610         .probe  = npcm_sgpio_probe,
 611 };
 612 module_platform_driver(npcm_sgpio_driver);
 613
 614 MODULE_AUTHOR("Jim Liu <jjliu0@nuvoton.com>");
 615 MODULE_AUTHOR("Joseph Liu <kwliu@nuvoton.com>");
 616 MODULE_DESCRIPTION("Nuvoton NPCM Serial GPIO Driver");
 617 MODULE_LICENSE("GPL v2");