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drm/panel-edp: Add STA 116QHD024002
[drm/drm-misc.git] / drivers / hwmon / it87.c
blobe233aafa8856c94c3fde3502732fcda2bd3bf130
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
4 * monitoring.
5 *
6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
8 * addition to an Environment Controller (Enhanced Hardware Monitor and
9 * Fan Controller)
10 *
11 * This driver supports only the Environment Controller in the IT8705F and
12 * similar parts. The other devices are supported by different drivers.
13 *
14 * Supports: IT8603E Super I/O chip w/LPC interface
15 * IT8620E Super I/O chip w/LPC interface
16 * IT8622E Super I/O chip w/LPC interface
17 * IT8623E Super I/O chip w/LPC interface
18 * IT8628E Super I/O chip w/LPC interface
19 * IT8705F Super I/O chip w/LPC interface
20 * IT8712F Super I/O chip w/LPC interface
21 * IT8716F Super I/O chip w/LPC interface
22 * IT8718F Super I/O chip w/LPC interface
23 * IT8720F Super I/O chip w/LPC interface
24 * IT8721F Super I/O chip w/LPC interface
25 * IT8726F Super I/O chip w/LPC interface
26 * IT8728F Super I/O chip w/LPC interface
27 * IT8732F Super I/O chip w/LPC interface
28 * IT8758E Super I/O chip w/LPC interface
29 * IT8771E Super I/O chip w/LPC interface
30 * IT8772E Super I/O chip w/LPC interface
31 * IT8781F Super I/O chip w/LPC interface
32 * IT8782F Super I/O chip w/LPC interface
33 * IT8783E/F Super I/O chip w/LPC interface
34 * IT8786E Super I/O chip w/LPC interface
35 * IT8790E Super I/O chip w/LPC interface
36 * IT8792E Super I/O chip w/LPC interface
37 * IT87952E Super I/O chip w/LPC interface
38 * Sis950 A clone of the IT8705F
39 *
40 * Copyright (C) 2001 Chris Gauthron
41 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
42 */
43
44 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
46 #include <linux/bitops.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/slab.h>
50 #include <linux/jiffies.h>
51 #include <linux/platform_device.h>
52 #include <linux/hwmon.h>
53 #include <linux/hwmon-sysfs.h>
54 #include <linux/hwmon-vid.h>
55 #include <linux/err.h>
56 #include <linux/mutex.h>
57 #include <linux/sysfs.h>
58 #include <linux/string.h>
59 #include <linux/dmi.h>
60 #include <linux/acpi.h>
61 #include <linux/io.h>
62
63 #define DRVNAME "it87"
64
65 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
66 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
67 it8792, it8603, it8620, it8622, it8628, it87952 };
68
69 static struct platform_device *it87_pdev[2];
70
71 #define REG_2E 0x2e /* The register to read/write */
72 #define REG_4E 0x4e /* Secondary register to read/write */
73
74 #define DEV 0x07 /* Register: Logical device select */
75 #define PME 0x04 /* The device with the fan registers in it */
76
77 /* The device with the IT8718F/IT8720F VID value in it */
78 #define GPIO 0x07
79
80 #define DEVID 0x20 /* Register: Device ID */
81 #define DEVREV 0x22 /* Register: Device Revision */
82
83 static inline void __superio_enter(int ioreg)
84 {
85 outb(0x87, ioreg);
86 outb(0x01, ioreg);
87 outb(0x55, ioreg);
88 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
89 }
90
91 static inline int superio_inb(int ioreg, int reg)
92 {
93 outb(reg, ioreg);
94 return inb(ioreg + 1);
95 }
96
97 static inline void superio_outb(int ioreg, int reg, int val)
98 {
99 outb(reg, ioreg);
100 outb(val, ioreg + 1);
101 }
102
103 static int superio_inw(int ioreg, int reg)
104 {
105 int val;
106
107 outb(reg++, ioreg);
108 val = inb(ioreg + 1) << 8;
109 outb(reg, ioreg);
110 val |= inb(ioreg + 1);
111 return val;
112 }
113
114 static inline void superio_select(int ioreg, int ldn)
115 {
116 outb(DEV, ioreg);
117 outb(ldn, ioreg + 1);
118 }
119
120 static inline int superio_enter(int ioreg, bool noentry)
121 {
122 /*
123 * Try to reserve ioreg and ioreg + 1 for exclusive access.
124 */
125 if (!request_muxed_region(ioreg, 2, DRVNAME))
126 return -EBUSY;
127
128 if (!noentry)
129 __superio_enter(ioreg);
130 return 0;
131 }
132
133 static inline void superio_exit(int ioreg, bool noexit)
134 {
135 if (!noexit) {
136 outb(0x02, ioreg);
137 outb(0x02, ioreg + 1);
138 }
139 release_region(ioreg, 2);
140 }
141
142 /* Logical device 4 registers */
143 #define IT8712F_DEVID 0x8712
144 #define IT8705F_DEVID 0x8705
145 #define IT8716F_DEVID 0x8716
146 #define IT8718F_DEVID 0x8718
147 #define IT8720F_DEVID 0x8720
148 #define IT8721F_DEVID 0x8721
149 #define IT8726F_DEVID 0x8726
150 #define IT8728F_DEVID 0x8728
151 #define IT8732F_DEVID 0x8732
152 #define IT8792E_DEVID 0x8733
153 #define IT8771E_DEVID 0x8771
154 #define IT8772E_DEVID 0x8772
155 #define IT8781F_DEVID 0x8781
156 #define IT8782F_DEVID 0x8782
157 #define IT8783E_DEVID 0x8783
158 #define IT8786E_DEVID 0x8786
159 #define IT8790E_DEVID 0x8790
160 #define IT8603E_DEVID 0x8603
161 #define IT8620E_DEVID 0x8620
162 #define IT8622E_DEVID 0x8622
163 #define IT8623E_DEVID 0x8623
164 #define IT8628E_DEVID 0x8628
165 #define IT87952E_DEVID 0x8695
166
167 /* Logical device 4 (Environmental Monitor) registers */
168 #define IT87_ACT_REG 0x30
169 #define IT87_BASE_REG 0x60
170 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
171
172 /* Logical device 7 registers (IT8712F and later) */
173 #define IT87_SIO_GPIO1_REG 0x25
174 #define IT87_SIO_GPIO2_REG 0x26
175 #define IT87_SIO_GPIO3_REG 0x27
176 #define IT87_SIO_GPIO4_REG 0x28
177 #define IT87_SIO_GPIO5_REG 0x29
178 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
179 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
180 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
181 #define IT87_SIO_VID_REG 0xfc /* VID value */
182 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
183
184 /* Force chip IDs to specified values. Should only be used for testing */
185 static unsigned short force_id[2];
186 static unsigned int force_id_cnt;
187
188 /* ACPI resource conflicts are ignored if this parameter is set to 1 */
189 static bool ignore_resource_conflict;
190
191 /* Update battery voltage after every reading if true */
192 static bool update_vbat;
193
194 /* Not all BIOSes properly configure the PWM registers */
195 static bool fix_pwm_polarity;
196
197 /* Many IT87 constants specified below */
198
199 /* Length of ISA address segment */
200 #define IT87_EXTENT 8
201
202 /* Length of ISA address segment for Environmental Controller */
203 #define IT87_EC_EXTENT 2
204
205 /* Offset of EC registers from ISA base address */
206 #define IT87_EC_OFFSET 5
207
208 /* Where are the ISA address/data registers relative to the EC base address */
209 #define IT87_ADDR_REG_OFFSET 0
210 #define IT87_DATA_REG_OFFSET 1
211
212 /*----- The IT87 registers -----*/
213
214 #define IT87_REG_CONFIG 0x00
215
216 #define IT87_REG_ALARM1 0x01
217 #define IT87_REG_ALARM2 0x02
218 #define IT87_REG_ALARM3 0x03
219
220 /*
221 * The IT8718F and IT8720F have the VID value in a different register, in
222 * Super-I/O configuration space.
223 */
224 #define IT87_REG_VID 0x0a
225
226 /* Interface Selection register on other chips */
227 #define IT87_REG_IFSEL 0x0a
228
229 /*
230 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
231 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
232 * mode.
233 */
234 #define IT87_REG_FAN_DIV 0x0b
235 #define IT87_REG_FAN_16BIT 0x0c
236
237 /*
238 * Monitors:
239 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
240 * - up to 6 temp (1 to 6)
241 * - up to 6 fan (1 to 6)
242 */
243
244 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
245 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
246 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
247 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
248 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
249
250 #define IT87_REG_FAN_MAIN_CTRL 0x13
251 #define IT87_REG_FAN_CTL 0x14
252 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
253 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
254
255 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
256 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
257
258 #define IT87_REG_TEMP(nr) (0x29 + (nr))
259
260 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
261 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
262 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
263 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
264
265 #define IT87_REG_VIN_ENABLE 0x50
266 #define IT87_REG_TEMP_ENABLE 0x51
267 #define IT87_REG_TEMP_EXTRA 0x55
268 #define IT87_REG_BEEP_ENABLE 0x5c
269
270 #define IT87_REG_CHIPID 0x58
271
272 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
273
274 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
275 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
276
277 #define IT87_REG_TEMP456_ENABLE 0x77
278
279 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
280 #define NUM_VIN_LIMIT 8
281 #define NUM_TEMP 6
282 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
283 #define NUM_TEMP_LIMIT 3
284 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
285 #define NUM_FAN_DIV 3
286 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
287 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
288
289 struct it87_devices {
290 const char *name;
291 const char * const model;
292 u32 features;
293 u8 peci_mask;
294 u8 old_peci_mask;
295 u8 smbus_bitmap; /* SMBus enable bits in extra config register */
296 u8 ec_special_config;
297 };
298
299 #define FEAT_12MV_ADC BIT(0)
300 #define FEAT_NEWER_AUTOPWM BIT(1)
301 #define FEAT_OLD_AUTOPWM BIT(2)
302 #define FEAT_16BIT_FANS BIT(3)
303 #define FEAT_TEMP_OFFSET BIT(4)
304 #define FEAT_TEMP_PECI BIT(5)
305 #define FEAT_TEMP_OLD_PECI BIT(6)
306 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
307 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
308 #define FEAT_VID BIT(9) /* Set if chip supports VID */
309 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
310 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
311 #define FEAT_10_9MV_ADC BIT(12)
312 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
313 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
314 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
315 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
316 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
317 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
318 /*
319 * Disabling configuration mode on some chips can result in system
320 * hang-ups and access failures to the Super-IO chip at the
321 * second SIO address. Never exit configuration mode on these
322 * chips to avoid the problem.
323 */
324 #define FEAT_NOCONF BIT(19) /* Chip conf mode enabled on startup */
325 #define FEAT_FOUR_FANS BIT(20) /* Supports four fans */
326 #define FEAT_FOUR_PWM BIT(21) /* Supports four fan controls */
327 #define FEAT_FOUR_TEMP BIT(22)
328 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
329
330 static const struct it87_devices it87_devices[] = {
331 [it87] = {
332 .name = "it87",
333 .model = "IT87F",
334 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
335 /* may need to overwrite */
336 },
337 [it8712] = {
338 .name = "it8712",
339 .model = "IT8712F",
340 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
341 /* may need to overwrite */
342 },
343 [it8716] = {
344 .name = "it8716",
345 .model = "IT8716F",
346 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
347 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
348 | FEAT_FANCTL_ONOFF,
349 },
350 [it8718] = {
351 .name = "it8718",
352 .model = "IT8718F",
353 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
354 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
355 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
356 .old_peci_mask = 0x4,
357 },
358 [it8720] = {
359 .name = "it8720",
360 .model = "IT8720F",
361 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
362 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
363 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
364 .old_peci_mask = 0x4,
365 },
366 [it8721] = {
367 .name = "it8721",
368 .model = "IT8721F",
369 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
370 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
371 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
372 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
373 .peci_mask = 0x05,
374 .old_peci_mask = 0x02, /* Actually reports PCH */
375 },
376 [it8728] = {
377 .name = "it8728",
378 .model = "IT8728F",
379 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
380 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
381 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
382 | FEAT_FANCTL_ONOFF,
383 .peci_mask = 0x07,
384 },
385 [it8732] = {
386 .name = "it8732",
387 .model = "IT8732F",
388 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
389 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
390 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
391 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
392 .peci_mask = 0x07,
393 .old_peci_mask = 0x02, /* Actually reports PCH */
394 },
395 [it8771] = {
396 .name = "it8771",
397 .model = "IT8771E",
398 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
399 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
400 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
401 /* PECI: guesswork */
402 /* 12mV ADC (OHM) */
403 /* 16 bit fans (OHM) */
404 /* three fans, always 16 bit (guesswork) */
405 .peci_mask = 0x07,
406 },
407 [it8772] = {
408 .name = "it8772",
409 .model = "IT8772E",
410 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
411 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
412 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
413 /* PECI (coreboot) */
414 /* 12mV ADC (HWSensors4, OHM) */
415 /* 16 bit fans (HWSensors4, OHM) */
416 /* three fans, always 16 bit (datasheet) */
417 .peci_mask = 0x07,
418 },
419 [it8781] = {
420 .name = "it8781",
421 .model = "IT8781F",
422 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
423 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
424 | FEAT_FANCTL_ONOFF,
425 .old_peci_mask = 0x4,
426 },
427 [it8782] = {
428 .name = "it8782",
429 .model = "IT8782F",
430 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
431 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
432 | FEAT_FANCTL_ONOFF,
433 .old_peci_mask = 0x4,
434 },
435 [it8783] = {
436 .name = "it8783",
437 .model = "IT8783E/F",
438 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
439 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
440 | FEAT_FANCTL_ONOFF,
441 .old_peci_mask = 0x4,
442 },
443 [it8786] = {
444 .name = "it8786",
445 .model = "IT8786E",
446 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
447 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
448 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
449 .peci_mask = 0x07,
450 },
451 [it8790] = {
452 .name = "it8790",
453 .model = "IT8790E",
454 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
455 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
456 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF | FEAT_NOCONF,
457 .peci_mask = 0x07,
458 },
459 [it8792] = {
460 .name = "it8792",
461 .model = "IT8792E/IT8795E",
462 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
463 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
464 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF
465 | FEAT_NOCONF,
466 .peci_mask = 0x07,
467 .old_peci_mask = 0x02, /* Actually reports PCH */
468 },
469 [it8603] = {
470 .name = "it8603",
471 .model = "IT8603E",
472 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
473 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
474 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
475 .peci_mask = 0x07,
476 },
477 [it8620] = {
478 .name = "it8620",
479 .model = "IT8620E",
480 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
481 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
482 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
483 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF,
484 .peci_mask = 0x07,
485 },
486 [it8622] = {
487 .name = "it8622",
488 .model = "IT8622E",
489 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
490 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
491 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
492 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_FOUR_TEMP,
493 .peci_mask = 0x07,
494 .smbus_bitmap = BIT(1) | BIT(2),
495 },
496 [it8628] = {
497 .name = "it8628",
498 .model = "IT8628E",
499 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
500 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
501 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
502 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF,
503 .peci_mask = 0x07,
504 },
505 [it87952] = {
506 .name = "it87952",
507 .model = "IT87952E",
508 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
509 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
510 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF
511 | FEAT_NOCONF,
512 .peci_mask = 0x07,
513 .old_peci_mask = 0x02, /* Actually reports PCH */
514 },
515 };
516
517 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
518 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
519 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
520 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
521 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
522 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
523 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
524 ((data)->peci_mask & BIT(nr)))
525 #define has_temp_old_peci(data, nr) \
526 (((data)->features & FEAT_TEMP_OLD_PECI) && \
527 ((data)->old_peci_mask & BIT(nr)))
528 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
529 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
530 FEAT_FIVE_FANS | \
531 FEAT_SIX_FANS))
532 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
533 FEAT_SIX_FANS))
534 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
535 #define has_vid(data) ((data)->features & FEAT_VID)
536 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
537 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
538 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
539 FEAT_FIVE_PWM | \
540 FEAT_SIX_PWM))
541 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM | \
542 FEAT_SIX_PWM))
543 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
544 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
545 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP)
546 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
547 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
548 #define has_noconf(data) ((data)->features & FEAT_NOCONF)
549 #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \
550 FEAT_10_9MV_ADC))
551 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
552
553 struct it87_sio_data {
554 int sioaddr;
555 enum chips type;
556 /* Values read from Super-I/O config space */
557 u8 revision;
558 u8 vid_value;
559 u8 beep_pin;
560 u8 internal; /* Internal sensors can be labeled */
561 bool need_in7_reroute;
562 /* Features skipped based on config or DMI */
563 u16 skip_in;
564 u8 skip_vid;
565 u8 skip_fan;
566 u8 skip_pwm;
567 u8 skip_temp;
568 u8 smbus_bitmap;
569 u8 ec_special_config;
570 };
571
572 /*
573 * For each registered chip, we need to keep some data in memory.
574 * The structure is dynamically allocated.
575 */
576 struct it87_data {
577 const struct attribute_group *groups[7];
578 int sioaddr;
579 enum chips type;
580 u32 features;
581 u8 peci_mask;
582 u8 old_peci_mask;
583
584 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
585 u8 ec_special_config; /* EC special config register restore value */
586
587 unsigned short addr;
588 const char *name;
589 struct mutex update_lock;
590 bool valid; /* true if following fields are valid */
591 unsigned long last_updated; /* In jiffies */
592
593 u16 in_scaled; /* Internal voltage sensors are scaled */
594 u16 in_internal; /* Bitfield, internal sensors (for labels) */
595 u16 has_in; /* Bitfield, voltage sensors enabled */
596 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
597 bool need_in7_reroute;
598 u8 has_fan; /* Bitfield, fans enabled */
599 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
600 u8 has_temp; /* Bitfield, temp sensors enabled */
601 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
602 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
603 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
604 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
605 bool has_vid; /* True if VID supported */
606 u8 vid; /* Register encoding, combined */
607 u8 vrm;
608 u32 alarms; /* Register encoding, combined */
609 bool has_beep; /* true if beep supported */
610 u8 beeps; /* Register encoding */
611 u8 fan_main_ctrl; /* Register value */
612 u8 fan_ctl; /* Register value */
613
614 /*
615 * The following 3 arrays correspond to the same registers up to
616 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
617 * 7, and we want to preserve settings on mode changes, so we have
618 * to track all values separately.
619 * Starting with the IT8721F, the manual PWM duty cycles are stored
620 * in separate registers (8-bit values), so the separate tracking
621 * is no longer needed, but it is still done to keep the driver
622 * simple.
623 */
624 u8 has_pwm; /* Bitfield, pwm control enabled */
625 u8 pwm_ctrl[NUM_PWM]; /* Register value */
626 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
627 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
628
629 /* Automatic fan speed control registers */
630 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
631 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
632 };
633
634 /* Board specific settings from DMI matching */
635 struct it87_dmi_data {
636 u8 skip_pwm; /* pwm channels to skip for this board */
637 };
638
639 /* Global for results from DMI matching, if needed */
640 static struct it87_dmi_data *dmi_data;
641
642 static int adc_lsb(const struct it87_data *data, int nr)
643 {
644 int lsb;
645
646 if (has_12mv_adc(data))
647 lsb = 120;
648 else if (has_10_9mv_adc(data))
649 lsb = 109;
650 else
651 lsb = 160;
652 if (data->in_scaled & BIT(nr))
653 lsb <<= 1;
654 return lsb;
655 }
656
657 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
658 {
659 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
660 return clamp_val(val, 0, 255);
661 }
662
663 static int in_from_reg(const struct it87_data *data, int nr, int val)
664 {
665 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
666 }
667
668 static inline u8 FAN_TO_REG(long rpm, int div)
669 {
670 if (rpm == 0)
671 return 255;
672 rpm = clamp_val(rpm, 1, 1000000);
673 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
674 }
675
676 static inline u16 FAN16_TO_REG(long rpm)
677 {
678 if (rpm == 0)
679 return 0xffff;
680 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
681 }
682
683 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
684 1350000 / ((val) * (div)))
685 /* The divider is fixed to 2 in 16-bit mode */
686 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
687 1350000 / ((val) * 2))
688
689 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
690 ((val) + 500) / 1000), -128, 127))
691 #define TEMP_FROM_REG(val) ((val) * 1000)
692
693 static u8 pwm_to_reg(const struct it87_data *data, long val)
694 {
695 if (has_newer_autopwm(data))
696 return val;
697 else
698 return val >> 1;
699 }
700
701 static int pwm_from_reg(const struct it87_data *data, u8 reg)
702 {
703 if (has_newer_autopwm(data))
704 return reg;
705 else
706 return (reg & 0x7f) << 1;
707 }
708
709 static int DIV_TO_REG(int val)
710 {
711 int answer = 0;
712
713 while (answer < 7 && (val >>= 1))
714 answer++;
715 return answer;
716 }
717
718 #define DIV_FROM_REG(val) BIT(val)
719
720 /*
721 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
722 * depending on the chip type, to calculate the actual PWM frequency.
723 *
724 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
725 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
726 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
727 * sometimes just one. It is unknown if this is a datasheet error or real,
728 * so this is ignored for now.
729 */
730 static const unsigned int pwm_freq[8] = {
731 48000000,
732 24000000,
733 12000000,
734 8000000,
735 6000000,
736 3000000,
737 1500000,
738 750000,
739 };
740
741 static int smbus_disable(struct it87_data *data)
742 {
743 int err;
744
745 if (data->smbus_bitmap) {
746 err = superio_enter(data->sioaddr, has_noconf(data));
747 if (err)
748 return err;
749 superio_select(data->sioaddr, PME);
750 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
751 data->ec_special_config & ~data->smbus_bitmap);
752 superio_exit(data->sioaddr, has_noconf(data));
753 }
754 return 0;
755 }
756
757 static int smbus_enable(struct it87_data *data)
758 {
759 int err;
760
761 if (data->smbus_bitmap) {
762 err = superio_enter(data->sioaddr, has_noconf(data));
763 if (err)
764 return err;
765
766 superio_select(data->sioaddr, PME);
767 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
768 data->ec_special_config);
769 superio_exit(data->sioaddr, has_noconf(data));
770 }
771 return 0;
772 }
773
774 /*
775 * Must be called with data->update_lock held, except during initialization.
776 * Must be called with SMBus accesses disabled.
777 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
778 * would slow down the IT87 access and should not be necessary.
779 */
780 static int it87_read_value(struct it87_data *data, u8 reg)
781 {
782 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
783 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
784 }
785
786 /*
787 * Must be called with data->update_lock held, except during initialization.
788 * Must be called with SMBus accesses disabled.
789 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
790 * would slow down the IT87 access and should not be necessary.
791 */
792 static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
793 {
794 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
795 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
796 }
797
798 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
799 {
800 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
801 if (has_newer_autopwm(data)) {
802 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
803 data->pwm_duty[nr] = it87_read_value(data,
804 IT87_REG_PWM_DUTY[nr]);
805 } else {
806 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
807 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
808 else /* Manual mode */
809 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
810 }
811
812 if (has_old_autopwm(data)) {
813 int i;
814
815 for (i = 0; i < 5 ; i++)
816 data->auto_temp[nr][i] = it87_read_value(data,
817 IT87_REG_AUTO_TEMP(nr, i));
818 for (i = 0; i < 3 ; i++)
819 data->auto_pwm[nr][i] = it87_read_value(data,
820 IT87_REG_AUTO_PWM(nr, i));
821 } else if (has_newer_autopwm(data)) {
822 int i;
823
824 /*
825 * 0: temperature hysteresis (base + 5)
826 * 1: fan off temperature (base + 0)
827 * 2: fan start temperature (base + 1)
828 * 3: fan max temperature (base + 2)
829 */
830 data->auto_temp[nr][0] =
831 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
832
833 for (i = 0; i < 3 ; i++)
834 data->auto_temp[nr][i + 1] =
835 it87_read_value(data,
836 IT87_REG_AUTO_TEMP(nr, i));
837 /*
838 * 0: start pwm value (base + 3)
839 * 1: pwm slope (base + 4, 1/8th pwm)
840 */
841 data->auto_pwm[nr][0] =
842 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
843 data->auto_pwm[nr][1] =
844 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
845 }
846 }
847
848 static int it87_lock(struct it87_data *data)
849 {
850 int err;
851
852 mutex_lock(&data->update_lock);
853 err = smbus_disable(data);
854 if (err)
855 mutex_unlock(&data->update_lock);
856 return err;
857 }
858
859 static void it87_unlock(struct it87_data *data)
860 {
861 smbus_enable(data);
862 mutex_unlock(&data->update_lock);
863 }
864
865 static struct it87_data *it87_update_device(struct device *dev)
866 {
867 struct it87_data *data = dev_get_drvdata(dev);
868 struct it87_data *ret = data;
869 int err;
870 int i;
871
872 mutex_lock(&data->update_lock);
873
874 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
875 !data->valid) {
876 err = smbus_disable(data);
877 if (err) {
878 ret = ERR_PTR(err);
879 goto unlock;
880 }
881 if (update_vbat) {
882 /*
883 * Cleared after each update, so reenable. Value
884 * returned by this read will be previous value
885 */
886 it87_write_value(data, IT87_REG_CONFIG,
887 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
888 }
889 for (i = 0; i < NUM_VIN; i++) {
890 if (!(data->has_in & BIT(i)))
891 continue;
892
893 data->in[i][0] =
894 it87_read_value(data, IT87_REG_VIN[i]);
895
896 /* VBAT and AVCC don't have limit registers */
897 if (i >= NUM_VIN_LIMIT)
898 continue;
899
900 data->in[i][1] =
901 it87_read_value(data, IT87_REG_VIN_MIN(i));
902 data->in[i][2] =
903 it87_read_value(data, IT87_REG_VIN_MAX(i));
904 }
905
906 for (i = 0; i < NUM_FAN; i++) {
907 /* Skip disabled fans */
908 if (!(data->has_fan & BIT(i)))
909 continue;
910
911 data->fan[i][1] =
912 it87_read_value(data, IT87_REG_FAN_MIN[i]);
913 data->fan[i][0] = it87_read_value(data,
914 IT87_REG_FAN[i]);
915 /* Add high byte if in 16-bit mode */
916 if (has_16bit_fans(data)) {
917 data->fan[i][0] |= it87_read_value(data,
918 IT87_REG_FANX[i]) << 8;
919 data->fan[i][1] |= it87_read_value(data,
920 IT87_REG_FANX_MIN[i]) << 8;
921 }
922 }
923 for (i = 0; i < NUM_TEMP; i++) {
924 if (!(data->has_temp & BIT(i)))
925 continue;
926 data->temp[i][0] =
927 it87_read_value(data, IT87_REG_TEMP(i));
928
929 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
930 data->temp[i][3] =
931 it87_read_value(data,
932 IT87_REG_TEMP_OFFSET[i]);
933
934 if (i >= NUM_TEMP_LIMIT)
935 continue;
936
937 data->temp[i][1] =
938 it87_read_value(data, IT87_REG_TEMP_LOW(i));
939 data->temp[i][2] =
940 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
941 }
942
943 /* Newer chips don't have clock dividers */
944 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
945 i = it87_read_value(data, IT87_REG_FAN_DIV);
946 data->fan_div[0] = i & 0x07;
947 data->fan_div[1] = (i >> 3) & 0x07;
948 data->fan_div[2] = (i & 0x40) ? 3 : 1;
949 }
950
951 data->alarms =
952 it87_read_value(data, IT87_REG_ALARM1) |
953 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
954 (it87_read_value(data, IT87_REG_ALARM3) << 16);
955 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
956
957 data->fan_main_ctrl = it87_read_value(data,
958 IT87_REG_FAN_MAIN_CTRL);
959 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
960 for (i = 0; i < NUM_PWM; i++) {
961 if (!(data->has_pwm & BIT(i)))
962 continue;
963 it87_update_pwm_ctrl(data, i);
964 }
965
966 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
967 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
968 /*
969 * The IT8705F does not have VID capability.
970 * The IT8718F and later don't use IT87_REG_VID for the
971 * same purpose.
972 */
973 if (data->type == it8712 || data->type == it8716) {
974 data->vid = it87_read_value(data, IT87_REG_VID);
975 /*
976 * The older IT8712F revisions had only 5 VID pins,
977 * but we assume it is always safe to read 6 bits.
978 */
979 data->vid &= 0x3f;
980 }
981 data->last_updated = jiffies;
982 data->valid = true;
983 smbus_enable(data);
984 }
985 unlock:
986 mutex_unlock(&data->update_lock);
987 return ret;
988 }
989
990 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
991 char *buf)
992 {
993 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
994 struct it87_data *data = it87_update_device(dev);
995 int index = sattr->index;
996 int nr = sattr->nr;
997
998 if (IS_ERR(data))
999 return PTR_ERR(data);
1000
1001 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1002 }
1003
1004 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1005 const char *buf, size_t count)
1006 {
1007 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1008 struct it87_data *data = dev_get_drvdata(dev);
1009 int index = sattr->index;
1010 int nr = sattr->nr;
1011 unsigned long val;
1012 int err;
1013
1014 if (kstrtoul(buf, 10, &val) < 0)
1015 return -EINVAL;
1016
1017 err = it87_lock(data);
1018 if (err)
1019 return err;
1020
1021 data->in[nr][index] = in_to_reg(data, nr, val);
1022 it87_write_value(data,
1023 index == 1 ? IT87_REG_VIN_MIN(nr)
1024 : IT87_REG_VIN_MAX(nr),
1025 data->in[nr][index]);
1026 it87_unlock(data);
1027 return count;
1028 }
1029
1030 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1031 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1032 0, 1);
1033 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1034 0, 2);
1035
1036 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1037 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1038 1, 1);
1039 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1040 1, 2);
1041
1042 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1043 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1044 2, 1);
1045 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1046 2, 2);
1047
1048 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1049 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1050 3, 1);
1051 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1052 3, 2);
1053
1054 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1055 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1056 4, 1);
1057 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1058 4, 2);
1059
1060 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1061 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1062 5, 1);
1063 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1064 5, 2);
1065
1066 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1067 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1068 6, 1);
1069 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1070 6, 2);
1071
1072 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1073 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1074 7, 1);
1075 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1076 7, 2);
1077
1078 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1079 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1080 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1081 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1082 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1083
1084 /* Up to 6 temperatures */
1085 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1086 char *buf)
1087 {
1088 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1089 int nr = sattr->nr;
1090 int index = sattr->index;
1091 struct it87_data *data = it87_update_device(dev);
1092
1093 if (IS_ERR(data))
1094 return PTR_ERR(data);
1095
1096 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1097 }
1098
1099 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1100 const char *buf, size_t count)
1101 {
1102 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1103 int nr = sattr->nr;
1104 int index = sattr->index;
1105 struct it87_data *data = dev_get_drvdata(dev);
1106 long val;
1107 u8 reg, regval;
1108 int err;
1109
1110 if (kstrtol(buf, 10, &val) < 0)
1111 return -EINVAL;
1112
1113 err = it87_lock(data);
1114 if (err)
1115 return err;
1116
1117 switch (index) {
1118 default:
1119 case 1:
1120 reg = IT87_REG_TEMP_LOW(nr);
1121 break;
1122 case 2:
1123 reg = IT87_REG_TEMP_HIGH(nr);
1124 break;
1125 case 3:
1126 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1127 if (!(regval & 0x80)) {
1128 regval |= 0x80;
1129 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1130 }
1131 data->valid = false;
1132 reg = IT87_REG_TEMP_OFFSET[nr];
1133 break;
1134 }
1135
1136 data->temp[nr][index] = TEMP_TO_REG(val);
1137 it87_write_value(data, reg, data->temp[nr][index]);
1138 it87_unlock(data);
1139 return count;
1140 }
1141
1142 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1143 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1144 0, 1);
1145 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1146 0, 2);
1147 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1148 set_temp, 0, 3);
1149 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1150 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1151 1, 1);
1152 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1153 1, 2);
1154 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1155 set_temp, 1, 3);
1156 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1157 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1158 2, 1);
1159 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1160 2, 2);
1161 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1162 set_temp, 2, 3);
1163 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1164 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1165 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1166
1167 static int get_temp_type(struct it87_data *data, int index)
1168 {
1169 /*
1170 * 2 is deprecated;
1171 * 3 = thermal diode;
1172 * 4 = thermistor;
1173 * 5 = AMDTSI;
1174 * 6 = Intel PECI;
1175 * 0 = disabled
1176 */
1177 u8 reg, extra;
1178 int ttype, type = 0;
1179
1180 /* Detect PECI vs. AMDTSI */
1181 ttype = 6;
1182 if ((has_temp_peci(data, index)) || data->type == it8721 ||
1183 data->type == it8720) {
1184 extra = it87_read_value(data, IT87_REG_IFSEL);
1185 if ((extra & 0x70) == 0x40)
1186 ttype = 5;
1187 }
1188
1189 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1190
1191 /* Per chip special detection */
1192 switch (data->type) {
1193 case it8622:
1194 if (!(reg & 0xc0) && index == 3)
1195 type = ttype;
1196 break;
1197 default:
1198 break;
1199 }
1200
1201 if (type || index >= 3)
1202 return type;
1203
1204 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1205
1206 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1207 (has_temp_old_peci(data, index) && (extra & 0x80)))
1208 type = ttype; /* Intel PECI or AMDTSI */
1209 else if (reg & BIT(index))
1210 type = 3; /* thermal diode */
1211 else if (reg & BIT(index + 3))
1212 type = 4; /* thermistor */
1213
1214 return type;
1215 }
1216
1217 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1218 char *buf)
1219 {
1220 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1221 struct it87_data *data = it87_update_device(dev);
1222
1223 if (IS_ERR(data))
1224 return PTR_ERR(data);
1225
1226 return sprintf(buf, "%d\n", get_temp_type(data, sensor_attr->index));
1227 }
1228
1229 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1230 const char *buf, size_t count)
1231 {
1232 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1233 int nr = sensor_attr->index;
1234
1235 struct it87_data *data = dev_get_drvdata(dev);
1236 long val;
1237 u8 reg, extra;
1238 int err;
1239
1240 if (kstrtol(buf, 10, &val) < 0)
1241 return -EINVAL;
1242
1243 err = it87_lock(data);
1244 if (err)
1245 return err;
1246
1247 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1248 reg &= ~(1 << nr);
1249 reg &= ~(8 << nr);
1250 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1251 reg &= 0x3f;
1252 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1253 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1254 extra &= 0x7f;
1255 if (val == 2) { /* backwards compatibility */
1256 dev_warn(dev,
1257 "Sensor type 2 is deprecated, please use 4 instead\n");
1258 val = 4;
1259 }
1260 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1261 if (val == 3)
1262 reg |= 1 << nr;
1263 else if (val == 4)
1264 reg |= 8 << nr;
1265 else if (has_temp_peci(data, nr) && val == 6)
1266 reg |= (nr + 1) << 6;
1267 else if (has_temp_old_peci(data, nr) && val == 6)
1268 extra |= 0x80;
1269 else if (val != 0) {
1270 count = -EINVAL;
1271 goto unlock;
1272 }
1273
1274 data->sensor = reg;
1275 data->extra = extra;
1276 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1277 if (has_temp_old_peci(data, nr))
1278 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1279 data->valid = false; /* Force cache refresh */
1280 unlock:
1281 it87_unlock(data);
1282 return count;
1283 }
1284
1285 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1286 set_temp_type, 0);
1287 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1288 set_temp_type, 1);
1289 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1290 set_temp_type, 2);
1291
1292 /* 6 Fans */
1293
1294 static int pwm_mode(const struct it87_data *data, int nr)
1295 {
1296 if (has_fanctl_onoff(data) && nr < 3 &&
1297 !(data->fan_main_ctrl & BIT(nr)))
1298 return 0; /* Full speed */
1299 if (data->pwm_ctrl[nr] & 0x80)
1300 return 2; /* Automatic mode */
1301 if ((!has_fanctl_onoff(data) || nr >= 3) &&
1302 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1303 return 0; /* Full speed */
1304
1305 return 1; /* Manual mode */
1306 }
1307
1308 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1309 char *buf)
1310 {
1311 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1312 int nr = sattr->nr;
1313 int index = sattr->index;
1314 int speed;
1315 struct it87_data *data = it87_update_device(dev);
1316
1317 if (IS_ERR(data))
1318 return PTR_ERR(data);
1319
1320 speed = has_16bit_fans(data) ?
1321 FAN16_FROM_REG(data->fan[nr][index]) :
1322 FAN_FROM_REG(data->fan[nr][index],
1323 DIV_FROM_REG(data->fan_div[nr]));
1324 return sprintf(buf, "%d\n", speed);
1325 }
1326
1327 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1328 char *buf)
1329 {
1330 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1331 struct it87_data *data = it87_update_device(dev);
1332 int nr = sensor_attr->index;
1333
1334 if (IS_ERR(data))
1335 return PTR_ERR(data);
1336
1337 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1338 }
1339
1340 static ssize_t show_pwm_enable(struct device *dev,
1341 struct device_attribute *attr, char *buf)
1342 {
1343 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1344 struct it87_data *data = it87_update_device(dev);
1345 int nr = sensor_attr->index;
1346
1347 if (IS_ERR(data))
1348 return PTR_ERR(data);
1349
1350 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1351 }
1352
1353 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1354 char *buf)
1355 {
1356 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1357 struct it87_data *data = it87_update_device(dev);
1358 int nr = sensor_attr->index;
1359
1360 if (IS_ERR(data))
1361 return PTR_ERR(data);
1362
1363 return sprintf(buf, "%d\n",
1364 pwm_from_reg(data, data->pwm_duty[nr]));
1365 }
1366
1367 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1368 char *buf)
1369 {
1370 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1371 struct it87_data *data = it87_update_device(dev);
1372 int nr = sensor_attr->index;
1373 unsigned int freq;
1374 int index;
1375
1376 if (IS_ERR(data))
1377 return PTR_ERR(data);
1378
1379 if (has_pwm_freq2(data) && nr == 1)
1380 index = (data->extra >> 4) & 0x07;
1381 else
1382 index = (data->fan_ctl >> 4) & 0x07;
1383
1384 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1385
1386 return sprintf(buf, "%u\n", freq);
1387 }
1388
1389 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1390 const char *buf, size_t count)
1391 {
1392 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1393 int nr = sattr->nr;
1394 int index = sattr->index;
1395
1396 struct it87_data *data = dev_get_drvdata(dev);
1397 long val;
1398 int err;
1399 u8 reg;
1400
1401 if (kstrtol(buf, 10, &val) < 0)
1402 return -EINVAL;
1403
1404 err = it87_lock(data);
1405 if (err)
1406 return err;
1407
1408 if (has_16bit_fans(data)) {
1409 data->fan[nr][index] = FAN16_TO_REG(val);
1410 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1411 data->fan[nr][index] & 0xff);
1412 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1413 data->fan[nr][index] >> 8);
1414 } else {
1415 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1416 switch (nr) {
1417 case 0:
1418 data->fan_div[nr] = reg & 0x07;
1419 break;
1420 case 1:
1421 data->fan_div[nr] = (reg >> 3) & 0x07;
1422 break;
1423 case 2:
1424 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1425 break;
1426 }
1427 data->fan[nr][index] =
1428 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1429 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1430 data->fan[nr][index]);
1431 }
1432
1433 it87_unlock(data);
1434 return count;
1435 }
1436
1437 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1438 const char *buf, size_t count)
1439 {
1440 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1441 struct it87_data *data = dev_get_drvdata(dev);
1442 int nr = sensor_attr->index;
1443 unsigned long val;
1444 int min, err;
1445 u8 old;
1446
1447 if (kstrtoul(buf, 10, &val) < 0)
1448 return -EINVAL;
1449
1450 err = it87_lock(data);
1451 if (err)
1452 return err;
1453
1454 old = it87_read_value(data, IT87_REG_FAN_DIV);
1455
1456 /* Save fan min limit */
1457 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1458
1459 switch (nr) {
1460 case 0:
1461 case 1:
1462 data->fan_div[nr] = DIV_TO_REG(val);
1463 break;
1464 case 2:
1465 if (val < 8)
1466 data->fan_div[nr] = 1;
1467 else
1468 data->fan_div[nr] = 3;
1469 }
1470 val = old & 0x80;
1471 val |= (data->fan_div[0] & 0x07);
1472 val |= (data->fan_div[1] & 0x07) << 3;
1473 if (data->fan_div[2] == 3)
1474 val |= 0x1 << 6;
1475 it87_write_value(data, IT87_REG_FAN_DIV, val);
1476
1477 /* Restore fan min limit */
1478 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1479 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
1480
1481 it87_unlock(data);
1482 return count;
1483 }
1484
1485 /* Returns 0 if OK, -EINVAL otherwise */
1486 static int check_trip_points(struct device *dev, int nr)
1487 {
1488 const struct it87_data *data = dev_get_drvdata(dev);
1489 int i, err = 0;
1490
1491 if (has_old_autopwm(data)) {
1492 for (i = 0; i < 3; i++) {
1493 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1494 err = -EINVAL;
1495 }
1496 for (i = 0; i < 2; i++) {
1497 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1498 err = -EINVAL;
1499 }
1500 } else if (has_newer_autopwm(data)) {
1501 for (i = 1; i < 3; i++) {
1502 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1503 err = -EINVAL;
1504 }
1505 }
1506
1507 if (err) {
1508 dev_err(dev,
1509 "Inconsistent trip points, not switching to automatic mode\n");
1510 dev_err(dev, "Adjust the trip points and try again\n");
1511 }
1512 return err;
1513 }
1514
1515 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1516 const char *buf, size_t count)
1517 {
1518 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1519 struct it87_data *data = dev_get_drvdata(dev);
1520 int nr = sensor_attr->index;
1521 long val;
1522 int err;
1523
1524 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1525 return -EINVAL;
1526
1527 /* Check trip points before switching to automatic mode */
1528 if (val == 2) {
1529 if (check_trip_points(dev, nr) < 0)
1530 return -EINVAL;
1531 }
1532
1533 err = it87_lock(data);
1534 if (err)
1535 return err;
1536
1537 if (val == 0) {
1538 if (nr < 3 && has_fanctl_onoff(data)) {
1539 int tmp;
1540 /* make sure the fan is on when in on/off mode */
1541 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1542 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1543 /* set on/off mode */
1544 data->fan_main_ctrl &= ~BIT(nr);
1545 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1546 data->fan_main_ctrl);
1547 } else {
1548 u8 ctrl;
1549
1550 /* No on/off mode, set maximum pwm value */
1551 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1552 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1553 data->pwm_duty[nr]);
1554 /* and set manual mode */
1555 if (has_newer_autopwm(data)) {
1556 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1557 data->pwm_temp_map[nr];
1558 } else {
1559 ctrl = data->pwm_duty[nr];
1560 }
1561 data->pwm_ctrl[nr] = ctrl;
1562 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1563 }
1564 } else {
1565 u8 ctrl;
1566
1567 if (has_newer_autopwm(data)) {
1568 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1569 data->pwm_temp_map[nr];
1570 if (val != 1)
1571 ctrl |= 0x80;
1572 } else {
1573 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1574 }
1575 data->pwm_ctrl[nr] = ctrl;
1576 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1577
1578 if (has_fanctl_onoff(data) && nr < 3) {
1579 /* set SmartGuardian mode */
1580 data->fan_main_ctrl |= BIT(nr);
1581 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1582 data->fan_main_ctrl);
1583 }
1584 }
1585
1586 it87_unlock(data);
1587 return count;
1588 }
1589
1590 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1591 const char *buf, size_t count)
1592 {
1593 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1594 struct it87_data *data = dev_get_drvdata(dev);
1595 int nr = sensor_attr->index;
1596 long val;
1597 int err;
1598
1599 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1600 return -EINVAL;
1601
1602 err = it87_lock(data);
1603 if (err)
1604 return err;
1605
1606 it87_update_pwm_ctrl(data, nr);
1607 if (has_newer_autopwm(data)) {
1608 /*
1609 * If we are in automatic mode, the PWM duty cycle register
1610 * is read-only so we can't write the value.
1611 */
1612 if (data->pwm_ctrl[nr] & 0x80) {
1613 count = -EBUSY;
1614 goto unlock;
1615 }
1616 data->pwm_duty[nr] = pwm_to_reg(data, val);
1617 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1618 data->pwm_duty[nr]);
1619 } else {
1620 data->pwm_duty[nr] = pwm_to_reg(data, val);
1621 /*
1622 * If we are in manual mode, write the duty cycle immediately;
1623 * otherwise, just store it for later use.
1624 */
1625 if (!(data->pwm_ctrl[nr] & 0x80)) {
1626 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1627 it87_write_value(data, IT87_REG_PWM[nr],
1628 data->pwm_ctrl[nr]);
1629 }
1630 }
1631 unlock:
1632 it87_unlock(data);
1633 return count;
1634 }
1635
1636 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1637 const char *buf, size_t count)
1638 {
1639 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1640 struct it87_data *data = dev_get_drvdata(dev);
1641 int nr = sensor_attr->index;
1642 unsigned long val;
1643 int err;
1644 int i;
1645
1646 if (kstrtoul(buf, 10, &val) < 0)
1647 return -EINVAL;
1648
1649 val = clamp_val(val, 0, 1000000);
1650 val *= has_newer_autopwm(data) ? 256 : 128;
1651
1652 /* Search for the nearest available frequency */
1653 for (i = 0; i < 7; i++) {
1654 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1655 break;
1656 }
1657
1658 err = it87_lock(data);
1659 if (err)
1660 return err;
1661
1662 if (nr == 0) {
1663 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1664 data->fan_ctl |= i << 4;
1665 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1666 } else {
1667 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1668 data->extra |= i << 4;
1669 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1670 }
1671 it87_unlock(data);
1672
1673 return count;
1674 }
1675
1676 static ssize_t show_pwm_temp_map(struct device *dev,
1677 struct device_attribute *attr, char *buf)
1678 {
1679 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1680 struct it87_data *data = it87_update_device(dev);
1681 int nr = sensor_attr->index;
1682 int map;
1683
1684 if (IS_ERR(data))
1685 return PTR_ERR(data);
1686
1687 map = data->pwm_temp_map[nr];
1688 if (map >= 3)
1689 map = 0; /* Should never happen */
1690 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
1691 map += 3;
1692
1693 return sprintf(buf, "%d\n", (int)BIT(map));
1694 }
1695
1696 static ssize_t set_pwm_temp_map(struct device *dev,
1697 struct device_attribute *attr, const char *buf,
1698 size_t count)
1699 {
1700 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1701 struct it87_data *data = dev_get_drvdata(dev);
1702 int nr = sensor_attr->index;
1703 long val;
1704 int err;
1705 u8 reg;
1706
1707 if (kstrtol(buf, 10, &val) < 0)
1708 return -EINVAL;
1709
1710 if (nr >= 3)
1711 val -= 3;
1712
1713 switch (val) {
1714 case BIT(0):
1715 reg = 0x00;
1716 break;
1717 case BIT(1):
1718 reg = 0x01;
1719 break;
1720 case BIT(2):
1721 reg = 0x02;
1722 break;
1723 default:
1724 return -EINVAL;
1725 }
1726
1727 err = it87_lock(data);
1728 if (err)
1729 return err;
1730
1731 it87_update_pwm_ctrl(data, nr);
1732 data->pwm_temp_map[nr] = reg;
1733 /*
1734 * If we are in automatic mode, write the temp mapping immediately;
1735 * otherwise, just store it for later use.
1736 */
1737 if (data->pwm_ctrl[nr] & 0x80) {
1738 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1739 data->pwm_temp_map[nr];
1740 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
1741 }
1742 it87_unlock(data);
1743 return count;
1744 }
1745
1746 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1747 char *buf)
1748 {
1749 struct it87_data *data = it87_update_device(dev);
1750 struct sensor_device_attribute_2 *sensor_attr =
1751 to_sensor_dev_attr_2(attr);
1752 int nr = sensor_attr->nr;
1753 int point = sensor_attr->index;
1754
1755 if (IS_ERR(data))
1756 return PTR_ERR(data);
1757
1758 return sprintf(buf, "%d\n",
1759 pwm_from_reg(data, data->auto_pwm[nr][point]));
1760 }
1761
1762 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t count)
1764 {
1765 struct it87_data *data = dev_get_drvdata(dev);
1766 struct sensor_device_attribute_2 *sensor_attr =
1767 to_sensor_dev_attr_2(attr);
1768 int nr = sensor_attr->nr;
1769 int point = sensor_attr->index;
1770 int regaddr;
1771 long val;
1772 int err;
1773
1774 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1775 return -EINVAL;
1776
1777 err = it87_lock(data);
1778 if (err)
1779 return err;
1780
1781 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1782 if (has_newer_autopwm(data))
1783 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1784 else
1785 regaddr = IT87_REG_AUTO_PWM(nr, point);
1786 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1787 it87_unlock(data);
1788 return count;
1789 }
1790
1791 static ssize_t show_auto_pwm_slope(struct device *dev,
1792 struct device_attribute *attr, char *buf)
1793 {
1794 struct it87_data *data = it87_update_device(dev);
1795 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1796 int nr = sensor_attr->index;
1797
1798 if (IS_ERR(data))
1799 return PTR_ERR(data);
1800
1801 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1802 }
1803
1804 static ssize_t set_auto_pwm_slope(struct device *dev,
1805 struct device_attribute *attr,
1806 const char *buf, size_t count)
1807 {
1808 struct it87_data *data = dev_get_drvdata(dev);
1809 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1810 int nr = sensor_attr->index;
1811 unsigned long val;
1812 int err;
1813
1814 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1815 return -EINVAL;
1816
1817 err = it87_lock(data);
1818 if (err)
1819 return err;
1820
1821 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1822 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1823 data->auto_pwm[nr][1]);
1824 it87_unlock(data);
1825 return count;
1826 }
1827
1828 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1829 char *buf)
1830 {
1831 struct it87_data *data = it87_update_device(dev);
1832 struct sensor_device_attribute_2 *sensor_attr =
1833 to_sensor_dev_attr_2(attr);
1834 int nr = sensor_attr->nr;
1835 int point = sensor_attr->index;
1836 int reg;
1837
1838 if (IS_ERR(data))
1839 return PTR_ERR(data);
1840
1841 if (has_old_autopwm(data) || point)
1842 reg = data->auto_temp[nr][point];
1843 else
1844 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1845
1846 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1847 }
1848
1849 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1850 const char *buf, size_t count)
1851 {
1852 struct it87_data *data = dev_get_drvdata(dev);
1853 struct sensor_device_attribute_2 *sensor_attr =
1854 to_sensor_dev_attr_2(attr);
1855 int nr = sensor_attr->nr;
1856 int point = sensor_attr->index;
1857 long val;
1858 int reg;
1859 int err;
1860
1861 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1862 return -EINVAL;
1863
1864 err = it87_lock(data);
1865 if (err)
1866 return err;
1867
1868 if (has_newer_autopwm(data) && !point) {
1869 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1870 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1871 data->auto_temp[nr][0] = reg;
1872 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1873 } else {
1874 reg = TEMP_TO_REG(val);
1875 data->auto_temp[nr][point] = reg;
1876 if (has_newer_autopwm(data))
1877 point--;
1878 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1879 }
1880 it87_unlock(data);
1881 return count;
1882 }
1883
1884 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1885 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1886 0, 1);
1887 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1888 set_fan_div, 0);
1889
1890 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1891 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1892 1, 1);
1893 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1894 set_fan_div, 1);
1895
1896 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1897 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1898 2, 1);
1899 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1900 set_fan_div, 2);
1901
1902 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1903 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1904 3, 1);
1905
1906 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1907 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1908 4, 1);
1909
1910 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1911 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1912 5, 1);
1913
1914 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1915 show_pwm_enable, set_pwm_enable, 0);
1916 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1917 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1918 set_pwm_freq, 0);
1919 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1920 show_pwm_temp_map, set_pwm_temp_map, 0);
1921 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1922 show_auto_pwm, set_auto_pwm, 0, 0);
1923 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1924 show_auto_pwm, set_auto_pwm, 0, 1);
1925 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1926 show_auto_pwm, set_auto_pwm, 0, 2);
1927 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1928 show_auto_pwm, NULL, 0, 3);
1929 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1930 show_auto_temp, set_auto_temp, 0, 1);
1931 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1932 show_auto_temp, set_auto_temp, 0, 0);
1933 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1934 show_auto_temp, set_auto_temp, 0, 2);
1935 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1936 show_auto_temp, set_auto_temp, 0, 3);
1937 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1938 show_auto_temp, set_auto_temp, 0, 4);
1939 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1940 show_auto_pwm, set_auto_pwm, 0, 0);
1941 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1942 show_auto_pwm_slope, set_auto_pwm_slope, 0);
1943
1944 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1945 show_pwm_enable, set_pwm_enable, 1);
1946 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1947 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1948 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1949 show_pwm_temp_map, set_pwm_temp_map, 1);
1950 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1951 show_auto_pwm, set_auto_pwm, 1, 0);
1952 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1953 show_auto_pwm, set_auto_pwm, 1, 1);
1954 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1955 show_auto_pwm, set_auto_pwm, 1, 2);
1956 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1957 show_auto_pwm, NULL, 1, 3);
1958 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1959 show_auto_temp, set_auto_temp, 1, 1);
1960 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1961 show_auto_temp, set_auto_temp, 1, 0);
1962 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1963 show_auto_temp, set_auto_temp, 1, 2);
1964 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1965 show_auto_temp, set_auto_temp, 1, 3);
1966 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1967 show_auto_temp, set_auto_temp, 1, 4);
1968 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1969 show_auto_pwm, set_auto_pwm, 1, 0);
1970 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1971 show_auto_pwm_slope, set_auto_pwm_slope, 1);
1972
1973 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1974 show_pwm_enable, set_pwm_enable, 2);
1975 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1976 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
1977 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
1978 show_pwm_temp_map, set_pwm_temp_map, 2);
1979 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1980 show_auto_pwm, set_auto_pwm, 2, 0);
1981 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1982 show_auto_pwm, set_auto_pwm, 2, 1);
1983 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1984 show_auto_pwm, set_auto_pwm, 2, 2);
1985 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1986 show_auto_pwm, NULL, 2, 3);
1987 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1988 show_auto_temp, set_auto_temp, 2, 1);
1989 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1990 show_auto_temp, set_auto_temp, 2, 0);
1991 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1992 show_auto_temp, set_auto_temp, 2, 2);
1993 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1994 show_auto_temp, set_auto_temp, 2, 3);
1995 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1996 show_auto_temp, set_auto_temp, 2, 4);
1997 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
1998 show_auto_pwm, set_auto_pwm, 2, 0);
1999 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2000 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2001
2002 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2003 show_pwm_enable, set_pwm_enable, 3);
2004 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2005 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2006 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2007 show_pwm_temp_map, set_pwm_temp_map, 3);
2008 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2009 show_auto_temp, set_auto_temp, 2, 1);
2010 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2011 show_auto_temp, set_auto_temp, 2, 0);
2012 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2013 show_auto_temp, set_auto_temp, 2, 2);
2014 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2015 show_auto_temp, set_auto_temp, 2, 3);
2016 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2017 show_auto_pwm, set_auto_pwm, 3, 0);
2018 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2019 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2020
2021 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2022 show_pwm_enable, set_pwm_enable, 4);
2023 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2024 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2025 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2026 show_pwm_temp_map, set_pwm_temp_map, 4);
2027 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2028 show_auto_temp, set_auto_temp, 2, 1);
2029 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2030 show_auto_temp, set_auto_temp, 2, 0);
2031 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2032 show_auto_temp, set_auto_temp, 2, 2);
2033 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2034 show_auto_temp, set_auto_temp, 2, 3);
2035 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2036 show_auto_pwm, set_auto_pwm, 4, 0);
2037 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2038 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2039
2040 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2041 show_pwm_enable, set_pwm_enable, 5);
2042 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2043 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2044 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2045 show_pwm_temp_map, set_pwm_temp_map, 5);
2046 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2047 show_auto_temp, set_auto_temp, 2, 1);
2048 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2049 show_auto_temp, set_auto_temp, 2, 0);
2050 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2051 show_auto_temp, set_auto_temp, 2, 2);
2052 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2053 show_auto_temp, set_auto_temp, 2, 3);
2054 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2055 show_auto_pwm, set_auto_pwm, 5, 0);
2056 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2057 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2058
2059 /* Alarms */
2060 static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
2061 char *buf)
2062 {
2063 struct it87_data *data = it87_update_device(dev);
2064
2065 if (IS_ERR(data))
2066 return PTR_ERR(data);
2067
2068 return sprintf(buf, "%u\n", data->alarms);
2069 }
2070 static DEVICE_ATTR_RO(alarms);
2071
2072 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2073 char *buf)
2074 {
2075 struct it87_data *data = it87_update_device(dev);
2076 int bitnr = to_sensor_dev_attr(attr)->index;
2077
2078 if (IS_ERR(data))
2079 return PTR_ERR(data);
2080
2081 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2082 }
2083
2084 static ssize_t clear_intrusion(struct device *dev,
2085 struct device_attribute *attr, const char *buf,
2086 size_t count)
2087 {
2088 struct it87_data *data = dev_get_drvdata(dev);
2089 int err, config;
2090 long val;
2091
2092 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2093 return -EINVAL;
2094
2095 err = it87_lock(data);
2096 if (err)
2097 return err;
2098
2099 config = it87_read_value(data, IT87_REG_CONFIG);
2100 if (config < 0) {
2101 count = config;
2102 } else {
2103 config |= BIT(5);
2104 it87_write_value(data, IT87_REG_CONFIG, config);
2105 /* Invalidate cache to force re-read */
2106 data->valid = false;
2107 }
2108 it87_unlock(data);
2109 return count;
2110 }
2111
2112 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2113 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2114 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2115 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2116 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2117 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2118 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2119 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2120 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2121 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2122 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2123 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2124 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2125 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2126 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2127 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2128 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2129 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2130 show_alarm, clear_intrusion, 4);
2131
2132 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2133 char *buf)
2134 {
2135 struct it87_data *data = it87_update_device(dev);
2136 int bitnr = to_sensor_dev_attr(attr)->index;
2137
2138 if (IS_ERR(data))
2139 return PTR_ERR(data);
2140
2141 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2142 }
2143
2144 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2145 const char *buf, size_t count)
2146 {
2147 int bitnr = to_sensor_dev_attr(attr)->index;
2148 struct it87_data *data = dev_get_drvdata(dev);
2149 long val;
2150 int err;
2151
2152 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2153 return -EINVAL;
2154
2155 err = it87_lock(data);
2156 if (err)
2157 return err;
2158
2159 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2160 if (val)
2161 data->beeps |= BIT(bitnr);
2162 else
2163 data->beeps &= ~BIT(bitnr);
2164 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2165 it87_unlock(data);
2166 return count;
2167 }
2168
2169 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2170 show_beep, set_beep, 1);
2171 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2172 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2173 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2174 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2175 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2176 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2177 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2178 /* fanX_beep writability is set later */
2179 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2180 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2181 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2182 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2183 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2184 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2185 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2186 show_beep, set_beep, 2);
2187 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2188 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2189
2190 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
2191 char *buf)
2192 {
2193 struct it87_data *data = dev_get_drvdata(dev);
2194
2195 return sprintf(buf, "%u\n", data->vrm);
2196 }
2197
2198 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
2199 const char *buf, size_t count)
2200 {
2201 struct it87_data *data = dev_get_drvdata(dev);
2202 unsigned long val;
2203
2204 if (kstrtoul(buf, 10, &val) < 0)
2205 return -EINVAL;
2206
2207 data->vrm = val;
2208
2209 return count;
2210 }
2211 static DEVICE_ATTR_RW(vrm);
2212
2213 static ssize_t cpu0_vid_show(struct device *dev,
2214 struct device_attribute *attr, char *buf)
2215 {
2216 struct it87_data *data = it87_update_device(dev);
2217
2218 if (IS_ERR(data))
2219 return PTR_ERR(data);
2220
2221 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2222 }
2223 static DEVICE_ATTR_RO(cpu0_vid);
2224
2225 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2226 char *buf)
2227 {
2228 static const char * const labels[] = {
2229 "+5V",
2230 "5VSB",
2231 "Vbat",
2232 "AVCC",
2233 };
2234 static const char * const labels_it8721[] = {
2235 "+3.3V",
2236 "3VSB",
2237 "Vbat",
2238 "+3.3V",
2239 };
2240 struct it87_data *data = dev_get_drvdata(dev);
2241 int nr = to_sensor_dev_attr(attr)->index;
2242 const char *label;
2243
2244 if (has_vin3_5v(data) && nr == 0)
2245 label = labels[0];
2246 else if (has_scaling(data))
2247 label = labels_it8721[nr];
2248 else
2249 label = labels[nr];
2250
2251 return sprintf(buf, "%s\n", label);
2252 }
2253 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2254 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2255 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2256 /* AVCC3 */
2257 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2258
2259 static umode_t it87_in_is_visible(struct kobject *kobj,
2260 struct attribute *attr, int index)
2261 {
2262 struct device *dev = kobj_to_dev(kobj);
2263 struct it87_data *data = dev_get_drvdata(dev);
2264 int i = index / 5; /* voltage index */
2265 int a = index % 5; /* attribute index */
2266
2267 if (index >= 40) { /* in8 and higher only have input attributes */
2268 i = index - 40 + 8;
2269 a = 0;
2270 }
2271
2272 if (!(data->has_in & BIT(i)))
2273 return 0;
2274
2275 if (a == 4 && !data->has_beep)
2276 return 0;
2277
2278 return attr->mode;
2279 }
2280
2281 static struct attribute *it87_attributes_in[] = {
2282 &sensor_dev_attr_in0_input.dev_attr.attr,
2283 &sensor_dev_attr_in0_min.dev_attr.attr,
2284 &sensor_dev_attr_in0_max.dev_attr.attr,
2285 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2286 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2287
2288 &sensor_dev_attr_in1_input.dev_attr.attr,
2289 &sensor_dev_attr_in1_min.dev_attr.attr,
2290 &sensor_dev_attr_in1_max.dev_attr.attr,
2291 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2292 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2293
2294 &sensor_dev_attr_in2_input.dev_attr.attr,
2295 &sensor_dev_attr_in2_min.dev_attr.attr,
2296 &sensor_dev_attr_in2_max.dev_attr.attr,
2297 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2298 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2299
2300 &sensor_dev_attr_in3_input.dev_attr.attr,
2301 &sensor_dev_attr_in3_min.dev_attr.attr,
2302 &sensor_dev_attr_in3_max.dev_attr.attr,
2303 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2304 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2305
2306 &sensor_dev_attr_in4_input.dev_attr.attr,
2307 &sensor_dev_attr_in4_min.dev_attr.attr,
2308 &sensor_dev_attr_in4_max.dev_attr.attr,
2309 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2310 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2311
2312 &sensor_dev_attr_in5_input.dev_attr.attr,
2313 &sensor_dev_attr_in5_min.dev_attr.attr,
2314 &sensor_dev_attr_in5_max.dev_attr.attr,
2315 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2316 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2317
2318 &sensor_dev_attr_in6_input.dev_attr.attr,
2319 &sensor_dev_attr_in6_min.dev_attr.attr,
2320 &sensor_dev_attr_in6_max.dev_attr.attr,
2321 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2322 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2323
2324 &sensor_dev_attr_in7_input.dev_attr.attr,
2325 &sensor_dev_attr_in7_min.dev_attr.attr,
2326 &sensor_dev_attr_in7_max.dev_attr.attr,
2327 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2328 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2329
2330 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2331 &sensor_dev_attr_in9_input.dev_attr.attr,
2332 &sensor_dev_attr_in10_input.dev_attr.attr,
2333 &sensor_dev_attr_in11_input.dev_attr.attr,
2334 &sensor_dev_attr_in12_input.dev_attr.attr,
2335 NULL
2336 };
2337
2338 static const struct attribute_group it87_group_in = {
2339 .attrs = it87_attributes_in,
2340 .is_visible = it87_in_is_visible,
2341 };
2342
2343 static umode_t it87_temp_is_visible(struct kobject *kobj,
2344 struct attribute *attr, int index)
2345 {
2346 struct device *dev = kobj_to_dev(kobj);
2347 struct it87_data *data = dev_get_drvdata(dev);
2348 int i = index / 7; /* temperature index */
2349 int a = index % 7; /* attribute index */
2350
2351 if (index >= 21) {
2352 i = index - 21 + 3;
2353 a = 0;
2354 }
2355
2356 if (!(data->has_temp & BIT(i)))
2357 return 0;
2358
2359 if (a == 3) {
2360 if (get_temp_type(data, i) == 0)
2361 return 0;
2362 return attr->mode;
2363 }
2364
2365 if (a == 5 && !has_temp_offset(data))
2366 return 0;
2367
2368 if (a == 6 && !data->has_beep)
2369 return 0;
2370
2371 return attr->mode;
2372 }
2373
2374 static struct attribute *it87_attributes_temp[] = {
2375 &sensor_dev_attr_temp1_input.dev_attr.attr,
2376 &sensor_dev_attr_temp1_max.dev_attr.attr,
2377 &sensor_dev_attr_temp1_min.dev_attr.attr,
2378 &sensor_dev_attr_temp1_type.dev_attr.attr,
2379 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2380 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2381 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2382
2383 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2384 &sensor_dev_attr_temp2_max.dev_attr.attr,
2385 &sensor_dev_attr_temp2_min.dev_attr.attr,
2386 &sensor_dev_attr_temp2_type.dev_attr.attr,
2387 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2388 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2389 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2390
2391 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2392 &sensor_dev_attr_temp3_max.dev_attr.attr,
2393 &sensor_dev_attr_temp3_min.dev_attr.attr,
2394 &sensor_dev_attr_temp3_type.dev_attr.attr,
2395 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2396 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2397 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2398
2399 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2400 &sensor_dev_attr_temp5_input.dev_attr.attr,
2401 &sensor_dev_attr_temp6_input.dev_attr.attr,
2402 NULL
2403 };
2404
2405 static const struct attribute_group it87_group_temp = {
2406 .attrs = it87_attributes_temp,
2407 .is_visible = it87_temp_is_visible,
2408 };
2409
2410 static umode_t it87_is_visible(struct kobject *kobj,
2411 struct attribute *attr, int index)
2412 {
2413 struct device *dev = kobj_to_dev(kobj);
2414 struct it87_data *data = dev_get_drvdata(dev);
2415
2416 if ((index == 2 || index == 3) && !data->has_vid)
2417 return 0;
2418
2419 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2420 return 0;
2421
2422 return attr->mode;
2423 }
2424
2425 static struct attribute *it87_attributes[] = {
2426 &dev_attr_alarms.attr,
2427 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2428 &dev_attr_vrm.attr, /* 2 */
2429 &dev_attr_cpu0_vid.attr, /* 3 */
2430 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2431 &sensor_dev_attr_in7_label.dev_attr.attr,
2432 &sensor_dev_attr_in8_label.dev_attr.attr,
2433 &sensor_dev_attr_in9_label.dev_attr.attr,
2434 NULL
2435 };
2436
2437 static const struct attribute_group it87_group = {
2438 .attrs = it87_attributes,
2439 .is_visible = it87_is_visible,
2440 };
2441
2442 static umode_t it87_fan_is_visible(struct kobject *kobj,
2443 struct attribute *attr, int index)
2444 {
2445 struct device *dev = kobj_to_dev(kobj);
2446 struct it87_data *data = dev_get_drvdata(dev);
2447 int i = index / 5; /* fan index */
2448 int a = index % 5; /* attribute index */
2449
2450 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2451 i = (index - 15) / 4 + 3;
2452 a = (index - 15) % 4;
2453 }
2454
2455 if (!(data->has_fan & BIT(i)))
2456 return 0;
2457
2458 if (a == 3) { /* beep */
2459 if (!data->has_beep)
2460 return 0;
2461 /* first fan beep attribute is writable */
2462 if (i == __ffs(data->has_fan))
2463 return attr->mode | S_IWUSR;
2464 }
2465
2466 if (a == 4 && has_16bit_fans(data)) /* divisor */
2467 return 0;
2468
2469 return attr->mode;
2470 }
2471
2472 static struct attribute *it87_attributes_fan[] = {
2473 &sensor_dev_attr_fan1_input.dev_attr.attr,
2474 &sensor_dev_attr_fan1_min.dev_attr.attr,
2475 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2476 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2477 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2478
2479 &sensor_dev_attr_fan2_input.dev_attr.attr,
2480 &sensor_dev_attr_fan2_min.dev_attr.attr,
2481 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2482 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2483 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2484
2485 &sensor_dev_attr_fan3_input.dev_attr.attr,
2486 &sensor_dev_attr_fan3_min.dev_attr.attr,
2487 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2488 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2489 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2490
2491 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2492 &sensor_dev_attr_fan4_min.dev_attr.attr,
2493 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2494 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2495
2496 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2497 &sensor_dev_attr_fan5_min.dev_attr.attr,
2498 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2499 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2500
2501 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2502 &sensor_dev_attr_fan6_min.dev_attr.attr,
2503 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2504 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2505 NULL
2506 };
2507
2508 static const struct attribute_group it87_group_fan = {
2509 .attrs = it87_attributes_fan,
2510 .is_visible = it87_fan_is_visible,
2511 };
2512
2513 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2514 struct attribute *attr, int index)
2515 {
2516 struct device *dev = kobj_to_dev(kobj);
2517 struct it87_data *data = dev_get_drvdata(dev);
2518 int i = index / 4; /* pwm index */
2519 int a = index % 4; /* attribute index */
2520
2521 if (!(data->has_pwm & BIT(i)))
2522 return 0;
2523
2524 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2525 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2526 return attr->mode | S_IWUSR;
2527
2528 /* pwm2_freq is writable if there are two pwm frequency selects */
2529 if (has_pwm_freq2(data) && i == 1 && a == 2)
2530 return attr->mode | S_IWUSR;
2531
2532 return attr->mode;
2533 }
2534
2535 static struct attribute *it87_attributes_pwm[] = {
2536 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2537 &sensor_dev_attr_pwm1.dev_attr.attr,
2538 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2539 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2540
2541 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2542 &sensor_dev_attr_pwm2.dev_attr.attr,
2543 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2544 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2545
2546 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2547 &sensor_dev_attr_pwm3.dev_attr.attr,
2548 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2549 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2550
2551 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2552 &sensor_dev_attr_pwm4.dev_attr.attr,
2553 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2554 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2555
2556 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2557 &sensor_dev_attr_pwm5.dev_attr.attr,
2558 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2559 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2560
2561 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2562 &sensor_dev_attr_pwm6.dev_attr.attr,
2563 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2564 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2565
2566 NULL
2567 };
2568
2569 static const struct attribute_group it87_group_pwm = {
2570 .attrs = it87_attributes_pwm,
2571 .is_visible = it87_pwm_is_visible,
2572 };
2573
2574 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2575 struct attribute *attr, int index)
2576 {
2577 struct device *dev = kobj_to_dev(kobj);
2578 struct it87_data *data = dev_get_drvdata(dev);
2579 int i = index / 11; /* pwm index */
2580 int a = index % 11; /* attribute index */
2581
2582 if (index >= 33) { /* pwm 4..6 */
2583 i = (index - 33) / 6 + 3;
2584 a = (index - 33) % 6 + 4;
2585 }
2586
2587 if (!(data->has_pwm & BIT(i)))
2588 return 0;
2589
2590 if (has_newer_autopwm(data)) {
2591 if (a < 4) /* no auto point pwm */
2592 return 0;
2593 if (a == 8) /* no auto_point4 */
2594 return 0;
2595 }
2596 if (has_old_autopwm(data)) {
2597 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2598 return 0;
2599 }
2600
2601 return attr->mode;
2602 }
2603
2604 static struct attribute *it87_attributes_auto_pwm[] = {
2605 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2606 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2607 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2608 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2609 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2610 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2611 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2612 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2613 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2614 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2615 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2616
2617 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2618 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2619 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2620 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2621 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2622 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2623 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2624 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2625 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2626 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2627 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2628
2629 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2630 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2631 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2632 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2633 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2634 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2635 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2636 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2637 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2638 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2639 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2640
2641 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2642 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2643 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2644 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2645 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2646 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2647
2648 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2649 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2650 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2651 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2652 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2653 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2654
2655 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2656 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2657 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2658 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2659 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2660 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2661
2662 NULL,
2663 };
2664
2665 static const struct attribute_group it87_group_auto_pwm = {
2666 .attrs = it87_attributes_auto_pwm,
2667 .is_visible = it87_auto_pwm_is_visible,
2668 };
2669
2670 /*
2671 * Original explanation:
2672 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
2673 * (IT8792E) needs to be in configuration mode before accessing the first
2674 * due to a bug in IT8792E which otherwise results in LPC bus access errors.
2675 * This needs to be done before accessing the first Super-IO chip since
2676 * the second chip may have been accessed prior to loading this driver.
2677 *
2678 * The problem is also reported to affect IT8795E, which is used on X299 boards
2679 * and has the same chip ID as IT8792E (0x8733). It also appears to affect
2680 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
2681 * Z87X-OC.
2682 *
2683 * From other information supplied:
2684 * ChipIDs 0x8733, 0x8695 (early ID for IT87952E) and 0x8790 are initialized
2685 * and left in configuration mode, and entering and/or exiting configuration
2686 * mode is what causes the crash.
2687 *
2688 * The recommendation is to look up the chipID before doing any mode swap
2689 * and then act accordingly.
2690 */
2691 /* SuperIO detection - will change isa_address if a chip is found */
2692 static int __init it87_find(int sioaddr, unsigned short *address,
2693 struct it87_sio_data *sio_data, int chip_cnt)
2694 {
2695 int err;
2696 u16 chip_type;
2697 const struct it87_devices *config = NULL;
2698 bool enabled = false;
2699
2700 /* First step, lock memory but don't enter configuration mode */
2701 err = superio_enter(sioaddr, true);
2702 if (err)
2703 return err;
2704
2705 err = -ENODEV;
2706 chip_type = superio_inw(sioaddr, DEVID);
2707 /* Check for a valid chip before forcing chip id */
2708 if (chip_type == 0xffff) {
2709 /* Enter configuration mode */
2710 __superio_enter(sioaddr);
2711 enabled = true;
2712 /* and then try again */
2713 chip_type = superio_inw(sioaddr, DEVID);
2714 if (chip_type == 0xffff)
2715 goto exit;
2716 }
2717
2718 if (force_id_cnt == 1) {
2719 /* If only one value given use for all chips */
2720 if (force_id[0])
2721 chip_type = force_id[0];
2722 } else if (force_id[chip_cnt])
2723 chip_type = force_id[chip_cnt];
2724
2725 switch (chip_type) {
2726 case IT8705F_DEVID:
2727 sio_data->type = it87;
2728 break;
2729 case IT8712F_DEVID:
2730 sio_data->type = it8712;
2731 break;
2732 case IT8716F_DEVID:
2733 case IT8726F_DEVID:
2734 sio_data->type = it8716;
2735 break;
2736 case IT8718F_DEVID:
2737 sio_data->type = it8718;
2738 break;
2739 case IT8720F_DEVID:
2740 sio_data->type = it8720;
2741 break;
2742 case IT8721F_DEVID:
2743 sio_data->type = it8721;
2744 break;
2745 case IT8728F_DEVID:
2746 sio_data->type = it8728;
2747 break;
2748 case IT8732F_DEVID:
2749 sio_data->type = it8732;
2750 break;
2751 case IT8792E_DEVID:
2752 sio_data->type = it8792;
2753 break;
2754 case IT8771E_DEVID:
2755 sio_data->type = it8771;
2756 break;
2757 case IT8772E_DEVID:
2758 sio_data->type = it8772;
2759 break;
2760 case IT8781F_DEVID:
2761 sio_data->type = it8781;
2762 break;
2763 case IT8782F_DEVID:
2764 sio_data->type = it8782;
2765 break;
2766 case IT8783E_DEVID:
2767 sio_data->type = it8783;
2768 break;
2769 case IT8786E_DEVID:
2770 sio_data->type = it8786;
2771 break;
2772 case IT8790E_DEVID:
2773 sio_data->type = it8790;
2774 break;
2775 case IT8603E_DEVID:
2776 case IT8623E_DEVID:
2777 sio_data->type = it8603;
2778 break;
2779 case IT8620E_DEVID:
2780 sio_data->type = it8620;
2781 break;
2782 case IT8622E_DEVID:
2783 sio_data->type = it8622;
2784 break;
2785 case IT8628E_DEVID:
2786 sio_data->type = it8628;
2787 break;
2788 case IT87952E_DEVID:
2789 sio_data->type = it87952;
2790 break;
2791 case 0xffff: /* No device at all */
2792 goto exit;
2793 default:
2794 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2795 goto exit;
2796 }
2797
2798 config = &it87_devices[sio_data->type];
2799
2800 /*
2801 * If previously we didn't enter configuration mode and it isn't a
2802 * chip we know is initialised in configuration mode, then enter
2803 * configuration mode.
2804 *
2805 * I don't know if any such chips can exist but be defensive.
2806 */
2807 if (!enabled && !has_noconf(config)) {
2808 __superio_enter(sioaddr);
2809 enabled = true;
2810 }
2811
2812 superio_select(sioaddr, PME);
2813 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2814 pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n",
2815 config->model, sioaddr);
2816 goto exit;
2817 }
2818
2819 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2820 if (*address == 0) {
2821 pr_info("Base address not set (chip %s ioreg 0x%x), skipping\n",
2822 config->model, sioaddr);
2823 goto exit;
2824 }
2825
2826 err = 0;
2827 sio_data->sioaddr = sioaddr;
2828 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2829 pr_info("Found %s chip at 0x%x, revision %d\n",
2830 it87_devices[sio_data->type].model,
2831 *address, sio_data->revision);
2832
2833 /* in7 (VSB or VCCH5V) is always internal on some chips */
2834 if (has_in7_internal(config))
2835 sio_data->internal |= BIT(1);
2836
2837 /* in8 (Vbat) is always internal */
2838 sio_data->internal |= BIT(2);
2839
2840 /* in9 (AVCC3), always internal if supported */
2841 if (has_avcc3(config))
2842 sio_data->internal |= BIT(3); /* in9 is AVCC */
2843 else
2844 sio_data->skip_in |= BIT(9);
2845
2846 if (!has_four_pwm(config))
2847 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2848 else if (!has_five_pwm(config))
2849 sio_data->skip_pwm |= BIT(4) | BIT(5);
2850 else if (!has_six_pwm(config))
2851 sio_data->skip_pwm |= BIT(5);
2852
2853 if (!has_vid(config))
2854 sio_data->skip_vid = 1;
2855
2856 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2857 if (sio_data->type == it87) {
2858 /* The IT8705F has a different LD number for GPIO */
2859 superio_select(sioaddr, 5);
2860 sio_data->beep_pin = superio_inb(sioaddr,
2861 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2862 } else if (sio_data->type == it8783) {
2863 int reg25, reg27, reg2a, reg2c, regef;
2864
2865 superio_select(sioaddr, GPIO);
2866
2867 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2868 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2869 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2870 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2871 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2872
2873 /* Check if fan3 is there or not */
2874 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2875 sio_data->skip_fan |= BIT(2);
2876 if ((reg25 & BIT(4)) ||
2877 (!(reg2a & BIT(1)) && (regef & BIT(0))))
2878 sio_data->skip_pwm |= BIT(2);
2879
2880 /* Check if fan2 is there or not */
2881 if (reg27 & BIT(7))
2882 sio_data->skip_fan |= BIT(1);
2883 if (reg27 & BIT(3))
2884 sio_data->skip_pwm |= BIT(1);
2885
2886 /* VIN5 */
2887 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2888 sio_data->skip_in |= BIT(5); /* No VIN5 */
2889
2890 /* VIN6 */
2891 if (reg27 & BIT(1))
2892 sio_data->skip_in |= BIT(6); /* No VIN6 */
2893
2894 /*
2895 * VIN7
2896 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2897 */
2898 if (reg27 & BIT(2)) {
2899 /*
2900 * The data sheet is a bit unclear regarding the
2901 * internal voltage divider for VCCH5V. It says
2902 * "This bit enables and switches VIN7 (pin 91) to the
2903 * internal voltage divider for VCCH5V".
2904 * This is different to other chips, where the internal
2905 * voltage divider would connect VIN7 to an internal
2906 * voltage source. Maybe that is the case here as well.
2907 *
2908 * Since we don't know for sure, re-route it if that is
2909 * not the case, and ask the user to report if the
2910 * resulting voltage is sane.
2911 */
2912 if (!(reg2c & BIT(1))) {
2913 reg2c |= BIT(1);
2914 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2915 reg2c);
2916 sio_data->need_in7_reroute = true;
2917 pr_notice("Routing internal VCCH5V to in7.\n");
2918 }
2919 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2920 pr_notice("Please report if it displays a reasonable voltage.\n");
2921 }
2922
2923 if (reg2c & BIT(0))
2924 sio_data->internal |= BIT(0);
2925 if (reg2c & BIT(1))
2926 sio_data->internal |= BIT(1);
2927
2928 sio_data->beep_pin = superio_inb(sioaddr,
2929 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2930 } else if (sio_data->type == it8603) {
2931 int reg27, reg29;
2932
2933 superio_select(sioaddr, GPIO);
2934
2935 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2936
2937 /* Check if fan3 is there or not */
2938 if (reg27 & BIT(6))
2939 sio_data->skip_pwm |= BIT(2);
2940 if (reg27 & BIT(7))
2941 sio_data->skip_fan |= BIT(2);
2942
2943 /* Check if fan2 is there or not */
2944 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2945 if (reg29 & BIT(1))
2946 sio_data->skip_pwm |= BIT(1);
2947 if (reg29 & BIT(2))
2948 sio_data->skip_fan |= BIT(1);
2949
2950 sio_data->skip_in |= BIT(5); /* No VIN5 */
2951 sio_data->skip_in |= BIT(6); /* No VIN6 */
2952
2953 sio_data->beep_pin = superio_inb(sioaddr,
2954 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2955 } else if (sio_data->type == it8620 || sio_data->type == it8628) {
2956 int reg;
2957
2958 superio_select(sioaddr, GPIO);
2959
2960 /* Check for pwm5 */
2961 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2962 if (reg & BIT(6))
2963 sio_data->skip_pwm |= BIT(4);
2964
2965 /* Check for fan4, fan5 */
2966 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2967 if (!(reg & BIT(5)))
2968 sio_data->skip_fan |= BIT(3);
2969 if (!(reg & BIT(4)))
2970 sio_data->skip_fan |= BIT(4);
2971
2972 /* Check for pwm3, fan3 */
2973 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2974 if (reg & BIT(6))
2975 sio_data->skip_pwm |= BIT(2);
2976 if (reg & BIT(7))
2977 sio_data->skip_fan |= BIT(2);
2978
2979 /* Check for pwm4 */
2980 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2981 if (reg & BIT(2))
2982 sio_data->skip_pwm |= BIT(3);
2983
2984 /* Check for pwm2, fan2 */
2985 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2986 if (reg & BIT(1))
2987 sio_data->skip_pwm |= BIT(1);
2988 if (reg & BIT(2))
2989 sio_data->skip_fan |= BIT(1);
2990 /* Check for pwm6, fan6 */
2991 if (!(reg & BIT(7))) {
2992 sio_data->skip_pwm |= BIT(5);
2993 sio_data->skip_fan |= BIT(5);
2994 }
2995
2996 /* Check if AVCC is on VIN3 */
2997 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2998 if (reg & BIT(0))
2999 sio_data->internal |= BIT(0);
3000 else
3001 sio_data->skip_in |= BIT(9);
3002
3003 sio_data->beep_pin = superio_inb(sioaddr,
3004 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3005 } else if (sio_data->type == it8622) {
3006 int reg;
3007
3008 superio_select(sioaddr, GPIO);
3009
3010 /* Check for pwm4, fan4 */
3011 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3012 if (reg & BIT(6))
3013 sio_data->skip_fan |= BIT(3);
3014 if (reg & BIT(5))
3015 sio_data->skip_pwm |= BIT(3);
3016
3017 /* Check for pwm3, fan3, pwm5, fan5 */
3018 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3019 if (reg & BIT(6))
3020 sio_data->skip_pwm |= BIT(2);
3021 if (reg & BIT(7))
3022 sio_data->skip_fan |= BIT(2);
3023 if (reg & BIT(3))
3024 sio_data->skip_pwm |= BIT(4);
3025 if (reg & BIT(1))
3026 sio_data->skip_fan |= BIT(4);
3027
3028 /* Check for pwm2, fan2 */
3029 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3030 if (reg & BIT(1))
3031 sio_data->skip_pwm |= BIT(1);
3032 if (reg & BIT(2))
3033 sio_data->skip_fan |= BIT(1);
3034
3035 /* Check for AVCC */
3036 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3037 if (!(reg & BIT(0)))
3038 sio_data->skip_in |= BIT(9);
3039
3040 sio_data->beep_pin = superio_inb(sioaddr,
3041 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3042 } else if (sio_data->type == it8732) {
3043 int reg;
3044
3045 superio_select(sioaddr, GPIO);
3046
3047 /* Check for pwm2, fan2 */
3048 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3049 if (reg & BIT(1))
3050 sio_data->skip_pwm |= BIT(1);
3051 if (reg & BIT(2))
3052 sio_data->skip_fan |= BIT(1);
3053
3054 /* Check for pwm3, fan3, fan4 */
3055 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3056 if (reg & BIT(6))
3057 sio_data->skip_pwm |= BIT(2);
3058 if (reg & BIT(7))
3059 sio_data->skip_fan |= BIT(2);
3060 if (reg & BIT(5))
3061 sio_data->skip_fan |= BIT(3);
3062
3063 /* Check if AVCC is on VIN3 */
3064 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3065 if (reg & BIT(0))
3066 sio_data->internal |= BIT(0);
3067
3068 sio_data->beep_pin = superio_inb(sioaddr,
3069 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3070 } else {
3071 int reg;
3072 bool uart6;
3073
3074 superio_select(sioaddr, GPIO);
3075
3076 /* Check for fan4, fan5 */
3077 if (has_five_fans(config)) {
3078 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3079 switch (sio_data->type) {
3080 case it8718:
3081 if (reg & BIT(5))
3082 sio_data->skip_fan |= BIT(3);
3083 if (reg & BIT(4))
3084 sio_data->skip_fan |= BIT(4);
3085 break;
3086 case it8720:
3087 case it8721:
3088 case it8728:
3089 if (!(reg & BIT(5)))
3090 sio_data->skip_fan |= BIT(3);
3091 if (!(reg & BIT(4)))
3092 sio_data->skip_fan |= BIT(4);
3093 break;
3094 default:
3095 break;
3096 }
3097 }
3098
3099 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3100 if (!sio_data->skip_vid) {
3101 /* We need at least 4 VID pins */
3102 if (reg & 0x0f) {
3103 pr_info("VID is disabled (pins used for GPIO)\n");
3104 sio_data->skip_vid = 1;
3105 }
3106 }
3107
3108 /* Check if fan3 is there or not */
3109 if (reg & BIT(6))
3110 sio_data->skip_pwm |= BIT(2);
3111 if (reg & BIT(7))
3112 sio_data->skip_fan |= BIT(2);
3113
3114 /* Check if fan2 is there or not */
3115 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3116 if (reg & BIT(1))
3117 sio_data->skip_pwm |= BIT(1);
3118 if (reg & BIT(2))
3119 sio_data->skip_fan |= BIT(1);
3120
3121 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3122 !(sio_data->skip_vid))
3123 sio_data->vid_value = superio_inb(sioaddr,
3124 IT87_SIO_VID_REG);
3125
3126 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3127
3128 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3129
3130 /*
3131 * The IT8720F has no VIN7 pin, so VCCH5V should always be
3132 * routed internally to VIN7 with an internal divider.
3133 * Curiously, there still is a configuration bit to control
3134 * this, which means it can be set incorrectly. And even
3135 * more curiously, many boards out there are improperly
3136 * configured, even though the IT8720F datasheet claims
3137 * that the internal routing of VCCH5V to VIN7 is the default
3138 * setting. So we force the internal routing in this case.
3139 *
3140 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3141 * If UART6 is enabled, re-route VIN7 to the internal divider
3142 * if that is not already the case.
3143 */
3144 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3145 reg |= BIT(1);
3146 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3147 sio_data->need_in7_reroute = true;
3148 pr_notice("Routing internal VCCH5V to in7\n");
3149 }
3150 if (reg & BIT(0))
3151 sio_data->internal |= BIT(0);
3152 if (reg & BIT(1))
3153 sio_data->internal |= BIT(1);
3154
3155 /*
3156 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3157 * While VIN7 can be routed to the internal voltage divider,
3158 * VIN5 and VIN6 are not available if UART6 is enabled.
3159 *
3160 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3161 * is the temperature source. Since we can not read the
3162 * temperature source here, skip_temp is preliminary.
3163 */
3164 if (uart6) {
3165 sio_data->skip_in |= BIT(5) | BIT(6);
3166 sio_data->skip_temp |= BIT(2);
3167 }
3168
3169 sio_data->beep_pin = superio_inb(sioaddr,
3170 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3171 }
3172 if (sio_data->beep_pin)
3173 pr_info("Beeping is supported\n");
3174
3175 /* Set values based on DMI matches */
3176 if (dmi_data)
3177 sio_data->skip_pwm |= dmi_data->skip_pwm;
3178
3179 if (config->smbus_bitmap) {
3180 u8 reg;
3181
3182 superio_select(sioaddr, PME);
3183 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3184 sio_data->ec_special_config = reg;
3185 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3186 }
3187
3188 exit:
3189 superio_exit(sioaddr, !enabled);
3190 return err;
3191 }
3192
3193 /*
3194 * Some chips seem to have default value 0xff for all limit
3195 * registers. For low voltage limits it makes no sense and triggers
3196 * alarms, so change to 0 instead. For high temperature limits, it
3197 * means -1 degree C, which surprisingly doesn't trigger an alarm,
3198 * but is still confusing, so change to 127 degrees C.
3199 */
3200 static void it87_check_limit_regs(struct it87_data *data)
3201 {
3202 int i, reg;
3203
3204 for (i = 0; i < NUM_VIN_LIMIT; i++) {
3205 reg = it87_read_value(data, IT87_REG_VIN_MIN(i));
3206 if (reg == 0xff)
3207 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3208 }
3209 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
3210 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
3211 if (reg == 0xff)
3212 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
3213 }
3214 }
3215
3216 /* Check if voltage monitors are reset manually or by some reason */
3217 static void it87_check_voltage_monitors_reset(struct it87_data *data)
3218 {
3219 int reg;
3220
3221 reg = it87_read_value(data, IT87_REG_VIN_ENABLE);
3222 if ((reg & 0xff) == 0) {
3223 /* Enable all voltage monitors */
3224 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3225 }
3226 }
3227
3228 /* Check if tachometers are reset manually or by some reason */
3229 static void it87_check_tachometers_reset(struct platform_device *pdev)
3230 {
3231 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3232 struct it87_data *data = platform_get_drvdata(pdev);
3233 u8 mask, fan_main_ctrl;
3234
3235 mask = 0x70 & ~(sio_data->skip_fan << 4);
3236 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3237 if ((fan_main_ctrl & mask) == 0) {
3238 /* Enable all fan tachometers */
3239 fan_main_ctrl |= mask;
3240 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3241 fan_main_ctrl);
3242 }
3243 }
3244
3245 /* Set tachometers to 16-bit mode if needed */
3246 static void it87_check_tachometers_16bit_mode(struct platform_device *pdev)
3247 {
3248 struct it87_data *data = platform_get_drvdata(pdev);
3249 int reg;
3250
3251 if (!has_fan16_config(data))
3252 return;
3253
3254 reg = it87_read_value(data, IT87_REG_FAN_16BIT);
3255 if (~reg & 0x07 & data->has_fan) {
3256 dev_dbg(&pdev->dev,
3257 "Setting fan1-3 to 16-bit mode\n");
3258 it87_write_value(data, IT87_REG_FAN_16BIT,
3259 reg | 0x07);
3260 }
3261 }
3262
3263 static void it87_start_monitoring(struct it87_data *data)
3264 {
3265 it87_write_value(data, IT87_REG_CONFIG,
3266 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3267 | (update_vbat ? 0x41 : 0x01));
3268 }
3269
3270 /* Called when we have found a new IT87. */
3271 static void it87_init_device(struct platform_device *pdev)
3272 {
3273 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3274 struct it87_data *data = platform_get_drvdata(pdev);
3275 int tmp, i;
3276
3277 /*
3278 * For each PWM channel:
3279 * - If it is in automatic mode, setting to manual mode should set
3280 * the fan to full speed by default.
3281 * - If it is in manual mode, we need a mapping to temperature
3282 * channels to use when later setting to automatic mode later.
3283 * Use a 1:1 mapping by default (we are clueless.)
3284 * In both cases, the value can (and should) be changed by the user
3285 * prior to switching to a different mode.
3286 * Note that this is no longer needed for the IT8721F and later, as
3287 * these have separate registers for the temperature mapping and the
3288 * manual duty cycle.
3289 */
3290 for (i = 0; i < NUM_AUTO_PWM; i++) {
3291 data->pwm_temp_map[i] = i;
3292 data->pwm_duty[i] = 0x7f; /* Full speed */
3293 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3294 }
3295
3296 it87_check_limit_regs(data);
3297
3298 /*
3299 * Temperature channels are not forcibly enabled, as they can be
3300 * set to two different sensor types and we can't guess which one
3301 * is correct for a given system. These channels can be enabled at
3302 * run-time through the temp{1-3}_type sysfs accessors if needed.
3303 */
3304
3305 it87_check_voltage_monitors_reset(data);
3306
3307 it87_check_tachometers_reset(pdev);
3308
3309 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3310 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3311
3312 it87_check_tachometers_16bit_mode(pdev);
3313
3314 /* Check for additional fans */
3315 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3316
3317 if (has_four_fans(data) && (tmp & BIT(4)))
3318 data->has_fan |= BIT(3); /* fan4 enabled */
3319 if (has_five_fans(data) && (tmp & BIT(5)))
3320 data->has_fan |= BIT(4); /* fan5 enabled */
3321 if (has_six_fans(data) && (tmp & BIT(2)))
3322 data->has_fan |= BIT(5); /* fan6 enabled */
3323
3324 /* Fan input pins may be used for alternative functions */
3325 data->has_fan &= ~sio_data->skip_fan;
3326
3327 /* Check if pwm5, pwm6 are enabled */
3328 if (has_six_pwm(data)) {
3329 /* The following code may be IT8620E specific */
3330 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3331 if ((tmp & 0xc0) == 0xc0)
3332 sio_data->skip_pwm |= BIT(4);
3333 if (!(tmp & BIT(3)))
3334 sio_data->skip_pwm |= BIT(5);
3335 }
3336
3337 it87_start_monitoring(data);
3338 }
3339
3340 /* Return 1 if and only if the PWM interface is safe to use */
3341 static int it87_check_pwm(struct device *dev)
3342 {
3343 struct it87_data *data = dev_get_drvdata(dev);
3344 /*
3345 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3346 * and polarity set to active low is sign that this is the case so we
3347 * disable pwm control to protect the user.
3348 */
3349 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3350
3351 if ((tmp & 0x87) == 0) {
3352 if (fix_pwm_polarity) {
3353 /*
3354 * The user asks us to attempt a chip reconfiguration.
3355 * This means switching to active high polarity and
3356 * inverting all fan speed values.
3357 */
3358 int i;
3359 u8 pwm[3];
3360
3361 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3362 pwm[i] = it87_read_value(data,
3363 IT87_REG_PWM[i]);
3364
3365 /*
3366 * If any fan is in automatic pwm mode, the polarity
3367 * might be correct, as suspicious as it seems, so we
3368 * better don't change anything (but still disable the
3369 * PWM interface).
3370 */
3371 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3372 dev_info(dev,
3373 "Reconfiguring PWM to active high polarity\n");
3374 it87_write_value(data, IT87_REG_FAN_CTL,
3375 tmp | 0x87);
3376 for (i = 0; i < 3; i++)
3377 it87_write_value(data,
3378 IT87_REG_PWM[i],
3379 0x7f & ~pwm[i]);
3380 return 1;
3381 }
3382
3383 dev_info(dev,
3384 "PWM configuration is too broken to be fixed\n");
3385 }
3386
3387 return 0;
3388 } else if (fix_pwm_polarity) {
3389 dev_info(dev,
3390 "PWM configuration looks sane, won't touch\n");
3391 }
3392
3393 return 1;
3394 }
3395
3396 static int it87_probe(struct platform_device *pdev)
3397 {
3398 struct it87_data *data;
3399 struct resource *res;
3400 struct device *dev = &pdev->dev;
3401 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3402 int enable_pwm_interface;
3403 struct device *hwmon_dev;
3404 int err;
3405
3406 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3407 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3408 DRVNAME)) {
3409 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3410 (unsigned long)res->start,
3411 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3412 return -EBUSY;
3413 }
3414
3415 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3416 if (!data)
3417 return -ENOMEM;
3418
3419 data->addr = res->start;
3420 data->sioaddr = sio_data->sioaddr;
3421 data->type = sio_data->type;
3422 data->smbus_bitmap = sio_data->smbus_bitmap;
3423 data->ec_special_config = sio_data->ec_special_config;
3424 data->features = it87_devices[sio_data->type].features;
3425 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3426 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3427 /*
3428 * IT8705F Datasheet 0.4.1, 3h == Version G.
3429 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3430 * These are the first revisions with 16-bit tachometer support.
3431 */
3432 switch (data->type) {
3433 case it87:
3434 if (sio_data->revision >= 0x03) {
3435 data->features &= ~FEAT_OLD_AUTOPWM;
3436 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3437 }
3438 break;
3439 case it8712:
3440 if (sio_data->revision >= 0x08) {
3441 data->features &= ~FEAT_OLD_AUTOPWM;
3442 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3443 FEAT_FIVE_FANS;
3444 }
3445 break;
3446 default:
3447 break;
3448 }
3449
3450 platform_set_drvdata(pdev, data);
3451
3452 mutex_init(&data->update_lock);
3453
3454 err = smbus_disable(data);
3455 if (err)
3456 return err;
3457
3458 /* Now, we do the remaining detection. */
3459 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3460 it87_read_value(data, IT87_REG_CHIPID) != 0x90) {
3461 smbus_enable(data);
3462 return -ENODEV;
3463 }
3464
3465 /* Check PWM configuration */
3466 enable_pwm_interface = it87_check_pwm(dev);
3467 if (!enable_pwm_interface)
3468 dev_info(dev,
3469 "Detected broken BIOS defaults, disabling PWM interface\n");
3470
3471 /* Starting with IT8721F, we handle scaling of internal voltages */
3472 if (has_scaling(data)) {
3473 if (sio_data->internal & BIT(0))
3474 data->in_scaled |= BIT(3); /* in3 is AVCC */
3475 if (sio_data->internal & BIT(1))
3476 data->in_scaled |= BIT(7); /* in7 is VSB */
3477 if (sio_data->internal & BIT(2))
3478 data->in_scaled |= BIT(8); /* in8 is Vbat */
3479 if (sio_data->internal & BIT(3))
3480 data->in_scaled |= BIT(9); /* in9 is AVCC */
3481 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3482 sio_data->type == it8783) {
3483 if (sio_data->internal & BIT(0))
3484 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3485 if (sio_data->internal & BIT(1))
3486 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3487 }
3488
3489 data->has_temp = 0x07;
3490 if (sio_data->skip_temp & BIT(2)) {
3491 if (sio_data->type == it8782 &&
3492 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3493 data->has_temp &= ~BIT(2);
3494 }
3495
3496 data->in_internal = sio_data->internal;
3497 data->need_in7_reroute = sio_data->need_in7_reroute;
3498 data->has_in = 0x3ff & ~sio_data->skip_in;
3499
3500 if (has_four_temp(data)) {
3501 data->has_temp |= BIT(3);
3502 } else if (has_six_temp(data)) {
3503 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3504
3505 /* Check for additional temperature sensors */
3506 if ((reg & 0x03) >= 0x02)
3507 data->has_temp |= BIT(3);
3508 if (((reg >> 2) & 0x03) >= 0x02)
3509 data->has_temp |= BIT(4);
3510 if (((reg >> 4) & 0x03) >= 0x02)
3511 data->has_temp |= BIT(5);
3512
3513 /* Check for additional voltage sensors */
3514 if ((reg & 0x03) == 0x01)
3515 data->has_in |= BIT(10);
3516 if (((reg >> 2) & 0x03) == 0x01)
3517 data->has_in |= BIT(11);
3518 if (((reg >> 4) & 0x03) == 0x01)
3519 data->has_in |= BIT(12);
3520 }
3521
3522 data->has_beep = !!sio_data->beep_pin;
3523
3524 /* Initialize the IT87 chip */
3525 it87_init_device(pdev);
3526
3527 smbus_enable(data);
3528
3529 if (!sio_data->skip_vid) {
3530 data->has_vid = true;
3531 data->vrm = vid_which_vrm();
3532 /* VID reading from Super-I/O config space if available */
3533 data->vid = sio_data->vid_value;
3534 }
3535
3536 /* Prepare for sysfs hooks */
3537 data->groups[0] = &it87_group;
3538 data->groups[1] = &it87_group_in;
3539 data->groups[2] = &it87_group_temp;
3540 data->groups[3] = &it87_group_fan;
3541
3542 if (enable_pwm_interface) {
3543 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3544 data->has_pwm &= ~sio_data->skip_pwm;
3545
3546 data->groups[4] = &it87_group_pwm;
3547 if (has_old_autopwm(data) || has_newer_autopwm(data))
3548 data->groups[5] = &it87_group_auto_pwm;
3549 }
3550
3551 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3552 it87_devices[sio_data->type].name,
3553 data, data->groups);
3554 return PTR_ERR_OR_ZERO(hwmon_dev);
3555 }
3556
3557 static void it87_resume_sio(struct platform_device *pdev)
3558 {
3559 struct it87_data *data = dev_get_drvdata(&pdev->dev);
3560 int err;
3561 int reg2c;
3562
3563 if (!data->need_in7_reroute)
3564 return;
3565
3566 err = superio_enter(data->sioaddr, has_noconf(data));
3567 if (err) {
3568 dev_warn(&pdev->dev,
3569 "Unable to enter Super I/O to reroute in7 (%d)",
3570 err);
3571 return;
3572 }
3573
3574 superio_select(data->sioaddr, GPIO);
3575
3576 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG);
3577 if (!(reg2c & BIT(1))) {
3578 dev_dbg(&pdev->dev,
3579 "Routing internal VCCH5V to in7 again");
3580
3581 reg2c |= BIT(1);
3582 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG,
3583 reg2c);
3584 }
3585
3586 superio_exit(data->sioaddr, has_noconf(data));
3587 }
3588
3589 static int it87_resume(struct device *dev)
3590 {
3591 struct platform_device *pdev = to_platform_device(dev);
3592 struct it87_data *data = dev_get_drvdata(dev);
3593
3594 it87_resume_sio(pdev);
3595
3596 it87_lock(data);
3597
3598 it87_check_pwm(dev);
3599 it87_check_limit_regs(data);
3600 it87_check_voltage_monitors_reset(data);
3601 it87_check_tachometers_reset(pdev);
3602 it87_check_tachometers_16bit_mode(pdev);
3603
3604 it87_start_monitoring(data);
3605
3606 /* force update */
3607 data->valid = false;
3608
3609 it87_unlock(data);
3610
3611 it87_update_device(dev);
3612
3613 return 0;
3614 }
3615
3616 static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume);
3617
3618 static struct platform_driver it87_driver = {
3619 .driver = {
3620 .name = DRVNAME,
3621 .pm = pm_sleep_ptr(&it87_dev_pm_ops),
3622 },
3623 .probe = it87_probe,
3624 };
3625
3626 static int __init it87_device_add(int index, unsigned short address,
3627 const struct it87_sio_data *sio_data)
3628 {
3629 struct platform_device *pdev;
3630 struct resource res = {
3631 .start = address + IT87_EC_OFFSET,
3632 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3633 .name = DRVNAME,
3634 .flags = IORESOURCE_IO,
3635 };
3636 int err;
3637
3638 err = acpi_check_resource_conflict(&res);
3639 if (err) {
3640 if (!ignore_resource_conflict)
3641 return err;
3642 }
3643
3644 pdev = platform_device_alloc(DRVNAME, address);
3645 if (!pdev)
3646 return -ENOMEM;
3647
3648 err = platform_device_add_resources(pdev, &res, 1);
3649 if (err) {
3650 pr_err("Device resource addition failed (%d)\n", err);
3651 goto exit_device_put;
3652 }
3653
3654 err = platform_device_add_data(pdev, sio_data,
3655 sizeof(struct it87_sio_data));
3656 if (err) {
3657 pr_err("Platform data allocation failed\n");
3658 goto exit_device_put;
3659 }
3660
3661 err = platform_device_add(pdev);
3662 if (err) {
3663 pr_err("Device addition failed (%d)\n", err);
3664 goto exit_device_put;
3665 }
3666
3667 it87_pdev[index] = pdev;
3668 return 0;
3669
3670 exit_device_put:
3671 platform_device_put(pdev);
3672 return err;
3673 }
3674
3675 /* callback function for DMI */
3676 static int it87_dmi_cb(const struct dmi_system_id *dmi_entry)
3677 {
3678 dmi_data = dmi_entry->driver_data;
3679
3680 if (dmi_data && dmi_data->skip_pwm)
3681 pr_info("Disabling pwm2 due to hardware constraints\n");
3682
3683 return 1;
3684 }
3685
3686 /*
3687 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3688 * connected to a fan, but to something else. One user
3689 * has reported instant system power-off when changing
3690 * the PWM2 duty cycle, so we disable it.
3691 * I use the board name string as the trigger in case
3692 * the same board is ever used in other systems.
3693 */
3694 static struct it87_dmi_data nvidia_fn68pt = {
3695 .skip_pwm = BIT(1),
3696 };
3697
3698 #define IT87_DMI_MATCH_VND(vendor, name, cb, data) \
3699 { \
3700 .callback = cb, \
3701 .matches = { \
3702 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \
3703 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \
3704 }, \
3705 .driver_data = data, \
3706 }
3707
3708 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3709 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt),
3710 { }
3711
3712 };
3713 MODULE_DEVICE_TABLE(dmi, it87_dmi_table);
3714
3715 static int __init sm_it87_init(void)
3716 {
3717 int sioaddr[2] = { REG_2E, REG_4E };
3718 struct it87_sio_data sio_data;
3719 unsigned short isa_address[2];
3720 bool found = false;
3721 int i, err;
3722
3723 err = platform_driver_register(&it87_driver);
3724 if (err)
3725 return err;
3726
3727 dmi_check_system(it87_dmi_table);
3728
3729 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3730 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3731 isa_address[i] = 0;
3732 err = it87_find(sioaddr[i], &isa_address[i], &sio_data, i);
3733 if (err || isa_address[i] == 0)
3734 continue;
3735 /*
3736 * Don't register second chip if its ISA address matches
3737 * the first chip's ISA address.
3738 */
3739 if (i && isa_address[i] == isa_address[0])
3740 break;
3741
3742 err = it87_device_add(i, isa_address[i], &sio_data);
3743 if (err)
3744 goto exit_dev_unregister;
3745
3746 found = true;
3747
3748 /*
3749 * IT8705F may respond on both SIO addresses.
3750 * Stop probing after finding one.
3751 */
3752 if (sio_data.type == it87)
3753 break;
3754 }
3755
3756 if (!found) {
3757 err = -ENODEV;
3758 goto exit_unregister;
3759 }
3760 return 0;
3761
3762 exit_dev_unregister:
3763 /* NULL check handled by platform_device_unregister */
3764 platform_device_unregister(it87_pdev[0]);
3765 exit_unregister:
3766 platform_driver_unregister(&it87_driver);
3767 return err;
3768 }
3769
3770 static void __exit sm_it87_exit(void)
3771 {
3772 /* NULL check handled by platform_device_unregister */
3773 platform_device_unregister(it87_pdev[1]);
3774 platform_device_unregister(it87_pdev[0]);
3775 platform_driver_unregister(&it87_driver);
3776 }
3777
3778 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3779 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3780
3781 module_param_array(force_id, ushort, &force_id_cnt, 0);
3782 MODULE_PARM_DESC(force_id, "Override one or more detected device ID(s)");
3783
3784 module_param(ignore_resource_conflict, bool, 0);
3785 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
3786
3787 module_param(update_vbat, bool, 0);
3788 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3789
3790 module_param(fix_pwm_polarity, bool, 0);
3791 MODULE_PARM_DESC(fix_pwm_polarity,
3792 "Force PWM polarity to active high (DANGEROUS)");
3793
3794 MODULE_LICENSE("GPL");
3795
3796 module_init(sm_it87_init);
3797 module_exit(sm_it87_exit);
Kernel DRM miscellaneous fixes and cross-tree changes