1 // SPDX-License-Identifier: GPL-2.0-only
2 /* ------------------------------------------------------------------------- */
3 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
4 /* ------------------------------------------------------------------------- */
5 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
6 * <Peter dot Milne at D hyphen TACQ dot com>
8 * With acknowledgements to i2c-algo-ibm_ocp.c by
9 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
11 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
13 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
15 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
16 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
18 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
20 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
21 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
22 * - Make it work with IXP46x chips
23 * - Cleanup function names, coding style, etc
25 * - writing to local target address causes latchup on iop331.
26 * fix: driver refuses to address self.
29 #include <linux/interrupt.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/errno.h>
35 #include <linux/platform_device.h>
36 #include <linux/i2c.h>
38 #include <linux/gpio/consumer.h>
40 #include "i2c-iop3xx.h"
42 /* global unit counter */
45 static inline unsigned char
46 iic_cook_addr(struct i2c_msg
*msg
)
50 addr
= i2c_8bit_addr_from_msg(msg
);
56 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
58 /* Follows devman 9.3 */
59 __raw_writel(IOP3XX_ICR_UNIT_RESET
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
60 __raw_writel(IOP3XX_ISR_CLEARBITS
, iop3xx_adap
->ioaddr
+ SR_OFFSET
);
61 __raw_writel(0, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
65 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
67 u32 cr
= IOP3XX_ICR_GCD
| IOP3XX_ICR_SCLEN
| IOP3XX_ICR_UE
;
70 * Every time unit enable is asserted, GPOD needs to be cleared
71 * on IOP3XX to avoid data corruption on the bus. We use the
72 * gpiod_set_raw_value() to make sure the 0 hits the hardware
73 * GPOD register. These descriptors are only passed along to
74 * the device if this is necessary.
76 if (iop3xx_adap
->gpio_scl
)
77 gpiod_set_raw_value(iop3xx_adap
->gpio_scl
, 0);
78 if (iop3xx_adap
->gpio_sda
)
79 gpiod_set_raw_value(iop3xx_adap
->gpio_sda
, 0);
81 /* NB SR bits not same position as CR IE bits :-( */
82 iop3xx_adap
->SR_enabled
=
83 IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
|
84 IOP3XX_ISR_RXFULL
| IOP3XX_ISR_TXEMPTY
;
86 cr
|= IOP3XX_ICR_ALD_IE
| IOP3XX_ICR_BERR_IE
|
87 IOP3XX_ICR_RXFULL_IE
| IOP3XX_ICR_TXEMPTY_IE
;
89 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
93 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
95 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
97 cr
&= ~(IOP3XX_ICR_MSTART
| IOP3XX_ICR_TBYTE
|
98 IOP3XX_ICR_MSTOP
| IOP3XX_ICR_SCLEN
);
100 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
104 * NB: the handler has to clear the source of the interrupt!
105 * Then it passes the SR flags of interest to BH via adap data
108 iop3xx_i2c_irq_handler(int this_irq
, void *dev_id
)
110 struct i2c_algo_iop3xx_data
*iop3xx_adap
= dev_id
;
111 u32 sr
= __raw_readl(iop3xx_adap
->ioaddr
+ SR_OFFSET
);
113 if ((sr
&= iop3xx_adap
->SR_enabled
)) {
114 __raw_writel(sr
, iop3xx_adap
->ioaddr
+ SR_OFFSET
);
115 iop3xx_adap
->SR_received
|= sr
;
116 wake_up_interruptible(&iop3xx_adap
->waitq
);
121 /* check all error conditions, clear them , report most important */
123 iop3xx_i2c_error(u32 sr
)
127 if ((sr
& IOP3XX_ISR_BERRD
)) {
131 if ((sr
& IOP3XX_ISR_ALD
)) {
139 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
144 spin_lock_irqsave(&iop3xx_adap
->lock
, flags
);
145 sr
= iop3xx_adap
->SR_received
;
146 iop3xx_adap
->SR_received
= 0;
147 spin_unlock_irqrestore(&iop3xx_adap
->lock
, flags
);
153 * sleep until interrupted, then recover and analyse the SR
156 typedef int (*compare_func
)(unsigned test
, unsigned mask
);
157 /* returns 1 on correct comparison */
160 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data
*iop3xx_adap
,
161 unsigned flags
, unsigned *status
,
162 compare_func compare
)
170 interrupted
= wait_event_interruptible_timeout (
172 (done
= compare(sr
= iop3xx_i2c_get_srstat(iop3xx_adap
), flags
)),
175 if ((rc
= iop3xx_i2c_error(sr
)) < 0) {
178 } else if (!interrupted
) {
190 * Concrete compare_funcs
193 all_bits_clear(unsigned test
, unsigned mask
)
195 return (test
& mask
) == 0;
199 any_bits_set(unsigned test
, unsigned mask
)
201 return (test
& mask
) != 0;
205 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
207 return iop3xx_i2c_wait_event(
209 IOP3XX_ISR_TXEMPTY
| IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
,
210 status
, any_bits_set
);
214 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
216 return iop3xx_i2c_wait_event(
218 IOP3XX_ISR_RXFULL
| IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
,
219 status
, any_bits_set
);
223 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
225 return iop3xx_i2c_wait_event(
226 iop3xx_adap
, IOP3XX_ISR_UNITBUSY
, status
, all_bits_clear
);
230 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data
*iop3xx_adap
,
233 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
237 /* avoid writing to local target address (hangs on 80331),
238 * forbidden in Intel developer manual
240 if (msg
->addr
== MYSAR
) {
244 __raw_writel(iic_cook_addr(msg
), iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
246 cr
&= ~(IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
);
247 cr
|= IOP3XX_ICR_MSTART
| IOP3XX_ICR_TBYTE
;
249 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
250 rc
= iop3xx_i2c_wait_tx_done(iop3xx_adap
, &status
);
256 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data
*iop3xx_adap
, char byte
,
259 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
263 __raw_writel(byte
, iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
264 cr
&= ~IOP3XX_ICR_MSTART
;
266 cr
|= IOP3XX_ICR_MSTOP
;
268 cr
&= ~IOP3XX_ICR_MSTOP
;
270 cr
|= IOP3XX_ICR_TBYTE
;
271 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
272 rc
= iop3xx_i2c_wait_tx_done(iop3xx_adap
, &status
);
278 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data
*iop3xx_adap
, char *byte
,
281 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
285 cr
&= ~IOP3XX_ICR_MSTART
;
288 cr
|= IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
;
290 cr
&= ~(IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
);
292 cr
|= IOP3XX_ICR_TBYTE
;
293 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
295 rc
= iop3xx_i2c_wait_rx_done(iop3xx_adap
, &status
);
297 *byte
= __raw_readl(iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
303 iop3xx_i2c_writebytes(struct i2c_adapter
*i2c_adap
, const char *buf
, int count
)
305 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
309 for (ii
= 0; rc
== 0 && ii
!= count
; ++ii
)
310 rc
= iop3xx_i2c_write_byte(iop3xx_adap
, buf
[ii
], ii
== count
-1);
315 iop3xx_i2c_readbytes(struct i2c_adapter
*i2c_adap
, char *buf
, int count
)
317 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
321 for (ii
= 0; rc
== 0 && ii
!= count
; ++ii
)
322 rc
= iop3xx_i2c_read_byte(iop3xx_adap
, &buf
[ii
], ii
== count
-1);
328 * Description: This function implements combined transactions. Combined
329 * transactions consist of combinations of reading and writing blocks of data.
330 * FROM THE SAME ADDRESS
331 * Each transfer (i.e. a read or a write) is separated by a repeated start
335 iop3xx_i2c_handle_msg(struct i2c_adapter
*i2c_adap
, struct i2c_msg
*pmsg
)
337 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
340 rc
= iop3xx_i2c_send_target_addr(iop3xx_adap
, pmsg
);
345 if ((pmsg
->flags
&I2C_M_RD
)) {
346 return iop3xx_i2c_readbytes(i2c_adap
, pmsg
->buf
, pmsg
->len
);
348 return iop3xx_i2c_writebytes(i2c_adap
, pmsg
->buf
, pmsg
->len
);
353 iop3xx_i2c_xfer(struct i2c_adapter
*i2c_adap
, struct i2c_msg
*msgs
,
356 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
361 iop3xx_i2c_wait_idle(iop3xx_adap
, &status
);
362 iop3xx_i2c_reset(iop3xx_adap
);
363 iop3xx_i2c_enable(iop3xx_adap
);
365 for (im
= 0; ret
== 0 && im
!= num
; im
++) {
366 ret
= iop3xx_i2c_handle_msg(i2c_adap
, &msgs
[im
]);
369 iop3xx_i2c_transaction_cleanup(iop3xx_adap
);
378 iop3xx_i2c_func(struct i2c_adapter
*adap
)
380 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
383 static const struct i2c_algorithm iop3xx_i2c_algo
= {
384 .xfer
= iop3xx_i2c_xfer
,
385 .functionality
= iop3xx_i2c_func
,
389 iop3xx_i2c_remove(struct platform_device
*pdev
)
391 struct i2c_adapter
*padapter
= platform_get_drvdata(pdev
);
392 struct i2c_algo_iop3xx_data
*adapter_data
=
393 (struct i2c_algo_iop3xx_data
*)padapter
->algo_data
;
394 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
395 unsigned long cr
= __raw_readl(adapter_data
->ioaddr
+ CR_OFFSET
);
398 * Disable the actual HW unit
400 cr
&= ~(IOP3XX_ICR_ALD_IE
| IOP3XX_ICR_BERR_IE
|
401 IOP3XX_ICR_RXFULL_IE
| IOP3XX_ICR_TXEMPTY_IE
);
402 __raw_writel(cr
, adapter_data
->ioaddr
+ CR_OFFSET
);
404 iounmap(adapter_data
->ioaddr
);
405 release_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
);
411 iop3xx_i2c_probe(struct platform_device
*pdev
)
413 struct resource
*res
;
415 struct i2c_adapter
*new_adapter
;
416 struct i2c_algo_iop3xx_data
*adapter_data
;
418 new_adapter
= kzalloc(sizeof(struct i2c_adapter
), GFP_KERNEL
);
424 adapter_data
= kzalloc(sizeof(struct i2c_algo_iop3xx_data
), GFP_KERNEL
);
430 adapter_data
->gpio_scl
= devm_gpiod_get_optional(&pdev
->dev
,
433 if (IS_ERR(adapter_data
->gpio_scl
)) {
434 ret
= PTR_ERR(adapter_data
->gpio_scl
);
437 adapter_data
->gpio_sda
= devm_gpiod_get_optional(&pdev
->dev
,
440 if (IS_ERR(adapter_data
->gpio_sda
)) {
441 ret
= PTR_ERR(adapter_data
->gpio_sda
);
445 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
451 if (!request_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
, pdev
->name
)) {
456 /* set the adapter enumeration # */
457 adapter_data
->id
= i2c_id
++;
459 adapter_data
->ioaddr
= ioremap(res
->start
, IOP3XX_I2C_IO_SIZE
);
460 if (!adapter_data
->ioaddr
) {
465 irq
= platform_get_irq(pdev
, 0);
470 ret
= request_irq(irq
, iop3xx_i2c_irq_handler
, 0,
471 pdev
->name
, adapter_data
);
476 memcpy(new_adapter
->name
, pdev
->name
, strlen(pdev
->name
));
477 new_adapter
->owner
= THIS_MODULE
;
478 new_adapter
->class = I2C_CLASS_HWMON
;
479 new_adapter
->dev
.parent
= &pdev
->dev
;
480 new_adapter
->dev
.of_node
= pdev
->dev
.of_node
;
481 new_adapter
->nr
= pdev
->id
;
484 * Default values...should these come in from board code?
486 new_adapter
->timeout
= HZ
;
487 new_adapter
->algo
= &iop3xx_i2c_algo
;
489 init_waitqueue_head(&adapter_data
->waitq
);
490 spin_lock_init(&adapter_data
->lock
);
492 iop3xx_i2c_reset(adapter_data
);
493 iop3xx_i2c_enable(adapter_data
);
495 platform_set_drvdata(pdev
, new_adapter
);
496 new_adapter
->algo_data
= adapter_data
;
498 i2c_add_numbered_adapter(new_adapter
);
503 iounmap(adapter_data
->ioaddr
);
506 release_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
);
518 static const struct of_device_id i2c_iop3xx_match
[] = {
519 { .compatible
= "intel,iop3xx-i2c", },
520 { .compatible
= "intel,ixp4xx-i2c", },
523 MODULE_DEVICE_TABLE(of
, i2c_iop3xx_match
);
525 static struct platform_driver iop3xx_i2c_driver
= {
526 .probe
= iop3xx_i2c_probe
,
527 .remove
= iop3xx_i2c_remove
,
529 .name
= "IOP3xx-I2C",
530 .of_match_table
= i2c_iop3xx_match
,
534 module_platform_driver(iop3xx_i2c_driver
);
536 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
537 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
538 MODULE_LICENSE("GPL");
539 MODULE_ALIAS("platform:IOP3xx-I2C");