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drm/modes: Fix drm_mode_vrefres() docs
[drm/drm-misc.git] / drivers / i2c / busses / i2c-jz4780.c
blob664a5471d9335781ee5f361add84380ebb35b012
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Ingenic JZ4780 I2C bus driver
4 *
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
6 * Copyright (C) 2015 Imagination Technologies
7 * Copyright (C) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
8 */
9
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 #include <linux/time.h>
26
27 #define JZ4780_I2C_CTRL 0x00
28 #define JZ4780_I2C_TAR 0x04
29 #define JZ4780_I2C_SAR 0x08
30 #define JZ4780_I2C_DC 0x10
31 #define JZ4780_I2C_SHCNT 0x14
32 #define JZ4780_I2C_SLCNT 0x18
33 #define JZ4780_I2C_FHCNT 0x1C
34 #define JZ4780_I2C_FLCNT 0x20
35 #define JZ4780_I2C_INTST 0x2C
36 #define JZ4780_I2C_INTM 0x30
37 #define JZ4780_I2C_RXTL 0x38
38 #define JZ4780_I2C_TXTL 0x3C
39 #define JZ4780_I2C_CINTR 0x40
40 #define JZ4780_I2C_CRXUF 0x44
41 #define JZ4780_I2C_CRXOF 0x48
42 #define JZ4780_I2C_CTXOF 0x4C
43 #define JZ4780_I2C_CRXREQ 0x50
44 #define JZ4780_I2C_CTXABRT 0x54
45 #define JZ4780_I2C_CRXDONE 0x58
46 #define JZ4780_I2C_CACT 0x5C
47 #define JZ4780_I2C_CSTP 0x60
48 #define JZ4780_I2C_CSTT 0x64
49 #define JZ4780_I2C_CGC 0x68
50 #define JZ4780_I2C_ENB 0x6C
51 #define JZ4780_I2C_STA 0x70
52 #define JZ4780_I2C_TXABRT 0x80
53 #define JZ4780_I2C_DMACR 0x88
54 #define JZ4780_I2C_DMATDLR 0x8C
55 #define JZ4780_I2C_DMARDLR 0x90
56 #define JZ4780_I2C_SDASU 0x94
57 #define JZ4780_I2C_ACKGC 0x98
58 #define JZ4780_I2C_ENSTA 0x9C
59 #define JZ4780_I2C_SDAHD 0xD0
60 #define X1000_I2C_SDAHD 0x7C
61
62 #define JZ4780_I2C_CTRL_STPHLD BIT(7)
63 #define JZ4780_I2C_CTRL_SLVDIS BIT(6)
64 #define JZ4780_I2C_CTRL_REST BIT(5)
65 #define JZ4780_I2C_CTRL_MATP BIT(4)
66 #define JZ4780_I2C_CTRL_SATP BIT(3)
67 #define JZ4780_I2C_CTRL_SPDF BIT(2)
68 #define JZ4780_I2C_CTRL_SPDS BIT(1)
69 #define JZ4780_I2C_CTRL_MD BIT(0)
70
71 #define JZ4780_I2C_STA_SLVACT BIT(6)
72 #define JZ4780_I2C_STA_MSTACT BIT(5)
73 #define JZ4780_I2C_STA_RFF BIT(4)
74 #define JZ4780_I2C_STA_RFNE BIT(3)
75 #define JZ4780_I2C_STA_TFE BIT(2)
76 #define JZ4780_I2C_STA_TFNF BIT(1)
77 #define JZ4780_I2C_STA_ACT BIT(0)
78
79 #define X1000_I2C_DC_STOP BIT(9)
80
81 #define JZ4780_I2C_INTST_IGC BIT(11)
82 #define JZ4780_I2C_INTST_ISTT BIT(10)
83 #define JZ4780_I2C_INTST_ISTP BIT(9)
84 #define JZ4780_I2C_INTST_IACT BIT(8)
85 #define JZ4780_I2C_INTST_RXDN BIT(7)
86 #define JZ4780_I2C_INTST_TXABT BIT(6)
87 #define JZ4780_I2C_INTST_RDREQ BIT(5)
88 #define JZ4780_I2C_INTST_TXEMP BIT(4)
89 #define JZ4780_I2C_INTST_TXOF BIT(3)
90 #define JZ4780_I2C_INTST_RXFL BIT(2)
91 #define JZ4780_I2C_INTST_RXOF BIT(1)
92 #define JZ4780_I2C_INTST_RXUF BIT(0)
93
94 #define JZ4780_I2C_INTM_MIGC BIT(11)
95 #define JZ4780_I2C_INTM_MISTT BIT(10)
96 #define JZ4780_I2C_INTM_MISTP BIT(9)
97 #define JZ4780_I2C_INTM_MIACT BIT(8)
98 #define JZ4780_I2C_INTM_MRXDN BIT(7)
99 #define JZ4780_I2C_INTM_MTXABT BIT(6)
100 #define JZ4780_I2C_INTM_MRDREQ BIT(5)
101 #define JZ4780_I2C_INTM_MTXEMP BIT(4)
102 #define JZ4780_I2C_INTM_MTXOF BIT(3)
103 #define JZ4780_I2C_INTM_MRXFL BIT(2)
104 #define JZ4780_I2C_INTM_MRXOF BIT(1)
105 #define JZ4780_I2C_INTM_MRXUF BIT(0)
106
107 #define JZ4780_I2C_DC_READ BIT(8)
108
109 #define JZ4780_I2C_SDAHD_HDENB BIT(8)
110
111 #define JZ4780_I2C_ENB_I2C BIT(0)
112
113 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
114 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
115 #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
116 #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
117
118 #define JZ4780_I2C_FIFO_LEN 16
119
120 #define X1000_I2C_FIFO_LEN 64
121
122 #define JZ4780_I2C_TIMEOUT 300
123
124 #define BUFSIZE 200
125
126 enum ingenic_i2c_version {
127 ID_JZ4780,
128 ID_X1000,
129 };
130
131 /* ingenic_i2c_config: SoC specific config data. */
132 struct ingenic_i2c_config {
133 enum ingenic_i2c_version version;
134
135 int fifosize;
136 int tx_level;
137 int rx_level;
138 };
139
140 struct jz4780_i2c {
141 void __iomem *iomem;
142 int irq;
143 struct clk *clk;
144 struct i2c_adapter adap;
145 const struct ingenic_i2c_config *cdata;
146
147 /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */
148 spinlock_t lock;
149
150 /* beginning of lock scope */
151 unsigned char *rbuf;
152 int rd_total_len;
153 int rd_data_xfered;
154 int rd_cmd_xfered;
155
156 unsigned char *wbuf;
157 int wt_len;
158
159 int is_write;
160 int stop_hold;
161 int speed;
162
163 int data_buf[BUFSIZE];
164 int cmd_buf[BUFSIZE];
165 int cmd;
166
167 /* end of lock scope */
168 struct completion trans_waitq;
169 };
170
171 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
172 unsigned long offset)
173 {
174 return readw(i2c->iomem + offset);
175 }
176
177 static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
178 unsigned long offset, unsigned short val)
179 {
180 writew(val, i2c->iomem + offset);
181 }
182
183 static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
184 {
185 unsigned short regval;
186 unsigned long loops = 5;
187
188 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
189
190 do {
191 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
192 if (!(regval & JZ4780_I2C_ENB_I2C))
193 return 0;
194
195 usleep_range(5000, 15000);
196 } while (--loops);
197
198 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
199 return -ETIMEDOUT;
200 }
201
202 static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
203 {
204 unsigned short regval;
205 unsigned long loops = 5;
206
207 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
208
209 do {
210 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
211 if (regval & JZ4780_I2C_ENB_I2C)
212 return 0;
213
214 usleep_range(5000, 15000);
215 } while (--loops);
216
217 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
218 return -ETIMEDOUT;
219 }
220
221 static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
222 {
223 unsigned short regval;
224 unsigned long loops = 5;
225
226 do {
227 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
228 if ((regval & JZ4780_I2C_STA_TFE) &&
229 !(regval & JZ4780_I2C_STA_MSTACT))
230 break;
231
232 usleep_range(5000, 15000);
233 } while (--loops);
234
235 if (loops) {
236 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
237 return 0;
238 }
239
240 dev_err(&i2c->adap.dev,
241 "set device to address 0x%02x failed, STA=0x%04x\n",
242 address, regval);
243
244 return -ENXIO;
245 }
246
247 static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
248 {
249 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
250 int cnt_high = 0; /* HIGH period count of the SCL clock */
251 int cnt_low = 0; /* LOW period count of the SCL clock */
252 int cnt_period = 0; /* period count of the SCL clock */
253 int setup_time = 0;
254 int hold_time = 0;
255 unsigned short tmp = 0;
256 int i2c_clk = i2c->speed;
257
258 if (jz4780_i2c_disable(i2c))
259 dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
260
261 /*
262 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
263 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
264 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns
265 */
266 cnt_period = dev_clk_khz / i2c_clk;
267
268 if (i2c_clk <= 100)
269 cnt_high = (cnt_period * 4000) / (4700 + 4000);
270 else
271 cnt_high = (cnt_period * 600) / (1300 + 600);
272
273 cnt_low = cnt_period - cnt_high;
274
275 /*
276 * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because
277 * normal read are 2 messages, we cannot disable i2c controller
278 * between these two messages, this means that we must always set
279 * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL
280 *
281 */
282 if (i2c_clk <= 100) {
283 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
284 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
285 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
286
287 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
288 JZ4780_I2CSHCNT_ADJUST(cnt_high));
289 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
290 JZ4780_I2CSLCNT_ADJUST(cnt_low));
291 } else {
292 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
293 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
294 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
295
296 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
297 JZ4780_I2CFHCNT_ADJUST(cnt_high));
298 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
299 JZ4780_I2CFLCNT_ADJUST(cnt_low));
300 }
301
302 /*
303 * a i2c device must internally provide a hold time at least 300ns
304 * tHD:DAT
305 * Standard Mode: min=300ns, max=3450ns
306 * Fast Mode: min=0ns, max=900ns
307 * tSU:DAT
308 * Standard Mode: min=250ns, max=infinite
309 * Fast Mode: min=100(250ns is recommended), max=infinite
310 *
311 * 1i2c_clk = 10^6 / dev_clk_khz
312 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
313 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
314 *
315 * The actual hold time is (SDAHD + 1) * (i2c_clk period).
316 *
317 * Length of setup time calculated using (SDASU - 1) * (ic_clk_period)
318 *
319 */
320 if (i2c_clk <= 100) { /* standard mode */
321 setup_time = 300;
322 hold_time = 400;
323 } else {
324 setup_time = 450;
325 hold_time = 450;
326 }
327
328 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
329 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
330
331 if (setup_time > 255)
332 setup_time = 255;
333
334 if (setup_time <= 0)
335 setup_time = 1;
336
337 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
338
339 if (hold_time > 255)
340 hold_time = 255;
341
342 if (hold_time >= 0) {
343 /*i2c hold time enable */
344 if (i2c->cdata->version >= ID_X1000) {
345 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, hold_time);
346 } else {
347 hold_time |= JZ4780_I2C_SDAHD_HDENB;
348 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
349 }
350 } else {
351 /* disable hold time */
352 if (i2c->cdata->version >= ID_X1000)
353 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, 0);
354 else
355 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
356 }
357
358 return 0;
359 }
360
361 static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
362 {
363 int ret;
364 unsigned long flags;
365 unsigned short tmp;
366
367 spin_lock_irqsave(&i2c->lock, flags);
368
369 /* can send stop now if need */
370 if (i2c->cdata->version < ID_X1000) {
371 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
372 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
373 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
374 }
375
376 /* disable all interrupts first */
377 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
378
379 /* then clear all interrupts */
380 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
381 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
382
383 /* then disable the controller */
384 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
385 tmp &= ~JZ4780_I2C_ENB_I2C;
386 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
387 udelay(10);
388 tmp |= JZ4780_I2C_ENB_I2C;
389 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
390
391 spin_unlock_irqrestore(&i2c->lock, flags);
392
393 ret = jz4780_i2c_disable(i2c);
394 if (ret)
395 dev_err(&i2c->adap.dev,
396 "unable to disable device during cleanup!\n");
397
398 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
399 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
400 dev_err(&i2c->adap.dev,
401 "device has interrupts after a complete cleanup!\n");
402
403 return ret;
404 }
405
406 static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
407 {
408 jz4780_i2c_set_speed(i2c);
409 return jz4780_i2c_enable(i2c);
410 }
411
412 static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c,
413 int cmd_count,
414 int cmd_left)
415 {
416 int i;
417
418 for (i = 0; i < cmd_count - 1; i++)
419 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
420
421 if ((cmd_left == 0) && (i2c->cdata->version >= ID_X1000))
422 jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
423 JZ4780_I2C_DC_READ | X1000_I2C_DC_STOP);
424 else
425 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
426 }
427
428 static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
429 {
430 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
431 complete(&i2c->trans_waitq);
432 }
433
434 static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
435 {
436 unsigned short tmp;
437 unsigned short intst;
438 unsigned short intmsk;
439 struct jz4780_i2c *i2c = dev_id;
440
441 spin_lock(&i2c->lock);
442 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
443 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
444
445 intst &= intmsk;
446
447 if (intst & JZ4780_I2C_INTST_TXABT) {
448 jz4780_i2c_trans_done(i2c);
449 goto done;
450 }
451
452 if (intst & JZ4780_I2C_INTST_RXOF) {
453 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
454 jz4780_i2c_trans_done(i2c);
455 goto done;
456 }
457
458 /*
459 * When reading, always drain RX FIFO before we send more Read
460 * Commands to avoid fifo overrun
461 */
462 if (i2c->is_write == 0) {
463 int rd_left;
464
465 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
466 & JZ4780_I2C_STA_RFNE)) {
467 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
468 & 0xff;
469 i2c->rd_data_xfered++;
470 if (i2c->rd_data_xfered == i2c->rd_total_len) {
471 jz4780_i2c_trans_done(i2c);
472 goto done;
473 }
474 }
475
476 rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
477
478 if (rd_left <= i2c->cdata->fifosize)
479 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
480 }
481
482 if (intst & JZ4780_I2C_INTST_TXEMP) {
483 if (i2c->is_write == 0) {
484 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
485 int max_send = (i2c->cdata->fifosize - 1)
486 - (i2c->rd_cmd_xfered
487 - i2c->rd_data_xfered);
488 int cmd_to_send = min(cmd_left, max_send);
489
490 if (i2c->rd_cmd_xfered != 0)
491 cmd_to_send = min(cmd_to_send,
492 i2c->cdata->fifosize
493 - i2c->cdata->tx_level - 1);
494
495 if (cmd_to_send) {
496 i2c->rd_cmd_xfered += cmd_to_send;
497 cmd_left = i2c->rd_total_len -
498 i2c->rd_cmd_xfered;
499 jz4780_i2c_send_rcmd(i2c,
500 cmd_to_send, cmd_left);
501
502 }
503
504 if (cmd_left == 0) {
505 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
506 intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
507 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
508
509 if (i2c->cdata->version < ID_X1000) {
510 tmp = jz4780_i2c_readw(i2c,
511 JZ4780_I2C_CTRL);
512 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
513 jz4780_i2c_writew(i2c,
514 JZ4780_I2C_CTRL, tmp);
515 }
516 }
517 } else {
518 unsigned short data;
519 unsigned short i2c_sta;
520
521 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
522
523 while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
524 (i2c->wt_len > 0)) {
525 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
526 data = *i2c->wbuf;
527 data &= ~JZ4780_I2C_DC_READ;
528 if ((i2c->wt_len == 1) && (!i2c->stop_hold) &&
529 (i2c->cdata->version >= ID_X1000))
530 data |= X1000_I2C_DC_STOP;
531 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data);
532 i2c->wbuf++;
533 i2c->wt_len--;
534 }
535
536 if (i2c->wt_len == 0) {
537 if ((!i2c->stop_hold) && (i2c->cdata->version <
538 ID_X1000)) {
539 tmp = jz4780_i2c_readw(i2c,
540 JZ4780_I2C_CTRL);
541 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
542 jz4780_i2c_writew(i2c,
543 JZ4780_I2C_CTRL, tmp);
544 }
545
546 jz4780_i2c_trans_done(i2c);
547 goto done;
548 }
549 }
550 }
551
552 done:
553 spin_unlock(&i2c->lock);
554 return IRQ_HANDLED;
555 }
556
557 static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
558 {
559 dev_dbg(&i2c->adap.dev, "txabrt: 0x%08x, cmd: %d, send: %d, recv: %d\n",
560 src, i2c->cmd, i2c->cmd_buf[i2c->cmd], i2c->data_buf[i2c->cmd]);
561 }
562
563 static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
564 unsigned char *buf, int len, int cnt,
565 int idx)
566 {
567 int ret = 0;
568 unsigned long time_left;
569 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
570 unsigned short tmp;
571 unsigned long flags;
572
573 memset(buf, 0, len);
574
575 spin_lock_irqsave(&i2c->lock, flags);
576
577 i2c->stop_hold = 0;
578 i2c->is_write = 0;
579 i2c->rbuf = buf;
580 i2c->rd_total_len = len;
581 i2c->rd_data_xfered = 0;
582 i2c->rd_cmd_xfered = 0;
583
584 if (len <= i2c->cdata->fifosize)
585 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
586 else
587 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, i2c->cdata->rx_level);
588
589 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level);
590
591 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
592 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
593 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
594
595 if (i2c->cdata->version < ID_X1000) {
596 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
597 tmp |= JZ4780_I2C_CTRL_STPHLD;
598 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
599 }
600
601 spin_unlock_irqrestore(&i2c->lock, flags);
602
603 time_left = wait_for_completion_timeout(&i2c->trans_waitq,
604 msecs_to_jiffies(wait_time));
605
606 if (!time_left) {
607 dev_err(&i2c->adap.dev, "irq read timeout\n");
608 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
609 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
610 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
611 i2c->cmd, i2c->data_buf[i2c->cmd]);
612 ret = -EIO;
613 }
614
615 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
616 if (tmp) {
617 jz4780_i2c_txabrt(i2c, tmp);
618 ret = -EIO;
619 }
620
621 return ret;
622 }
623
624 static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
625 unsigned char *buf, int len,
626 int cnt, int idx)
627 {
628 int ret = 0;
629 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
630 unsigned long time_left;
631 unsigned short tmp;
632 unsigned long flags;
633
634 spin_lock_irqsave(&i2c->lock, flags);
635
636 if (idx < (cnt - 1))
637 i2c->stop_hold = 1;
638 else
639 i2c->stop_hold = 0;
640
641 i2c->is_write = 1;
642 i2c->wbuf = buf;
643 i2c->wt_len = len;
644
645 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level);
646
647 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
648 | JZ4780_I2C_INTM_MTXABT);
649
650 if (i2c->cdata->version < ID_X1000) {
651 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
652 tmp |= JZ4780_I2C_CTRL_STPHLD;
653 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
654 }
655
656 spin_unlock_irqrestore(&i2c->lock, flags);
657
658 time_left = wait_for_completion_timeout(&i2c->trans_waitq,
659 msecs_to_jiffies(wait_time));
660 if (time_left && !i2c->stop_hold) {
661 unsigned short i2c_sta;
662 int write_in_process;
663
664 time_left = JZ4780_I2C_TIMEOUT * 100;
665 for (; time_left > 0; time_left--) {
666 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
667
668 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
669 !(i2c_sta & JZ4780_I2C_STA_TFE);
670 if (!write_in_process)
671 break;
672 udelay(10);
673 }
674 }
675
676 if (!time_left) {
677 dev_err(&i2c->adap.dev, "write wait timeout\n");
678 ret = -EIO;
679 }
680
681 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
682 if (tmp) {
683 jz4780_i2c_txabrt(i2c, tmp);
684 ret = -EIO;
685 }
686
687 return ret;
688 }
689
690 static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
691 int count)
692 {
693 int i = -EIO;
694 int ret = 0;
695 struct jz4780_i2c *i2c = adap->algo_data;
696
697 ret = jz4780_i2c_prepare(i2c);
698 if (ret) {
699 dev_err(&i2c->adap.dev, "I2C prepare failed\n");
700 goto out;
701 }
702
703 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
704 ret = jz4780_i2c_set_target(i2c, msg->addr);
705 if (ret)
706 goto out;
707 }
708 for (i = 0; i < count; i++, msg++) {
709 if (msg->flags & I2C_M_RD)
710 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
711 count, i);
712 else
713 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
714 count, i);
715
716 if (ret)
717 goto out;
718 }
719
720 ret = i;
721
722 out:
723 jz4780_i2c_cleanup(i2c);
724 return ret;
725 }
726
727 static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
728 {
729 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
730 }
731
732 static const struct i2c_algorithm jz4780_i2c_algorithm = {
733 .xfer = jz4780_i2c_xfer,
734 .functionality = jz4780_i2c_functionality,
735 };
736
737 static const struct ingenic_i2c_config jz4780_i2c_config = {
738 .version = ID_JZ4780,
739
740 .fifosize = JZ4780_I2C_FIFO_LEN,
741 .tx_level = JZ4780_I2C_FIFO_LEN / 2,
742 .rx_level = JZ4780_I2C_FIFO_LEN / 2 - 1,
743 };
744
745 static const struct ingenic_i2c_config x1000_i2c_config = {
746 .version = ID_X1000,
747
748 .fifosize = X1000_I2C_FIFO_LEN,
749 .tx_level = X1000_I2C_FIFO_LEN / 2,
750 .rx_level = X1000_I2C_FIFO_LEN / 2 - 1,
751 };
752
753 static const struct of_device_id jz4780_i2c_of_matches[] = {
754 { .compatible = "ingenic,jz4770-i2c", .data = &jz4780_i2c_config },
755 { .compatible = "ingenic,jz4780-i2c", .data = &jz4780_i2c_config },
756 { .compatible = "ingenic,x1000-i2c", .data = &x1000_i2c_config },
757 { /* sentinel */ }
758 };
759 MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches);
760
761 static int jz4780_i2c_probe(struct platform_device *pdev)
762 {
763 int ret = 0;
764 unsigned int clk_freq = 0;
765 unsigned short tmp;
766 struct jz4780_i2c *i2c;
767
768 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
769 if (!i2c)
770 return -ENOMEM;
771
772 i2c->cdata = device_get_match_data(&pdev->dev);
773 if (!i2c->cdata) {
774 dev_err(&pdev->dev, "Error: No device match found\n");
775 return -ENODEV;
776 }
777
778 i2c->adap.owner = THIS_MODULE;
779 i2c->adap.algo = &jz4780_i2c_algorithm;
780 i2c->adap.algo_data = i2c;
781 i2c->adap.retries = 5;
782 i2c->adap.dev.parent = &pdev->dev;
783 i2c->adap.dev.of_node = pdev->dev.of_node;
784 sprintf(i2c->adap.name, "%s", pdev->name);
785
786 init_completion(&i2c->trans_waitq);
787 spin_lock_init(&i2c->lock);
788
789 i2c->iomem = devm_platform_ioremap_resource(pdev, 0);
790 if (IS_ERR(i2c->iomem))
791 return PTR_ERR(i2c->iomem);
792
793 platform_set_drvdata(pdev, i2c);
794
795 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL);
796 if (IS_ERR(i2c->clk))
797 return PTR_ERR(i2c->clk);
798
799 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
800 &clk_freq);
801 if (ret) {
802 dev_err(&pdev->dev, "clock-frequency not specified in DT\n");
803 return ret;
804 }
805
806 i2c->speed = clk_freq / 1000;
807 if (i2c->speed == 0) {
808 ret = -EINVAL;
809 dev_err(&pdev->dev, "clock-frequency minimum is 1000\n");
810 return ret;
811 }
812 jz4780_i2c_set_speed(i2c);
813
814 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
815
816 if (i2c->cdata->version < ID_X1000) {
817 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
818 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
819 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
820 }
821
822 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
823
824 ret = platform_get_irq(pdev, 0);
825 if (ret < 0)
826 return ret;
827 i2c->irq = ret;
828
829 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
830 dev_name(&pdev->dev), i2c);
831 if (ret)
832 return ret;
833
834 ret = i2c_add_adapter(&i2c->adap);
835 if (ret < 0)
836 return ret;
837
838 return 0;
839 }
840
841 static void jz4780_i2c_remove(struct platform_device *pdev)
842 {
843 struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
844
845 i2c_del_adapter(&i2c->adap);
846 }
847
848 static struct platform_driver jz4780_i2c_driver = {
849 .probe = jz4780_i2c_probe,
850 .remove = jz4780_i2c_remove,
851 .driver = {
852 .name = "jz4780-i2c",
853 .of_match_table = jz4780_i2c_of_matches,
854 },
855 };
856
857 module_platform_driver(jz4780_i2c_driver);
858
859 MODULE_LICENSE("GPL");
860 MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
861 MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");
Kernel DRM miscellaneous fixes and cross-tree changes