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drm/modes: Fix drm_mode_vrefres() docs
[drm/drm-misc.git] / drivers / i2c / busses / i2c-rcar.c
bloba7b77d14ee8671eb2b0b2a9caf606fd04d95ba0a
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Renesas R-Car I2C unit
4 *
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
7 *
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 *
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 */
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/i2c.h>
24 #include <linux/i2c-smbus.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32
33 /* register offsets */
34 #define ICSCR 0x00 /* slave ctrl */
35 #define ICMCR 0x04 /* master ctrl */
36 #define ICSSR 0x08 /* slave status */
37 #define ICMSR 0x0C /* master status */
38 #define ICSIER 0x10 /* slave irq enable */
39 #define ICMIER 0x14 /* master irq enable */
40 #define ICCCR 0x18 /* clock dividers */
41 #define ICSAR 0x1C /* slave address */
42 #define ICMAR 0x20 /* master address */
43 #define ICRXTX 0x24 /* data port */
44 #define ICCCR2 0x28 /* Clock control 2 */
45 #define ICMPR 0x2C /* SCL mask control */
46 #define ICHPR 0x30 /* SCL HIGH control */
47 #define ICLPR 0x34 /* SCL LOW control */
48 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
49 #define ICDMAER 0x3c /* DMA enable (Gen3) */
50
51 /* ICSCR */
52 #define SDBS BIT(3) /* slave data buffer select */
53 #define SIE BIT(2) /* slave interface enable */
54 #define GCAE BIT(1) /* general call address enable */
55 #define FNA BIT(0) /* forced non acknowledgment */
56
57 /* ICMCR */
58 #define MDBS BIT(7) /* non-fifo mode switch */
59 #define FSCL BIT(6) /* override SCL pin */
60 #define FSDA BIT(5) /* override SDA pin */
61 #define OBPC BIT(4) /* override pins */
62 #define MIE BIT(3) /* master if enable */
63 #define TSBE BIT(2)
64 #define FSB BIT(1) /* force stop bit */
65 #define ESG BIT(0) /* enable start bit gen */
66
67 /* ICSSR (also for ICSIER) */
68 #define GCAR BIT(6) /* general call received */
69 #define STM BIT(5) /* slave transmit mode */
70 #define SSR BIT(4) /* stop received */
71 #define SDE BIT(3) /* slave data empty */
72 #define SDT BIT(2) /* slave data transmitted */
73 #define SDR BIT(1) /* slave data received */
74 #define SAR BIT(0) /* slave addr received */
75
76 /* ICMSR (also for ICMIE) */
77 #define MNR BIT(6) /* nack received */
78 #define MAL BIT(5) /* arbitration lost */
79 #define MST BIT(4) /* sent a stop */
80 #define MDE BIT(3)
81 #define MDT BIT(2)
82 #define MDR BIT(1)
83 #define MAT BIT(0) /* slave addr xfer done */
84
85 /* ICDMAER */
86 #define RSDMAE BIT(3) /* DMA Slave Received Enable */
87 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */
88 #define RMDMAE BIT(1) /* DMA Master Received Enable */
89 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */
90
91 /* ICCCR2 */
92 #define FMPE BIT(7) /* Fast Mode Plus Enable */
93 #define CDFD BIT(2) /* CDF Disable */
94 #define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */
95 #define SME BIT(0) /* SCL Mask Enable */
96
97 /* ICFBSCR */
98 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
99
100 #define RCAR_MIN_DMA_LEN 8
101
102 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */
103 #define RCAR_SCLD_RATIO 5
104 #define RCAR_SCHD_RATIO 4
105 /*
106 * SMD should be smaller than SCLD/SCHD and is always around 20 in the docs.
107 * Thus, we simply use 20 which works for low and high speeds.
108 */
109 #define RCAR_DEFAULT_SMD 20
110
111 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
112 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
113 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
114
115 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
116 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
117 #define RCAR_IRQ_STOP (MST)
118
119 #define ID_LAST_MSG BIT(0)
120 #define ID_REP_AFTER_RD BIT(1)
121 #define ID_DONE BIT(2)
122 #define ID_ARBLOST BIT(3)
123 #define ID_NACK BIT(4)
124 #define ID_EPROTO BIT(5)
125 /* persistent flags */
126 #define ID_P_FMPLUS BIT(27)
127 #define ID_P_NOT_ATOMIC BIT(28)
128 #define ID_P_HOST_NOTIFY BIT(29)
129 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */
130 #define ID_P_PM_BLOCKED BIT(31)
131 #define ID_P_MASK GENMASK(31, 27)
132
133 enum rcar_i2c_type {
134 I2C_RCAR_GEN1,
135 I2C_RCAR_GEN2,
136 I2C_RCAR_GEN3,
137 I2C_RCAR_GEN4,
138 };
139
140 struct rcar_i2c_priv {
141 u32 flags;
142 void __iomem *io;
143 struct i2c_adapter adap;
144 struct i2c_msg *msg;
145 int msgs_left;
146 struct clk *clk;
147
148 wait_queue_head_t wait;
149
150 int pos;
151 u32 icccr;
152 u16 schd;
153 u16 scld;
154 u8 smd;
155 u8 recovery_icmcr; /* protected by adapter lock */
156 enum rcar_i2c_type devtype;
157 struct i2c_client *slave;
158
159 struct resource *res;
160 struct dma_chan *dma_tx;
161 struct dma_chan *dma_rx;
162 struct scatterlist sg;
163 enum dma_data_direction dma_direction;
164
165 struct reset_control *rstc;
166 int irq;
167
168 struct i2c_client *host_notify_client;
169 };
170
171 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
172 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
173
174 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
175 {
176 writel(val, priv->io + reg);
177 }
178
179 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
180 {
181 return readl(priv->io + reg);
182 }
183
184 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val)
185 {
186 writel(~val & 0x7f, priv->io + ICMSR);
187 }
188
189 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
190 {
191 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
192
193 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
194 }
195
196 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
197 {
198 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
199
200 if (val)
201 priv->recovery_icmcr |= FSCL;
202 else
203 priv->recovery_icmcr &= ~FSCL;
204
205 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
206 }
207
208 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
209 {
210 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
211
212 if (val)
213 priv->recovery_icmcr |= FSDA;
214 else
215 priv->recovery_icmcr &= ~FSDA;
216
217 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
218 }
219
220 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
221 {
222 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
223
224 return !(rcar_i2c_read(priv, ICMCR) & FSDA);
225 }
226
227 static struct i2c_bus_recovery_info rcar_i2c_bri = {
228 .get_scl = rcar_i2c_get_scl,
229 .set_scl = rcar_i2c_set_scl,
230 .set_sda = rcar_i2c_set_sda,
231 .get_bus_free = rcar_i2c_get_bus_free,
232 .recover_bus = i2c_generic_scl_recovery,
233 };
234
235 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
236 {
237 /* reset master mode */
238 rcar_i2c_write(priv, ICMIER, 0);
239 rcar_i2c_write(priv, ICMCR, MDBS);
240 rcar_i2c_write(priv, ICMSR, 0);
241 /* start clock */
242 if (priv->devtype < I2C_RCAR_GEN3) {
243 rcar_i2c_write(priv, ICCCR, priv->icccr);
244 } else {
245 u32 icccr2 = CDFD | HLSE | SME;
246
247 if (priv->flags & ID_P_FMPLUS)
248 icccr2 |= FMPE;
249
250 rcar_i2c_write(priv, ICCCR2, icccr2);
251 rcar_i2c_write(priv, ICCCR, priv->icccr);
252 rcar_i2c_write(priv, ICMPR, priv->smd);
253 rcar_i2c_write(priv, ICHPR, priv->schd);
254 rcar_i2c_write(priv, ICLPR, priv->scld);
255 rcar_i2c_write(priv, ICFBSCR, TCYC17);
256 }
257 }
258
259 static void rcar_i2c_reset_slave(struct rcar_i2c_priv *priv)
260 {
261 rcar_i2c_write(priv, ICSIER, 0);
262 rcar_i2c_write(priv, ICSSR, 0);
263 rcar_i2c_write(priv, ICSCR, SDBS);
264 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
265 }
266
267 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
268 {
269 int ret;
270 u32 val;
271
272 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
273 priv->adap.timeout);
274 if (ret) {
275 /* Waiting did not help, try to recover */
276 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
277 ret = i2c_recover_bus(&priv->adap);
278 }
279
280 return ret;
281 }
282
283 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
284 {
285 u32 cdf, round, ick, sum, scl, cdf_width;
286 unsigned long rate;
287 struct device *dev = rcar_i2c_priv_to_dev(priv);
288 struct i2c_timings t = {
289 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ,
290 .scl_fall_ns = 35,
291 .scl_rise_ns = 200,
292 .scl_int_delay_ns = 50,
293 };
294
295 /* Fall back to previously used values if not supplied */
296 i2c_parse_fw_timings(dev, &t, false);
297 priv->smd = RCAR_DEFAULT_SMD;
298
299 /*
300 * calculate SCL clock
301 * see
302 * ICCCR (and ICCCR2 for Gen3+)
303 *
304 * ick = clkp / (1 + CDF)
305 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
306 *
307 * for Gen3+:
308 * SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp])
309 *
310 * ick : I2C internal clock < 20 MHz
311 * ticf : I2C SCL falling time
312 * tr : I2C SCL rising time
313 * intd : LSI internal delay
314 * clkp : peripheral_clk
315 * F[] : integer up-valuation
316 */
317 rate = clk_get_rate(priv->clk);
318 cdf = rate / 20000000;
319 cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3;
320 if (cdf >= 1U << cdf_width)
321 goto err_no_val;
322
323 if (t.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ && priv->devtype >= I2C_RCAR_GEN4)
324 priv->flags |= ID_P_FMPLUS;
325 else
326 priv->flags &= ~ID_P_FMPLUS;
327
328 /* On Gen3+, we use cdf only for the filters, not as a SCL divider */
329 ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1);
330
331 /*
332 * It is impossible to calculate a large scale number on u32. Separate it.
333 *
334 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
335 * = F[sum * ick / 1000000000]
336 * = F[(ick / 1000000) * sum / 1000]
337 */
338 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
339 round = DIV_ROUND_CLOSEST(ick, 1000000);
340 round = DIV_ROUND_CLOSEST(round * sum, 1000);
341
342 if (priv->devtype < I2C_RCAR_GEN3) {
343 u32 scgd;
344 /*
345 * SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick])
346 * 20 + 8 * SCGD + F[...] = ick / SCL
347 * SCGD = ((ick / SCL) - 20 - F[...]) / 8
348 * Result (= SCL) should be less than bus_speed for hardware safety
349 */
350 scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1);
351 scgd = DIV_ROUND_UP(scgd - 20 - round, 8);
352 scl = ick / (20 + 8 * scgd + round);
353
354 if (scgd > 0x3f)
355 goto err_no_val;
356
357 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n",
358 scl, t.bus_freq_hz, rate, round, cdf, scgd);
359
360 priv->icccr = scgd << cdf_width | cdf;
361 } else {
362 u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO;
363 /*
364 * SCLD/SCHD ratio and SMD default value are explained above
365 * where they are defined. With these definitions, we can compute
366 * x as a base value for the SCLD/SCHD ratio:
367 *
368 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp])
369 * SCL = clkp / (8 + 2 * SMD + RCAR_SCLD_RATIO * x
370 * + RCAR_SCHD_RATIO * x + F[...])
371 *
372 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO
373 *
374 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...])
375 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL
376 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio
377 */
378 x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1);
379 x = DIV_ROUND_UP(x - 8 - 2 * priv->smd - round, sum_ratio);
380 scl = rate / (8 + 2 * priv->smd + sum_ratio * x + round);
381
382 if (x == 0 || x * RCAR_SCLD_RATIO > 0xffff)
383 goto err_no_val;
384
385 priv->icccr = cdf;
386 priv->schd = RCAR_SCHD_RATIO * x;
387 priv->scld = RCAR_SCLD_RATIO * x;
388 if (priv->smd >= priv->schd)
389 priv->smd = priv->schd - 1;
390
391 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u SMD %u\n",
392 scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld, priv->smd);
393 }
394
395 return 0;
396
397 err_no_val:
398 dev_err(dev, "it is impossible to calculate best SCL\n");
399 return -EINVAL;
400 }
401
402 /*
403 * We don't have a test case but the HW engineers say that the write order of
404 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR
405 * handling is outside of this function. First messages clear ICMSR before this
406 * function, interrupt handlers clear the relevant bits after this function.
407 */
408 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
409 {
410 int read = !!rcar_i2c_is_recv(priv);
411 bool rep_start = !(priv->flags & ID_REP_AFTER_RD);
412
413 priv->pos = 0;
414 priv->flags &= ID_P_MASK;
415
416 if (priv->msgs_left == 1)
417 priv->flags |= ID_LAST_MSG;
418
419 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
420 if (priv->flags & ID_P_NOT_ATOMIC)
421 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
422
423 if (rep_start)
424 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
425 }
426
427 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv,
428 struct i2c_msg *msgs, int num)
429 {
430 priv->msg = msgs;
431 priv->msgs_left = num;
432 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */
433 rcar_i2c_prepare_msg(priv);
434 }
435
436 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
437 {
438 priv->msg++;
439 priv->msgs_left--;
440 rcar_i2c_prepare_msg(priv);
441 /* ICMSR handling must come afterwards in the irq handler */
442 }
443
444 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)
445 {
446 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
447 ? priv->dma_rx : priv->dma_tx;
448
449 /* only allowed from thread context! */
450 if (terminate)
451 dmaengine_terminate_sync(chan);
452
453 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
454 sg_dma_len(&priv->sg), priv->dma_direction);
455
456 /* Gen3+ can only do one RXDMA per transfer and we just completed it */
457 if (priv->devtype >= I2C_RCAR_GEN3 &&
458 priv->dma_direction == DMA_FROM_DEVICE)
459 priv->flags |= ID_P_NO_RXDMA;
460
461 priv->dma_direction = DMA_NONE;
462
463 /* Disable DMA Master Received/Transmitted, must be last! */
464 rcar_i2c_write(priv, ICDMAER, 0);
465 }
466
467 static void rcar_i2c_dma_callback(void *data)
468 {
469 struct rcar_i2c_priv *priv = data;
470
471 priv->pos += sg_dma_len(&priv->sg);
472
473 rcar_i2c_cleanup_dma(priv, false);
474 }
475
476 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
477 {
478 struct device *dev = rcar_i2c_priv_to_dev(priv);
479 struct i2c_msg *msg = priv->msg;
480 bool read = msg->flags & I2C_M_RD;
481 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
482 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
483 struct dma_async_tx_descriptor *txdesc;
484 dma_addr_t dma_addr;
485 dma_cookie_t cookie;
486 unsigned char *buf;
487 int len;
488
489 /* Do various checks to see if DMA is feasible at all */
490 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
491 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
492 return false;
493
494 if (read) {
495 /*
496 * The last two bytes needs to be fetched using PIO in
497 * order for the STOP phase to work.
498 */
499 buf = priv->msg->buf;
500 len = priv->msg->len - 2;
501 } else {
502 /*
503 * First byte in message was sent using PIO.
504 */
505 buf = priv->msg->buf + 1;
506 len = priv->msg->len - 1;
507 }
508
509 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
510 if (dma_mapping_error(chan->device->dev, dma_addr)) {
511 dev_dbg(dev, "dma map failed, using PIO\n");
512 return false;
513 }
514
515 sg_dma_len(&priv->sg) = len;
516 sg_dma_address(&priv->sg) = dma_addr;
517
518 priv->dma_direction = dir;
519
520 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
521 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
522 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
523 if (!txdesc) {
524 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
525 rcar_i2c_cleanup_dma(priv, false);
526 return false;
527 }
528
529 txdesc->callback = rcar_i2c_dma_callback;
530 txdesc->callback_param = priv;
531
532 cookie = dmaengine_submit(txdesc);
533 if (dma_submit_error(cookie)) {
534 dev_dbg(dev, "submitting dma failed, using PIO\n");
535 rcar_i2c_cleanup_dma(priv, false);
536 return false;
537 }
538
539 /* Enable DMA Master Received/Transmitted */
540 if (read)
541 rcar_i2c_write(priv, ICDMAER, RMDMAE);
542 else
543 rcar_i2c_write(priv, ICDMAER, TMDMAE);
544
545 dma_async_issue_pending(chan);
546 return true;
547 }
548
549 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
550 {
551 struct i2c_msg *msg = priv->msg;
552 u32 irqs_to_clear = MDE;
553
554 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
555 if (WARN(!(msr & MDE), "spurious irq"))
556 return;
557
558 if (msr & MAT)
559 irqs_to_clear |= MAT;
560
561 /* Check if DMA can be enabled and take over */
562 if (priv->pos == 1 && rcar_i2c_dma(priv))
563 return;
564
565 if (priv->pos < msg->len) {
566 /*
567 * Prepare next data to ICRXTX register.
568 * This data will go to _SHIFT_ register.
569 *
570 * *
571 * [ICRXTX] -> [SHIFT] -> [I2C bus]
572 */
573 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
574 priv->pos++;
575 } else {
576 /*
577 * The last data was pushed to ICRXTX on _PREV_ empty irq.
578 * It is on _SHIFT_ register, and will sent to I2C bus.
579 *
580 * *
581 * [ICRXTX] -> [SHIFT] -> [I2C bus]
582 */
583
584 if (priv->flags & ID_LAST_MSG)
585 /*
586 * If current msg is the _LAST_ msg,
587 * prepare stop condition here.
588 * ID_DONE will be set on STOP irq.
589 */
590 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
591 else
592 rcar_i2c_next_msg(priv);
593 }
594
595 rcar_i2c_clear_irq(priv, irqs_to_clear);
596 }
597
598 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
599 {
600 struct i2c_msg *msg = priv->msg;
601 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN;
602 u32 irqs_to_clear = MDR;
603
604 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
605 if (!(msr & MDR))
606 return;
607
608 if (msr & MAT) {
609 irqs_to_clear |= MAT;
610 /*
611 * Address transfer phase finished, but no data at this point.
612 * Try to use DMA to receive data.
613 */
614 rcar_i2c_dma(priv);
615 } else if (priv->pos < msg->len) {
616 /* get received data */
617 u8 data = rcar_i2c_read(priv, ICRXTX);
618
619 msg->buf[priv->pos] = data;
620 if (recv_len_init) {
621 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) {
622 priv->flags |= ID_DONE | ID_EPROTO;
623 return;
624 }
625 msg->len += msg->buf[0];
626 /* Enough data for DMA? */
627 if (rcar_i2c_dma(priv))
628 return;
629 /* new length after RECV_LEN now properly initialized */
630 recv_len_init = false;
631 }
632 priv->pos++;
633 }
634
635 /*
636 * If next received data is the _LAST_ and we are not waiting for a new
637 * length because of RECV_LEN, then go to a new phase.
638 */
639 if (priv->pos + 1 == msg->len && !recv_len_init) {
640 if (priv->flags & ID_LAST_MSG) {
641 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
642 } else {
643 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
644 priv->flags |= ID_REP_AFTER_RD;
645 }
646 }
647
648 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
649 rcar_i2c_next_msg(priv);
650
651 rcar_i2c_clear_irq(priv, irqs_to_clear);
652 }
653
654 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
655 {
656 u32 ssr_raw, ssr_filtered;
657 u8 value;
658
659 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
660 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
661
662 if (!ssr_filtered)
663 return false;
664
665 /* address detected */
666 if (ssr_filtered & SAR) {
667 /* read or write request */
668 if (ssr_raw & STM) {
669 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
670 rcar_i2c_write(priv, ICRXTX, value);
671 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
672 } else {
673 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
674 rcar_i2c_read(priv, ICRXTX); /* dummy read */
675 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
676 }
677
678 /* Clear SSR, too, because of old STOPs to other clients than us */
679 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
680 }
681
682 /* master sent stop */
683 if (ssr_filtered & SSR) {
684 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
685 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
686 rcar_i2c_write(priv, ICSIER, SAR);
687 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
688 }
689
690 /* master wants to write to us */
691 if (ssr_filtered & SDR) {
692 int ret;
693
694 value = rcar_i2c_read(priv, ICRXTX);
695 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
696 /* Send NACK in case of error */
697 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
698 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
699 }
700
701 /* master wants to read from us */
702 if (ssr_filtered & SDE) {
703 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
704 rcar_i2c_write(priv, ICRXTX, value);
705 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
706 }
707
708 return true;
709 }
710
711 /*
712 * This driver has a lock-free design because there are IP cores (at least
713 * R-Car Gen2) which have an inherent race condition in their hardware design.
714 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
715 * the interrupt was generated, otherwise an unwanted repeated message gets
716 * generated. It turned out that taking a spinlock at the beginning of the ISR
717 * was already causing repeated messages. Thus, this driver was converted to
718 * the now lockless behaviour. Please keep this in mind when hacking the driver.
719 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
720 * likely affected. Therefore, we have different interrupt handler entries.
721 */
722 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
723 {
724 if (!msr) {
725 if (rcar_i2c_slave_irq(priv))
726 return IRQ_HANDLED;
727
728 return IRQ_NONE;
729 }
730
731 /* Arbitration lost */
732 if (msr & MAL) {
733 priv->flags |= ID_DONE | ID_ARBLOST;
734 goto out;
735 }
736
737 /* Nack */
738 if (msr & MNR) {
739 /* HW automatically sends STOP after received NACK */
740 if (priv->flags & ID_P_NOT_ATOMIC)
741 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
742 priv->flags |= ID_NACK;
743 goto out;
744 }
745
746 /* Stop */
747 if (msr & MST) {
748 priv->msgs_left--; /* The last message also made it */
749 priv->flags |= ID_DONE;
750 goto out;
751 }
752
753 if (rcar_i2c_is_recv(priv))
754 rcar_i2c_irq_recv(priv, msr);
755 else
756 rcar_i2c_irq_send(priv, msr);
757
758 out:
759 if (priv->flags & ID_DONE) {
760 rcar_i2c_write(priv, ICMIER, 0);
761 rcar_i2c_write(priv, ICMSR, 0);
762 if (priv->flags & ID_P_NOT_ATOMIC)
763 wake_up(&priv->wait);
764 }
765
766 return IRQ_HANDLED;
767 }
768
769 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
770 {
771 struct rcar_i2c_priv *priv = ptr;
772 u32 msr;
773
774 /* Clear START or STOP immediately, except for REPSTART after read */
775 if (likely(!(priv->flags & ID_REP_AFTER_RD)))
776 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
777
778 /* Only handle interrupts that are currently enabled */
779 msr = rcar_i2c_read(priv, ICMSR);
780 if (priv->flags & ID_P_NOT_ATOMIC)
781 msr &= rcar_i2c_read(priv, ICMIER);
782
783 return rcar_i2c_irq(irq, priv, msr);
784 }
785
786 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
787 {
788 struct rcar_i2c_priv *priv = ptr;
789 u32 msr;
790
791 /* Only handle interrupts that are currently enabled */
792 msr = rcar_i2c_read(priv, ICMSR);
793 if (priv->flags & ID_P_NOT_ATOMIC)
794 msr &= rcar_i2c_read(priv, ICMIER);
795
796 /*
797 * Clear START or STOP immediately, except for REPSTART after read or
798 * if a spurious interrupt was detected.
799 */
800 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr))
801 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
802
803 return rcar_i2c_irq(irq, priv, msr);
804 }
805
806 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
807 enum dma_transfer_direction dir,
808 dma_addr_t port_addr)
809 {
810 struct dma_chan *chan;
811 struct dma_slave_config cfg;
812 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
813 int ret;
814
815 chan = dma_request_chan(dev, chan_name);
816 if (IS_ERR(chan)) {
817 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
818 chan_name, PTR_ERR(chan));
819 return chan;
820 }
821
822 memset(&cfg, 0, sizeof(cfg));
823 cfg.direction = dir;
824 if (dir == DMA_MEM_TO_DEV) {
825 cfg.dst_addr = port_addr;
826 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
827 } else {
828 cfg.src_addr = port_addr;
829 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
830 }
831
832 ret = dmaengine_slave_config(chan, &cfg);
833 if (ret) {
834 dev_dbg(dev, "slave_config failed for %s (%d)\n",
835 chan_name, ret);
836 dma_release_channel(chan);
837 return ERR_PTR(ret);
838 }
839
840 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
841 return chan;
842 }
843
844 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
845 struct i2c_msg *msg)
846 {
847 struct device *dev = rcar_i2c_priv_to_dev(priv);
848 bool read;
849 struct dma_chan *chan;
850 enum dma_transfer_direction dir;
851
852 read = msg->flags & I2C_M_RD;
853
854 chan = read ? priv->dma_rx : priv->dma_tx;
855 if (PTR_ERR(chan) != -EPROBE_DEFER)
856 return;
857
858 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
859 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
860
861 if (read)
862 priv->dma_rx = chan;
863 else
864 priv->dma_tx = chan;
865 }
866
867 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
868 {
869 if (!IS_ERR(priv->dma_tx)) {
870 dma_release_channel(priv->dma_tx);
871 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
872 }
873
874 if (!IS_ERR(priv->dma_rx)) {
875 dma_release_channel(priv->dma_rx);
876 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
877 }
878 }
879
880 /* I2C is a special case, we need to poll the status of a reset */
881 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
882 {
883 int ret;
884
885 /* Don't reset if a slave instance is currently running */
886 if (priv->slave)
887 return -EISCONN;
888
889 ret = reset_control_reset(priv->rstc);
890 if (ret)
891 return ret;
892
893 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
894 100, false, priv->rstc);
895 }
896
897 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
898 struct i2c_msg *msgs,
899 int num)
900 {
901 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
902 struct device *dev = rcar_i2c_priv_to_dev(priv);
903 int i, ret;
904 long time_left;
905
906 priv->flags |= ID_P_NOT_ATOMIC;
907
908 pm_runtime_get_sync(dev);
909
910 /* Check bus state before init otherwise bus busy info will be lost */
911 ret = rcar_i2c_bus_barrier(priv);
912 if (ret < 0)
913 goto out;
914
915 /* Gen3+ needs a reset. That also allows RXDMA once */
916 if (priv->devtype >= I2C_RCAR_GEN3) {
917 ret = rcar_i2c_do_reset(priv);
918 if (ret)
919 goto out;
920 priv->flags &= ~ID_P_NO_RXDMA;
921 }
922
923 rcar_i2c_init(priv);
924
925 for (i = 0; i < num; i++)
926 rcar_i2c_request_dma(priv, msgs + i);
927
928 rcar_i2c_first_msg(priv, msgs, num);
929
930 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
931 num * adap->timeout);
932
933 /* cleanup DMA if it couldn't complete properly due to an error */
934 if (priv->dma_direction != DMA_NONE)
935 rcar_i2c_cleanup_dma(priv, true);
936
937 if (!time_left) {
938 rcar_i2c_init(priv);
939 ret = -ETIMEDOUT;
940 } else if (priv->flags & ID_NACK) {
941 ret = -ENXIO;
942 } else if (priv->flags & ID_ARBLOST) {
943 ret = -EAGAIN;
944 } else if (priv->flags & ID_EPROTO) {
945 ret = -EPROTO;
946 } else {
947 ret = num - priv->msgs_left; /* The number of transfer */
948 }
949 out:
950 pm_runtime_put(dev);
951
952 if (ret < 0 && ret != -ENXIO)
953 dev_err(dev, "error %d : %x\n", ret, priv->flags);
954
955 return ret;
956 }
957
958 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap,
959 struct i2c_msg *msgs,
960 int num)
961 {
962 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
963 struct device *dev = rcar_i2c_priv_to_dev(priv);
964 unsigned long j;
965 bool time_left;
966 int ret;
967
968 priv->flags &= ~ID_P_NOT_ATOMIC;
969
970 pm_runtime_get_sync(dev);
971
972 /* Check bus state before init otherwise bus busy info will be lost */
973 ret = rcar_i2c_bus_barrier(priv);
974 if (ret < 0)
975 goto out;
976
977 rcar_i2c_init(priv);
978 rcar_i2c_first_msg(priv, msgs, num);
979
980 j = jiffies + num * adap->timeout;
981 do {
982 u32 msr = rcar_i2c_read(priv, ICMSR);
983
984 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP;
985
986 if (msr) {
987 if (priv->devtype < I2C_RCAR_GEN3)
988 rcar_i2c_gen2_irq(0, priv);
989 else
990 rcar_i2c_gen3_irq(0, priv);
991 }
992
993 time_left = time_before_eq(jiffies, j);
994 } while (!(priv->flags & ID_DONE) && time_left);
995
996 if (!time_left) {
997 rcar_i2c_init(priv);
998 ret = -ETIMEDOUT;
999 } else if (priv->flags & ID_NACK) {
1000 ret = -ENXIO;
1001 } else if (priv->flags & ID_ARBLOST) {
1002 ret = -EAGAIN;
1003 } else if (priv->flags & ID_EPROTO) {
1004 ret = -EPROTO;
1005 } else {
1006 ret = num - priv->msgs_left; /* The number of transfer */
1007 }
1008 out:
1009 pm_runtime_put(dev);
1010
1011 if (ret < 0 && ret != -ENXIO)
1012 dev_err(dev, "error %d : %x\n", ret, priv->flags);
1013
1014 return ret;
1015 }
1016
1017 static int rcar_reg_slave(struct i2c_client *slave)
1018 {
1019 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
1020
1021 if (priv->slave)
1022 return -EBUSY;
1023
1024 if (slave->flags & I2C_CLIENT_TEN)
1025 return -EAFNOSUPPORT;
1026
1027 /* Keep device active for slave address detection logic */
1028 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
1029
1030 priv->slave = slave;
1031 rcar_i2c_write(priv, ICSAR, slave->addr);
1032 rcar_i2c_write(priv, ICSSR, 0);
1033 rcar_i2c_write(priv, ICSIER, SAR);
1034 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
1035
1036 return 0;
1037 }
1038
1039 static int rcar_unreg_slave(struct i2c_client *slave)
1040 {
1041 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
1042
1043 WARN_ON(!priv->slave);
1044
1045 /* ensure no irq is running before clearing ptr */
1046 disable_irq(priv->irq);
1047 rcar_i2c_reset_slave(priv);
1048 enable_irq(priv->irq);
1049
1050 priv->slave = NULL;
1051
1052 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
1053
1054 return 0;
1055 }
1056
1057 static u32 rcar_i2c_func(struct i2c_adapter *adap)
1058 {
1059 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
1060
1061 /*
1062 * This HW can't do:
1063 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
1064 * I2C_M_NOSTART (automatically sends address after START)
1065 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
1066 */
1067 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
1068 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1069
1070 if (priv->flags & ID_P_HOST_NOTIFY)
1071 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
1072
1073 return func;
1074 }
1075
1076 static const struct i2c_algorithm rcar_i2c_algo = {
1077 .master_xfer = rcar_i2c_master_xfer,
1078 .master_xfer_atomic = rcar_i2c_master_xfer_atomic,
1079 .functionality = rcar_i2c_func,
1080 .reg_slave = rcar_reg_slave,
1081 .unreg_slave = rcar_unreg_slave,
1082 };
1083
1084 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
1085 .flags = I2C_AQ_NO_ZERO_LEN,
1086 };
1087
1088 static const struct of_device_id rcar_i2c_dt_ids[] = {
1089 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
1090 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
1091 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
1092 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
1093 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
1094 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
1095 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
1096 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
1097 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
1098 /* S4 has no FM+ bit */
1099 { .compatible = "renesas,i2c-r8a779f0", .data = (void *)I2C_RCAR_GEN3 },
1100 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
1101 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
1102 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
1103 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 },
1104 {},
1105 };
1106 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
1107
1108 static int rcar_i2c_probe(struct platform_device *pdev)
1109 {
1110 struct rcar_i2c_priv *priv;
1111 struct i2c_adapter *adap;
1112 struct device *dev = &pdev->dev;
1113 unsigned long irqflags = 0;
1114 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
1115 int ret;
1116
1117 /* Otherwise logic will break because some bytes must always use PIO */
1118 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
1119
1120 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
1121 if (!priv)
1122 return -ENOMEM;
1123
1124 priv->clk = devm_clk_get(dev, NULL);
1125 if (IS_ERR(priv->clk)) {
1126 dev_err(dev, "cannot get clock\n");
1127 return PTR_ERR(priv->clk);
1128 }
1129
1130 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
1131 if (IS_ERR(priv->io))
1132 return PTR_ERR(priv->io);
1133
1134 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
1135 init_waitqueue_head(&priv->wait);
1136
1137 adap = &priv->adap;
1138 adap->nr = pdev->id;
1139 adap->algo = &rcar_i2c_algo;
1140 adap->class = I2C_CLASS_DEPRECATED;
1141 adap->retries = 3;
1142 adap->dev.parent = dev;
1143 adap->dev.of_node = dev->of_node;
1144 adap->bus_recovery_info = &rcar_i2c_bri;
1145 adap->quirks = &rcar_i2c_quirks;
1146 i2c_set_adapdata(adap, priv);
1147 strscpy(adap->name, pdev->name, sizeof(adap->name));
1148
1149 /* Init DMA */
1150 sg_init_table(&priv->sg, 1);
1151 priv->dma_direction = DMA_NONE;
1152 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
1153
1154 /* Activate device for clock calculation */
1155 pm_runtime_enable(dev);
1156 pm_runtime_get_sync(dev);
1157 ret = rcar_i2c_clock_calculate(priv);
1158 if (ret < 0) {
1159 pm_runtime_put(dev);
1160 goto out_pm_disable;
1161 }
1162
1163 /* Bring hardware to known state */
1164 rcar_i2c_init(priv);
1165 rcar_i2c_reset_slave(priv);
1166
1167 /* Stay always active when multi-master to keep arbitration working */
1168 if (of_property_read_bool(dev->of_node, "multi-master"))
1169 priv->flags |= ID_P_PM_BLOCKED;
1170 else
1171 pm_runtime_put(dev);
1172
1173 if (of_property_read_bool(dev->of_node, "smbus"))
1174 priv->flags |= ID_P_HOST_NOTIFY;
1175
1176 if (priv->devtype < I2C_RCAR_GEN3) {
1177 irqflags |= IRQF_NO_THREAD;
1178 irqhandler = rcar_i2c_gen2_irq;
1179 } else {
1180 /* R-Car Gen3+ needs a reset before every transfer */
1181 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1182 if (IS_ERR(priv->rstc)) {
1183 ret = PTR_ERR(priv->rstc);
1184 goto out_pm_put;
1185 }
1186
1187 ret = reset_control_status(priv->rstc);
1188 if (ret < 0)
1189 goto out_pm_put;
1190
1191 /* hard reset disturbs HostNotify local target, so disable it */
1192 priv->flags &= ~ID_P_HOST_NOTIFY;
1193 }
1194
1195 ret = platform_get_irq(pdev, 0);
1196 if (ret < 0)
1197 goto out_pm_put;
1198 priv->irq = ret;
1199 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
1200 if (ret < 0) {
1201 dev_err(dev, "cannot get irq %d\n", priv->irq);
1202 goto out_pm_put;
1203 }
1204
1205 platform_set_drvdata(pdev, priv);
1206
1207 ret = i2c_add_numbered_adapter(adap);
1208 if (ret < 0)
1209 goto out_pm_put;
1210
1211 if (priv->flags & ID_P_HOST_NOTIFY) {
1212 priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
1213 if (IS_ERR(priv->host_notify_client)) {
1214 ret = PTR_ERR(priv->host_notify_client);
1215 goto out_del_device;
1216 }
1217 }
1218
1219 dev_info(dev, "probed\n");
1220
1221 return 0;
1222
1223 out_del_device:
1224 i2c_del_adapter(&priv->adap);
1225 out_pm_put:
1226 if (priv->flags & ID_P_PM_BLOCKED)
1227 pm_runtime_put(dev);
1228 out_pm_disable:
1229 pm_runtime_disable(dev);
1230 return ret;
1231 }
1232
1233 static void rcar_i2c_remove(struct platform_device *pdev)
1234 {
1235 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1236 struct device *dev = &pdev->dev;
1237
1238 if (priv->host_notify_client)
1239 i2c_free_slave_host_notify_device(priv->host_notify_client);
1240 i2c_del_adapter(&priv->adap);
1241 rcar_i2c_release_dma(priv);
1242 if (priv->flags & ID_P_PM_BLOCKED)
1243 pm_runtime_put(dev);
1244 pm_runtime_disable(dev);
1245 }
1246
1247 static int rcar_i2c_suspend(struct device *dev)
1248 {
1249 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1250
1251 i2c_mark_adapter_suspended(&priv->adap);
1252 return 0;
1253 }
1254
1255 static int rcar_i2c_resume(struct device *dev)
1256 {
1257 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1258
1259 i2c_mark_adapter_resumed(&priv->adap);
1260 return 0;
1261 }
1262
1263 static const struct dev_pm_ops rcar_i2c_pm_ops = {
1264 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1265 };
1266
1267 static struct platform_driver rcar_i2c_driver = {
1268 .driver = {
1269 .name = "i2c-rcar",
1270 .of_match_table = rcar_i2c_dt_ids,
1271 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops),
1272 },
1273 .probe = rcar_i2c_probe,
1274 .remove = rcar_i2c_remove,
1275 };
1276
1277 module_platform_driver(rcar_i2c_driver);
1278
1279 MODULE_LICENSE("GPL v2");
1280 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1281 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Kernel DRM miscellaneous fixes and cross-tree changes