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drm/client: Fix drm client endless Kconfig loop
[drm/drm-misc.git] / drivers / iio / accel / bmc150-accel-core.c
blob744a034bb8b5f27a9184e33db5c90ebcd3e08fbe
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * 3-axis accelerometer driver supporting many Bosch-Sensortec chips
4 * Copyright (c) 2014, Intel Corporation.
5 */
6
7 #include <linux/module.h>
8 #include <linux/i2c.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/slab.h>
12 #include <linux/acpi.h>
13 #include <linux/pm.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/property.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/events.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25
26 #include "bmc150-accel.h"
27
28 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
29 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
30
31 #define BMC150_ACCEL_REG_CHIP_ID 0x00
32
33 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
34 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
35 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
36 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
37 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
38 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
39
40 #define BMC150_ACCEL_REG_PMU_LPW 0x11
41 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
42 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
43 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
44 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
45
46 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
47
48 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
49 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
50 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
51 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
52
53 /* Default BW: 125Hz */
54 #define BMC150_ACCEL_REG_PMU_BW 0x10
55 #define BMC150_ACCEL_DEF_BW 125
56
57 #define BMC150_ACCEL_REG_RESET 0x14
58 #define BMC150_ACCEL_RESET_VAL 0xB6
59
60 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
61 #define BMC150_ACCEL_INT_MAP_0_BIT_INT1_SLOPE BIT(2)
62
63 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
64 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_DATA BIT(0)
65 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_FWM BIT(1)
66 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_FFULL BIT(2)
67 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_FFULL BIT(5)
68 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_FWM BIT(6)
69 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_DATA BIT(7)
70
71 #define BMC150_ACCEL_REG_INT_MAP_2 0x1B
72 #define BMC150_ACCEL_INT_MAP_2_BIT_INT2_SLOPE BIT(2)
73
74 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
75 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
76 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
77 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
78
79 #define BMC150_ACCEL_REG_INT_EN_0 0x16
80 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
81 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
82 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
83
84 #define BMC150_ACCEL_REG_INT_EN_1 0x17
85 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
86 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
87 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
88
89 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
90 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
91 #define BMC150_ACCEL_INT_OUT_CTRL_INT2_LVL BIT(2)
92
93 #define BMC150_ACCEL_REG_INT_5 0x27
94 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
95
96 #define BMC150_ACCEL_REG_INT_6 0x28
97 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
98
99 /* Slope duration in terms of number of samples */
100 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
101 /* in terms of multiples of g's/LSB, based on range */
102 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
103
104 #define BMC150_ACCEL_REG_XOUT_L 0x02
105
106 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
107
108 /* Sleep Duration values */
109 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
110 #define BMC150_ACCEL_SLEEP_1_MS 0x06
111 #define BMC150_ACCEL_SLEEP_2_MS 0x07
112 #define BMC150_ACCEL_SLEEP_4_MS 0x08
113 #define BMC150_ACCEL_SLEEP_6_MS 0x09
114 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
115 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
116 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
117 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
118 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
119 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
120
121 #define BMC150_ACCEL_REG_TEMP 0x08
122 #define BMC150_ACCEL_TEMP_CENTER_VAL 23
123
124 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
125 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
126
127 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
128 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
129 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
130 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
131 #define BMC150_ACCEL_FIFO_LENGTH 32
132
133 enum bmc150_accel_axis {
134 AXIS_X,
135 AXIS_Y,
136 AXIS_Z,
137 AXIS_MAX,
138 };
139
140 enum bmc150_power_modes {
141 BMC150_ACCEL_SLEEP_MODE_NORMAL,
142 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
143 BMC150_ACCEL_SLEEP_MODE_LPM,
144 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
145 };
146
147 struct bmc150_scale_info {
148 int scale;
149 u8 reg_range;
150 };
151
152 struct bmc150_accel_chip_info {
153 const char *name;
154 u8 chip_id;
155 const struct iio_chan_spec *channels;
156 int num_channels;
157 const struct bmc150_scale_info scale_table[4];
158 };
159
160 static const struct {
161 int val;
162 int val2;
163 u8 bw_bits;
164 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
165 {31, 260000, 0x09},
166 {62, 500000, 0x0A},
167 {125, 0, 0x0B},
168 {250, 0, 0x0C},
169 {500, 0, 0x0D},
170 {1000, 0, 0x0E},
171 {2000, 0, 0x0F} };
172
173 static __maybe_unused const struct {
174 int bw_bits;
175 int msec;
176 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
177 {0x09, 32},
178 {0x0A, 16},
179 {0x0B, 8},
180 {0x0C, 4},
181 {0x0D, 2},
182 {0x0E, 1},
183 {0x0F, 1} };
184
185 static const struct {
186 int sleep_dur;
187 u8 reg_value;
188 } bmc150_accel_sleep_value_table[] = { {0, 0},
189 {500, BMC150_ACCEL_SLEEP_500_MICRO},
190 {1000, BMC150_ACCEL_SLEEP_1_MS},
191 {2000, BMC150_ACCEL_SLEEP_2_MS},
192 {4000, BMC150_ACCEL_SLEEP_4_MS},
193 {6000, BMC150_ACCEL_SLEEP_6_MS},
194 {10000, BMC150_ACCEL_SLEEP_10_MS},
195 {25000, BMC150_ACCEL_SLEEP_25_MS},
196 {50000, BMC150_ACCEL_SLEEP_50_MS},
197 {100000, BMC150_ACCEL_SLEEP_100_MS},
198 {500000, BMC150_ACCEL_SLEEP_500_MS},
199 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
200
201 const struct regmap_config bmc150_regmap_conf = {
202 .reg_bits = 8,
203 .val_bits = 8,
204 .max_register = 0x3f,
205 };
206 EXPORT_SYMBOL_NS_GPL(bmc150_regmap_conf, "IIO_BMC150");
207
208 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
209 enum bmc150_power_modes mode,
210 int dur_us)
211 {
212 struct device *dev = regmap_get_device(data->regmap);
213 int i;
214 int ret;
215 u8 lpw_bits;
216 int dur_val = -1;
217
218 if (dur_us > 0) {
219 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
220 ++i) {
221 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
222 dur_us)
223 dur_val =
224 bmc150_accel_sleep_value_table[i].reg_value;
225 }
226 } else {
227 dur_val = 0;
228 }
229
230 if (dur_val < 0)
231 return -EINVAL;
232
233 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
234 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
235
236 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
237
238 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
239 if (ret < 0) {
240 dev_err(dev, "Error writing reg_pmu_lpw\n");
241 return ret;
242 }
243
244 return 0;
245 }
246
247 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
248 int val2)
249 {
250 int i;
251 int ret;
252
253 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
254 if (bmc150_accel_samp_freq_table[i].val == val &&
255 bmc150_accel_samp_freq_table[i].val2 == val2) {
256 ret = regmap_write(data->regmap,
257 BMC150_ACCEL_REG_PMU_BW,
258 bmc150_accel_samp_freq_table[i].bw_bits);
259 if (ret < 0)
260 return ret;
261
262 data->bw_bits =
263 bmc150_accel_samp_freq_table[i].bw_bits;
264 return 0;
265 }
266 }
267
268 return -EINVAL;
269 }
270
271 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
272 {
273 struct device *dev = regmap_get_device(data->regmap);
274 int ret;
275
276 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
277 data->slope_thres);
278 if (ret < 0) {
279 dev_err(dev, "Error writing reg_int_6\n");
280 return ret;
281 }
282
283 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
284 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
285 if (ret < 0) {
286 dev_err(dev, "Error updating reg_int_5\n");
287 return ret;
288 }
289
290 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
291
292 return ret;
293 }
294
295 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
296 bool state)
297 {
298 if (state)
299 return bmc150_accel_update_slope(t->data);
300
301 return 0;
302 }
303
304 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
305 int *val2)
306 {
307 int i;
308
309 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
310 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
311 *val = bmc150_accel_samp_freq_table[i].val;
312 *val2 = bmc150_accel_samp_freq_table[i].val2;
313 return IIO_VAL_INT_PLUS_MICRO;
314 }
315 }
316
317 return -EINVAL;
318 }
319
320 #ifdef CONFIG_PM
321 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
322 {
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
326 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
327 return bmc150_accel_sample_upd_time[i].msec;
328 }
329
330 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
331 }
332
333 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
334 {
335 struct device *dev = regmap_get_device(data->regmap);
336 int ret;
337
338 if (on) {
339 ret = pm_runtime_resume_and_get(dev);
340 } else {
341 pm_runtime_mark_last_busy(dev);
342 ret = pm_runtime_put_autosuspend(dev);
343 }
344
345 if (ret < 0) {
346 dev_err(dev,
347 "Failed: %s for %d\n", __func__, on);
348 return ret;
349 }
350
351 return 0;
352 }
353 #else
354 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
355 {
356 return 0;
357 }
358 #endif
359
360 #ifdef CONFIG_ACPI
361 /*
362 * Support for getting accelerometer information from BOSC0200 ACPI nodes.
363 *
364 * There are 2 variants of the BOSC0200 ACPI node. Some 2-in-1s with 360 degree
365 * hinges declare 2 I2C ACPI-resources for 2 accelerometers, 1 in the display
366 * and 1 in the base of the 2-in-1. On these 2-in-1s the ROMS ACPI object
367 * contains the mount-matrix for the sensor in the display and ROMK contains
368 * the mount-matrix for the sensor in the base. On devices using a single
369 * sensor there is a ROTM ACPI object which contains the mount-matrix.
370 *
371 * Here is an incomplete list of devices known to use 1 of these setups:
372 *
373 * Yoga devices with 2 accelerometers using ROMS + ROMK for the mount-matrices:
374 * Lenovo Thinkpad Yoga 11e 3th gen
375 * Lenovo Thinkpad Yoga 11e 4th gen
376 *
377 * Tablets using a single accelerometer using ROTM for the mount-matrix:
378 * Chuwi Hi8 Pro (CWI513)
379 * Chuwi Vi8 Plus (CWI519)
380 * Chuwi Hi13
381 * Irbis TW90
382 * Jumper EZpad mini 3
383 * Onda V80 plus
384 * Predia Basic Tablet
385 */
386 static bool bmc150_apply_bosc0200_acpi_orientation(struct device *dev,
387 struct iio_mount_matrix *orientation)
388 {
389 struct iio_dev *indio_dev = dev_get_drvdata(dev);
390 acpi_handle handle = ACPI_HANDLE(dev);
391 char *name, *alt_name, *label;
392
393 if (strcmp(dev_name(dev), "i2c-BOSC0200:base") == 0) {
394 alt_name = "ROMK";
395 label = "accel-base";
396 } else {
397 alt_name = "ROMS";
398 label = "accel-display";
399 }
400
401 if (acpi_has_method(handle, "ROTM")) {
402 name = "ROTM";
403 } else if (acpi_has_method(handle, alt_name)) {
404 name = alt_name;
405 indio_dev->label = label;
406 } else {
407 return false;
408 }
409
410 return iio_read_acpi_mount_matrix(dev, orientation, name);
411 }
412
413 static bool bmc150_apply_dual250e_acpi_orientation(struct device *dev,
414 struct iio_mount_matrix *orientation)
415 {
416 struct iio_dev *indio_dev = dev_get_drvdata(dev);
417
418 if (strcmp(dev_name(dev), "i2c-DUAL250E:base") == 0)
419 indio_dev->label = "accel-base";
420 else
421 indio_dev->label = "accel-display";
422
423 return false; /* DUAL250E fwnodes have no mount matrix info */
424 }
425
426 static bool bmc150_apply_acpi_orientation(struct device *dev,
427 struct iio_mount_matrix *orientation)
428 {
429 struct acpi_device *adev = ACPI_COMPANION(dev);
430
431 if (adev && acpi_dev_hid_uid_match(adev, "BOSC0200", NULL))
432 return bmc150_apply_bosc0200_acpi_orientation(dev, orientation);
433
434 if (adev && acpi_dev_hid_uid_match(adev, "DUAL250E", NULL))
435 return bmc150_apply_dual250e_acpi_orientation(dev, orientation);
436
437 return false;
438 }
439 #else
440 static bool bmc150_apply_acpi_orientation(struct device *dev,
441 struct iio_mount_matrix *orientation)
442 {
443 return false;
444 }
445 #endif
446
447 struct bmc150_accel_interrupt_info {
448 u8 map_reg;
449 u8 map_bitmask;
450 u8 en_reg;
451 u8 en_bitmask;
452 };
453
454 static const struct bmc150_accel_interrupt_info
455 bmc150_accel_interrupts_int1[BMC150_ACCEL_INTERRUPTS] = {
456 { /* data ready interrupt */
457 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
458 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT1_DATA,
459 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
460 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
461 },
462 { /* motion interrupt */
463 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
464 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_INT1_SLOPE,
465 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
466 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
467 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
468 BMC150_ACCEL_INT_EN_BIT_SLP_Z
469 },
470 { /* fifo watermark interrupt */
471 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
472 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT1_FWM,
473 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
474 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
475 },
476 };
477
478 static const struct bmc150_accel_interrupt_info
479 bmc150_accel_interrupts_int2[BMC150_ACCEL_INTERRUPTS] = {
480 { /* data ready interrupt */
481 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
482 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT2_DATA,
483 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
484 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
485 },
486 { /* motion interrupt */
487 .map_reg = BMC150_ACCEL_REG_INT_MAP_2,
488 .map_bitmask = BMC150_ACCEL_INT_MAP_2_BIT_INT2_SLOPE,
489 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
490 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
491 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
492 BMC150_ACCEL_INT_EN_BIT_SLP_Z
493 },
494 { /* fifo watermark interrupt */
495 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
496 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT2_FWM,
497 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
498 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
499 },
500 };
501
502 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
503 struct bmc150_accel_data *data, int irq)
504 {
505 const struct bmc150_accel_interrupt_info *irq_info = NULL;
506 struct device *dev = regmap_get_device(data->regmap);
507 int i;
508
509 /*
510 * For now we map all interrupts to the same output pin.
511 * However, some boards may have just INT2 (and not INT1) connected,
512 * so we try to detect which IRQ it is based on the interrupt-names.
513 * Without interrupt-names, we assume the irq belongs to INT1.
514 */
515 irq_info = bmc150_accel_interrupts_int1;
516 if (data->type == BOSCH_BMC156 ||
517 irq == fwnode_irq_get_byname(dev_fwnode(dev), "INT2"))
518 irq_info = bmc150_accel_interrupts_int2;
519
520 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
521 data->interrupts[i].info = &irq_info[i];
522 }
523
524 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
525 bool state)
526 {
527 struct device *dev = regmap_get_device(data->regmap);
528 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
529 const struct bmc150_accel_interrupt_info *info = intr->info;
530 int ret;
531
532 if (state) {
533 if (atomic_inc_return(&intr->users) > 1)
534 return 0;
535 } else {
536 if (atomic_dec_return(&intr->users) > 0)
537 return 0;
538 }
539
540 /*
541 * We will expect the enable and disable to do operation in reverse
542 * order. This will happen here anyway, as our resume operation uses
543 * sync mode runtime pm calls. The suspend operation will be delayed
544 * by autosuspend delay.
545 * So the disable operation will still happen in reverse order of
546 * enable operation. When runtime pm is disabled the mode is always on,
547 * so sequence doesn't matter.
548 */
549 ret = bmc150_accel_set_power_state(data, state);
550 if (ret < 0)
551 return ret;
552
553 /* map the interrupt to the appropriate pins */
554 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
555 (state ? info->map_bitmask : 0));
556 if (ret < 0) {
557 dev_err(dev, "Error updating reg_int_map\n");
558 goto out_fix_power_state;
559 }
560
561 /* enable/disable the interrupt */
562 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
563 (state ? info->en_bitmask : 0));
564 if (ret < 0) {
565 dev_err(dev, "Error updating reg_int_en\n");
566 goto out_fix_power_state;
567 }
568
569 return 0;
570
571 out_fix_power_state:
572 bmc150_accel_set_power_state(data, false);
573 return ret;
574 }
575
576 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
577 {
578 struct device *dev = regmap_get_device(data->regmap);
579 int ret, i;
580
581 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
582 if (data->chip_info->scale_table[i].scale == val) {
583 ret = regmap_write(data->regmap,
584 BMC150_ACCEL_REG_PMU_RANGE,
585 data->chip_info->scale_table[i].reg_range);
586 if (ret < 0) {
587 dev_err(dev, "Error writing pmu_range\n");
588 return ret;
589 }
590
591 data->range = data->chip_info->scale_table[i].reg_range;
592 return 0;
593 }
594 }
595
596 return -EINVAL;
597 }
598
599 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
600 {
601 struct device *dev = regmap_get_device(data->regmap);
602 int ret;
603 unsigned int value;
604
605 mutex_lock(&data->mutex);
606
607 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
608 if (ret < 0) {
609 dev_err(dev, "Error reading reg_temp\n");
610 mutex_unlock(&data->mutex);
611 return ret;
612 }
613 *val = sign_extend32(value, 7);
614
615 mutex_unlock(&data->mutex);
616
617 return IIO_VAL_INT;
618 }
619
620 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
621 struct iio_chan_spec const *chan,
622 int *val)
623 {
624 struct device *dev = regmap_get_device(data->regmap);
625 int ret;
626 int axis = chan->scan_index;
627 __le16 raw_val;
628
629 mutex_lock(&data->mutex);
630 ret = bmc150_accel_set_power_state(data, true);
631 if (ret < 0) {
632 mutex_unlock(&data->mutex);
633 return ret;
634 }
635
636 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
637 &raw_val, sizeof(raw_val));
638 if (ret < 0) {
639 dev_err(dev, "Error reading axis %d\n", axis);
640 bmc150_accel_set_power_state(data, false);
641 mutex_unlock(&data->mutex);
642 return ret;
643 }
644 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
645 chan->scan_type.realbits - 1);
646 ret = bmc150_accel_set_power_state(data, false);
647 mutex_unlock(&data->mutex);
648 if (ret < 0)
649 return ret;
650
651 return IIO_VAL_INT;
652 }
653
654 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
655 struct iio_chan_spec const *chan,
656 int *val, int *val2, long mask)
657 {
658 struct bmc150_accel_data *data = iio_priv(indio_dev);
659 int ret;
660
661 switch (mask) {
662 case IIO_CHAN_INFO_RAW:
663 switch (chan->type) {
664 case IIO_TEMP:
665 return bmc150_accel_get_temp(data, val);
666 case IIO_ACCEL:
667 if (iio_buffer_enabled(indio_dev))
668 return -EBUSY;
669 else
670 return bmc150_accel_get_axis(data, chan, val);
671 default:
672 return -EINVAL;
673 }
674 case IIO_CHAN_INFO_OFFSET:
675 if (chan->type == IIO_TEMP) {
676 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
677 return IIO_VAL_INT;
678 } else {
679 return -EINVAL;
680 }
681 case IIO_CHAN_INFO_SCALE:
682 *val = 0;
683 switch (chan->type) {
684 case IIO_TEMP:
685 *val2 = 500000;
686 return IIO_VAL_INT_PLUS_MICRO;
687 case IIO_ACCEL:
688 {
689 int i;
690 const struct bmc150_scale_info *si;
691 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
692
693 for (i = 0; i < st_size; ++i) {
694 si = &data->chip_info->scale_table[i];
695 if (si->reg_range == data->range) {
696 *val2 = si->scale;
697 return IIO_VAL_INT_PLUS_MICRO;
698 }
699 }
700 return -EINVAL;
701 }
702 default:
703 return -EINVAL;
704 }
705 case IIO_CHAN_INFO_SAMP_FREQ:
706 mutex_lock(&data->mutex);
707 ret = bmc150_accel_get_bw(data, val, val2);
708 mutex_unlock(&data->mutex);
709 return ret;
710 default:
711 return -EINVAL;
712 }
713 }
714
715 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
716 struct iio_chan_spec const *chan,
717 int val, int val2, long mask)
718 {
719 struct bmc150_accel_data *data = iio_priv(indio_dev);
720 int ret;
721
722 switch (mask) {
723 case IIO_CHAN_INFO_SAMP_FREQ:
724 mutex_lock(&data->mutex);
725 ret = bmc150_accel_set_bw(data, val, val2);
726 mutex_unlock(&data->mutex);
727 break;
728 case IIO_CHAN_INFO_SCALE:
729 if (val)
730 return -EINVAL;
731
732 mutex_lock(&data->mutex);
733 ret = bmc150_accel_set_scale(data, val2);
734 mutex_unlock(&data->mutex);
735 return ret;
736 default:
737 ret = -EINVAL;
738 }
739
740 return ret;
741 }
742
743 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
744 const struct iio_chan_spec *chan,
745 enum iio_event_type type,
746 enum iio_event_direction dir,
747 enum iio_event_info info,
748 int *val, int *val2)
749 {
750 struct bmc150_accel_data *data = iio_priv(indio_dev);
751
752 *val2 = 0;
753 switch (info) {
754 case IIO_EV_INFO_VALUE:
755 *val = data->slope_thres;
756 break;
757 case IIO_EV_INFO_PERIOD:
758 *val = data->slope_dur;
759 break;
760 default:
761 return -EINVAL;
762 }
763
764 return IIO_VAL_INT;
765 }
766
767 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
768 const struct iio_chan_spec *chan,
769 enum iio_event_type type,
770 enum iio_event_direction dir,
771 enum iio_event_info info,
772 int val, int val2)
773 {
774 struct bmc150_accel_data *data = iio_priv(indio_dev);
775
776 if (data->ev_enable_state)
777 return -EBUSY;
778
779 switch (info) {
780 case IIO_EV_INFO_VALUE:
781 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
782 break;
783 case IIO_EV_INFO_PERIOD:
784 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
785 break;
786 default:
787 return -EINVAL;
788 }
789
790 return 0;
791 }
792
793 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
794 const struct iio_chan_spec *chan,
795 enum iio_event_type type,
796 enum iio_event_direction dir)
797 {
798 struct bmc150_accel_data *data = iio_priv(indio_dev);
799
800 return data->ev_enable_state;
801 }
802
803 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
804 const struct iio_chan_spec *chan,
805 enum iio_event_type type,
806 enum iio_event_direction dir,
807 bool state)
808 {
809 struct bmc150_accel_data *data = iio_priv(indio_dev);
810 int ret;
811
812 if (state == data->ev_enable_state)
813 return 0;
814
815 mutex_lock(&data->mutex);
816
817 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
818 state);
819 if (ret < 0) {
820 mutex_unlock(&data->mutex);
821 return ret;
822 }
823
824 data->ev_enable_state = state;
825 mutex_unlock(&data->mutex);
826
827 return 0;
828 }
829
830 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
831 struct iio_trigger *trig)
832 {
833 struct bmc150_accel_data *data = iio_priv(indio_dev);
834 int i;
835
836 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
837 if (data->triggers[i].indio_trig == trig)
838 return 0;
839 }
840
841 return -EINVAL;
842 }
843
844 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
845 struct device_attribute *attr,
846 char *buf)
847 {
848 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
849 struct bmc150_accel_data *data = iio_priv(indio_dev);
850 int wm;
851
852 mutex_lock(&data->mutex);
853 wm = data->watermark;
854 mutex_unlock(&data->mutex);
855
856 return sprintf(buf, "%d\n", wm);
857 }
858
859 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
860 struct device_attribute *attr,
861 char *buf)
862 {
863 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
864 struct bmc150_accel_data *data = iio_priv(indio_dev);
865 bool state;
866
867 mutex_lock(&data->mutex);
868 state = data->fifo_mode;
869 mutex_unlock(&data->mutex);
870
871 return sprintf(buf, "%d\n", state);
872 }
873
874 static const struct iio_mount_matrix *
875 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev,
876 const struct iio_chan_spec *chan)
877 {
878 struct bmc150_accel_data *data = iio_priv(indio_dev);
879
880 return &data->orientation;
881 }
882
883 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = {
884 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix),
885 { }
886 };
887
888 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
889 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
890 __stringify(BMC150_ACCEL_FIFO_LENGTH));
891 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
892 bmc150_accel_get_fifo_state, NULL, 0);
893 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
894 bmc150_accel_get_fifo_watermark, NULL, 0);
895
896 static const struct iio_dev_attr *bmc150_accel_fifo_attributes[] = {
897 &iio_dev_attr_hwfifo_watermark_min,
898 &iio_dev_attr_hwfifo_watermark_max,
899 &iio_dev_attr_hwfifo_watermark,
900 &iio_dev_attr_hwfifo_enabled,
901 NULL,
902 };
903
904 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
905 {
906 struct bmc150_accel_data *data = iio_priv(indio_dev);
907
908 if (val > BMC150_ACCEL_FIFO_LENGTH)
909 val = BMC150_ACCEL_FIFO_LENGTH;
910
911 mutex_lock(&data->mutex);
912 data->watermark = val;
913 mutex_unlock(&data->mutex);
914
915 return 0;
916 }
917
918 /*
919 * We must read at least one full frame in one burst, otherwise the rest of the
920 * frame data is discarded.
921 */
922 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
923 char *buffer, int samples)
924 {
925 struct device *dev = regmap_get_device(data->regmap);
926 int sample_length = 3 * 2;
927 int ret;
928 int total_length = samples * sample_length;
929
930 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
931 buffer, total_length);
932 if (ret)
933 dev_err(dev,
934 "Error transferring data from fifo: %d\n", ret);
935
936 return ret;
937 }
938
939 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
940 unsigned samples, bool irq)
941 {
942 struct bmc150_accel_data *data = iio_priv(indio_dev);
943 struct device *dev = regmap_get_device(data->regmap);
944 int ret, i;
945 u8 count;
946 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
947 int64_t tstamp;
948 uint64_t sample_period;
949 unsigned int val;
950
951 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
952 if (ret < 0) {
953 dev_err(dev, "Error reading reg_fifo_status\n");
954 return ret;
955 }
956
957 count = val & 0x7F;
958
959 if (!count)
960 return 0;
961
962 /*
963 * If we getting called from IRQ handler we know the stored timestamp is
964 * fairly accurate for the last stored sample. Otherwise, if we are
965 * called as a result of a read operation from userspace and hence
966 * before the watermark interrupt was triggered, take a timestamp
967 * now. We can fall anywhere in between two samples so the error in this
968 * case is at most one sample period.
969 */
970 if (!irq) {
971 data->old_timestamp = data->timestamp;
972 data->timestamp = iio_get_time_ns(indio_dev);
973 }
974
975 /*
976 * Approximate timestamps for each of the sample based on the sampling
977 * frequency, timestamp for last sample and number of samples.
978 *
979 * Note that we can't use the current bandwidth settings to compute the
980 * sample period because the sample rate varies with the device
981 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
982 * small variation adds when we store a large number of samples and
983 * creates significant jitter between the last and first samples in
984 * different batches (e.g. 32ms vs 21ms).
985 *
986 * To avoid this issue we compute the actual sample period ourselves
987 * based on the timestamp delta between the last two flush operations.
988 */
989 sample_period = (data->timestamp - data->old_timestamp);
990 do_div(sample_period, count);
991 tstamp = data->timestamp - (count - 1) * sample_period;
992
993 if (samples && count > samples)
994 count = samples;
995
996 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
997 if (ret)
998 return ret;
999
1000 /*
1001 * Ideally we want the IIO core to handle the demux when running in fifo
1002 * mode but not when running in triggered buffer mode. Unfortunately
1003 * this does not seem to be possible, so stick with driver demux for
1004 * now.
1005 */
1006 for (i = 0; i < count; i++) {
1007 int j, bit;
1008
1009 j = 0;
1010 iio_for_each_active_channel(indio_dev, bit)
1011 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
1012 sizeof(data->scan.channels[0]));
1013
1014 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
1015 tstamp);
1016
1017 tstamp += sample_period;
1018 }
1019
1020 return count;
1021 }
1022
1023 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
1024 {
1025 struct bmc150_accel_data *data = iio_priv(indio_dev);
1026 int ret;
1027
1028 mutex_lock(&data->mutex);
1029 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
1030 mutex_unlock(&data->mutex);
1031
1032 return ret;
1033 }
1034
1035 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
1036 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
1037
1038 static struct attribute *bmc150_accel_attributes[] = {
1039 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1040 NULL,
1041 };
1042
1043 static const struct attribute_group bmc150_accel_attrs_group = {
1044 .attrs = bmc150_accel_attributes,
1045 };
1046
1047 static const struct iio_event_spec bmc150_accel_event = {
1048 .type = IIO_EV_TYPE_ROC,
1049 .dir = IIO_EV_DIR_EITHER,
1050 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1051 BIT(IIO_EV_INFO_ENABLE) |
1052 BIT(IIO_EV_INFO_PERIOD)
1053 };
1054
1055 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
1056 .type = IIO_ACCEL, \
1057 .modified = 1, \
1058 .channel2 = IIO_MOD_##_axis, \
1059 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1060 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
1061 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1062 .scan_index = AXIS_##_axis, \
1063 .scan_type = { \
1064 .sign = 's', \
1065 .realbits = (bits), \
1066 .storagebits = 16, \
1067 .shift = 16 - (bits), \
1068 .endianness = IIO_LE, \
1069 }, \
1070 .ext_info = bmc150_accel_ext_info, \
1071 .event_spec = &bmc150_accel_event, \
1072 .num_event_specs = 1 \
1073 }
1074
1075 #define BMC150_ACCEL_CHANNELS(bits) { \
1076 { \
1077 .type = IIO_TEMP, \
1078 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1079 BIT(IIO_CHAN_INFO_SCALE) | \
1080 BIT(IIO_CHAN_INFO_OFFSET), \
1081 .scan_index = -1, \
1082 }, \
1083 BMC150_ACCEL_CHANNEL(X, bits), \
1084 BMC150_ACCEL_CHANNEL(Y, bits), \
1085 BMC150_ACCEL_CHANNEL(Z, bits), \
1086 IIO_CHAN_SOFT_TIMESTAMP(3), \
1087 }
1088
1089 static const struct iio_chan_spec bma222e_accel_channels[] =
1090 BMC150_ACCEL_CHANNELS(8);
1091 static const struct iio_chan_spec bma250e_accel_channels[] =
1092 BMC150_ACCEL_CHANNELS(10);
1093 static const struct iio_chan_spec bmc150_accel_channels[] =
1094 BMC150_ACCEL_CHANNELS(12);
1095 static const struct iio_chan_spec bma280_accel_channels[] =
1096 BMC150_ACCEL_CHANNELS(14);
1097
1098 /*
1099 * The range for the Bosch sensors is typically +-2g/4g/8g/16g, distributed
1100 * over the amount of bits (see above). The scale table can be calculated using
1101 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2
1102 * e.g. for +-2g and 12 bits: (4 / 2^12) * 9.80665 m/s^2 = 0.0095768... m/s^2
1103 * Multiply 10^6 and round to get the values listed below.
1104 */
1105 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1106 {
1107 .name = "BMA222",
1108 .chip_id = 0x03,
1109 .channels = bma222e_accel_channels,
1110 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1111 .scale_table = { {153229, BMC150_ACCEL_DEF_RANGE_2G},
1112 {306458, BMC150_ACCEL_DEF_RANGE_4G},
1113 {612916, BMC150_ACCEL_DEF_RANGE_8G},
1114 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1115 },
1116 {
1117 .name = "BMA222E",
1118 .chip_id = 0xF8,
1119 .channels = bma222e_accel_channels,
1120 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1121 .scale_table = { {153229, BMC150_ACCEL_DEF_RANGE_2G},
1122 {306458, BMC150_ACCEL_DEF_RANGE_4G},
1123 {612916, BMC150_ACCEL_DEF_RANGE_8G},
1124 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1125 },
1126 {
1127 .name = "BMA250E",
1128 .chip_id = 0xF9,
1129 .channels = bma250e_accel_channels,
1130 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1131 .scale_table = { {38307, BMC150_ACCEL_DEF_RANGE_2G},
1132 {76614, BMC150_ACCEL_DEF_RANGE_4G},
1133 {153229, BMC150_ACCEL_DEF_RANGE_8G},
1134 {306458, BMC150_ACCEL_DEF_RANGE_16G} },
1135 },
1136 {
1137 .name = "BMA253/BMA254/BMA255/BMC150/BMC156/BMI055",
1138 .chip_id = 0xFA,
1139 .channels = bmc150_accel_channels,
1140 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1141 .scale_table = { {9577, BMC150_ACCEL_DEF_RANGE_2G},
1142 {19154, BMC150_ACCEL_DEF_RANGE_4G},
1143 {38307, BMC150_ACCEL_DEF_RANGE_8G},
1144 {76614, BMC150_ACCEL_DEF_RANGE_16G} },
1145 },
1146 {
1147 .name = "BMA280",
1148 .chip_id = 0xFB,
1149 .channels = bma280_accel_channels,
1150 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1151 .scale_table = { {2394, BMC150_ACCEL_DEF_RANGE_2G},
1152 {4788, BMC150_ACCEL_DEF_RANGE_4G},
1153 {9577, BMC150_ACCEL_DEF_RANGE_8G},
1154 {19154, BMC150_ACCEL_DEF_RANGE_16G} },
1155 },
1156 };
1157
1158 static const struct iio_info bmc150_accel_info = {
1159 .attrs = &bmc150_accel_attrs_group,
1160 .read_raw = bmc150_accel_read_raw,
1161 .write_raw = bmc150_accel_write_raw,
1162 .read_event_value = bmc150_accel_read_event,
1163 .write_event_value = bmc150_accel_write_event,
1164 .write_event_config = bmc150_accel_write_event_config,
1165 .read_event_config = bmc150_accel_read_event_config,
1166 };
1167
1168 static const struct iio_info bmc150_accel_info_fifo = {
1169 .attrs = &bmc150_accel_attrs_group,
1170 .read_raw = bmc150_accel_read_raw,
1171 .write_raw = bmc150_accel_write_raw,
1172 .read_event_value = bmc150_accel_read_event,
1173 .write_event_value = bmc150_accel_write_event,
1174 .write_event_config = bmc150_accel_write_event_config,
1175 .read_event_config = bmc150_accel_read_event_config,
1176 .validate_trigger = bmc150_accel_validate_trigger,
1177 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1178 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1179 };
1180
1181 static const unsigned long bmc150_accel_scan_masks[] = {
1182 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1183 0};
1184
1185 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1186 {
1187 struct iio_poll_func *pf = p;
1188 struct iio_dev *indio_dev = pf->indio_dev;
1189 struct bmc150_accel_data *data = iio_priv(indio_dev);
1190 int ret;
1191
1192 mutex_lock(&data->mutex);
1193 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1194 data->buffer, AXIS_MAX * 2);
1195 mutex_unlock(&data->mutex);
1196 if (ret < 0)
1197 goto err_read;
1198
1199 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1200 pf->timestamp);
1201 err_read:
1202 iio_trigger_notify_done(indio_dev->trig);
1203
1204 return IRQ_HANDLED;
1205 }
1206
1207 static void bmc150_accel_trig_reen(struct iio_trigger *trig)
1208 {
1209 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1210 struct bmc150_accel_data *data = t->data;
1211 struct device *dev = regmap_get_device(data->regmap);
1212 int ret;
1213
1214 /* new data interrupts don't need ack */
1215 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1216 return;
1217
1218 mutex_lock(&data->mutex);
1219 /* clear any latched interrupt */
1220 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1221 BMC150_ACCEL_INT_MODE_LATCH_INT |
1222 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1223 mutex_unlock(&data->mutex);
1224 if (ret < 0)
1225 dev_err(dev, "Error writing reg_int_rst_latch\n");
1226 }
1227
1228 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1229 bool state)
1230 {
1231 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1232 struct bmc150_accel_data *data = t->data;
1233 int ret;
1234
1235 mutex_lock(&data->mutex);
1236
1237 if (t->enabled == state) {
1238 mutex_unlock(&data->mutex);
1239 return 0;
1240 }
1241
1242 if (t->setup) {
1243 ret = t->setup(t, state);
1244 if (ret < 0) {
1245 mutex_unlock(&data->mutex);
1246 return ret;
1247 }
1248 }
1249
1250 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1251 if (ret < 0) {
1252 mutex_unlock(&data->mutex);
1253 return ret;
1254 }
1255
1256 t->enabled = state;
1257
1258 mutex_unlock(&data->mutex);
1259
1260 return ret;
1261 }
1262
1263 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1264 .set_trigger_state = bmc150_accel_trigger_set_state,
1265 .reenable = bmc150_accel_trig_reen,
1266 };
1267
1268 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1269 {
1270 struct bmc150_accel_data *data = iio_priv(indio_dev);
1271 struct device *dev = regmap_get_device(data->regmap);
1272 int dir;
1273 int ret;
1274 unsigned int val;
1275
1276 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1277 if (ret < 0) {
1278 dev_err(dev, "Error reading reg_int_status_2\n");
1279 return ret;
1280 }
1281
1282 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1283 dir = IIO_EV_DIR_FALLING;
1284 else
1285 dir = IIO_EV_DIR_RISING;
1286
1287 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1288 iio_push_event(indio_dev,
1289 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1290 0,
1291 IIO_MOD_X,
1292 IIO_EV_TYPE_ROC,
1293 dir),
1294 data->timestamp);
1295
1296 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1297 iio_push_event(indio_dev,
1298 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1299 0,
1300 IIO_MOD_Y,
1301 IIO_EV_TYPE_ROC,
1302 dir),
1303 data->timestamp);
1304
1305 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1306 iio_push_event(indio_dev,
1307 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1308 0,
1309 IIO_MOD_Z,
1310 IIO_EV_TYPE_ROC,
1311 dir),
1312 data->timestamp);
1313
1314 return ret;
1315 }
1316
1317 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1318 {
1319 struct iio_dev *indio_dev = private;
1320 struct bmc150_accel_data *data = iio_priv(indio_dev);
1321 struct device *dev = regmap_get_device(data->regmap);
1322 bool ack = false;
1323 int ret;
1324
1325 mutex_lock(&data->mutex);
1326
1327 if (data->fifo_mode) {
1328 ret = __bmc150_accel_fifo_flush(indio_dev,
1329 BMC150_ACCEL_FIFO_LENGTH, true);
1330 if (ret > 0)
1331 ack = true;
1332 }
1333
1334 if (data->ev_enable_state) {
1335 ret = bmc150_accel_handle_roc_event(indio_dev);
1336 if (ret > 0)
1337 ack = true;
1338 }
1339
1340 if (ack) {
1341 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1342 BMC150_ACCEL_INT_MODE_LATCH_INT |
1343 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1344 if (ret)
1345 dev_err(dev, "Error writing reg_int_rst_latch\n");
1346
1347 ret = IRQ_HANDLED;
1348 } else {
1349 ret = IRQ_NONE;
1350 }
1351
1352 mutex_unlock(&data->mutex);
1353
1354 return ret;
1355 }
1356
1357 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1358 {
1359 struct iio_dev *indio_dev = private;
1360 struct bmc150_accel_data *data = iio_priv(indio_dev);
1361 bool ack = false;
1362 int i;
1363
1364 data->old_timestamp = data->timestamp;
1365 data->timestamp = iio_get_time_ns(indio_dev);
1366
1367 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1368 if (data->triggers[i].enabled) {
1369 iio_trigger_poll(data->triggers[i].indio_trig);
1370 ack = true;
1371 break;
1372 }
1373 }
1374
1375 if (data->ev_enable_state || data->fifo_mode)
1376 return IRQ_WAKE_THREAD;
1377
1378 if (ack)
1379 return IRQ_HANDLED;
1380
1381 return IRQ_NONE;
1382 }
1383
1384 static const struct {
1385 int intr;
1386 const char *name;
1387 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1388 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1389 {
1390 .intr = 0,
1391 .name = "%s-dev%d",
1392 },
1393 {
1394 .intr = 1,
1395 .name = "%s-any-motion-dev%d",
1396 .setup = bmc150_accel_any_motion_setup,
1397 },
1398 };
1399
1400 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1401 int from)
1402 {
1403 int i;
1404
1405 for (i = from; i >= 0; i--) {
1406 if (data->triggers[i].indio_trig) {
1407 iio_trigger_unregister(data->triggers[i].indio_trig);
1408 data->triggers[i].indio_trig = NULL;
1409 }
1410 }
1411 }
1412
1413 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1414 struct bmc150_accel_data *data)
1415 {
1416 struct device *dev = regmap_get_device(data->regmap);
1417 int i, ret;
1418
1419 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1420 struct bmc150_accel_trigger *t = &data->triggers[i];
1421
1422 t->indio_trig = devm_iio_trigger_alloc(dev,
1423 bmc150_accel_triggers[i].name,
1424 indio_dev->name,
1425 iio_device_id(indio_dev));
1426 if (!t->indio_trig) {
1427 ret = -ENOMEM;
1428 break;
1429 }
1430
1431 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1432 t->intr = bmc150_accel_triggers[i].intr;
1433 t->data = data;
1434 t->setup = bmc150_accel_triggers[i].setup;
1435 iio_trigger_set_drvdata(t->indio_trig, t);
1436
1437 ret = iio_trigger_register(t->indio_trig);
1438 if (ret)
1439 break;
1440 }
1441
1442 if (ret)
1443 bmc150_accel_unregister_triggers(data, i - 1);
1444
1445 return ret;
1446 }
1447
1448 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1449 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1450 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1451
1452 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1453 {
1454 struct device *dev = regmap_get_device(data->regmap);
1455 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1456 int ret;
1457
1458 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1459 if (ret < 0) {
1460 dev_err(dev, "Error writing reg_fifo_config1\n");
1461 return ret;
1462 }
1463
1464 if (!data->fifo_mode)
1465 return 0;
1466
1467 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1468 data->watermark);
1469 if (ret < 0)
1470 dev_err(dev, "Error writing reg_fifo_config0\n");
1471
1472 return ret;
1473 }
1474
1475 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1476 {
1477 struct bmc150_accel_data *data = iio_priv(indio_dev);
1478
1479 return bmc150_accel_set_power_state(data, true);
1480 }
1481
1482 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1483 {
1484 struct bmc150_accel_data *data = iio_priv(indio_dev);
1485 int ret = 0;
1486
1487 if (iio_device_get_current_mode(indio_dev) == INDIO_BUFFER_TRIGGERED)
1488 return 0;
1489
1490 mutex_lock(&data->mutex);
1491
1492 if (!data->watermark)
1493 goto out;
1494
1495 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1496 true);
1497 if (ret)
1498 goto out;
1499
1500 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1501
1502 ret = bmc150_accel_fifo_set_mode(data);
1503 if (ret) {
1504 data->fifo_mode = 0;
1505 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1506 false);
1507 }
1508
1509 out:
1510 mutex_unlock(&data->mutex);
1511
1512 return ret;
1513 }
1514
1515 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1516 {
1517 struct bmc150_accel_data *data = iio_priv(indio_dev);
1518
1519 if (iio_device_get_current_mode(indio_dev) == INDIO_BUFFER_TRIGGERED)
1520 return 0;
1521
1522 mutex_lock(&data->mutex);
1523
1524 if (!data->fifo_mode)
1525 goto out;
1526
1527 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1528 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1529 data->fifo_mode = 0;
1530 bmc150_accel_fifo_set_mode(data);
1531
1532 out:
1533 mutex_unlock(&data->mutex);
1534
1535 return 0;
1536 }
1537
1538 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1539 {
1540 struct bmc150_accel_data *data = iio_priv(indio_dev);
1541
1542 return bmc150_accel_set_power_state(data, false);
1543 }
1544
1545 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1546 .preenable = bmc150_accel_buffer_preenable,
1547 .postenable = bmc150_accel_buffer_postenable,
1548 .predisable = bmc150_accel_buffer_predisable,
1549 .postdisable = bmc150_accel_buffer_postdisable,
1550 };
1551
1552 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1553 {
1554 struct device *dev = regmap_get_device(data->regmap);
1555 int ret, i;
1556 unsigned int val;
1557
1558 /*
1559 * Reset chip to get it in a known good state. A delay of 1.8ms after
1560 * reset is required according to the data sheets of supported chips.
1561 */
1562 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1563 BMC150_ACCEL_RESET_VAL);
1564 usleep_range(1800, 2500);
1565
1566 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1567 if (ret < 0) {
1568 dev_err(dev, "Error: Reading chip id\n");
1569 return ret;
1570 }
1571
1572 dev_dbg(dev, "Chip Id %x\n", val);
1573 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1574 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1575 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1576 break;
1577 }
1578 }
1579
1580 if (!data->chip_info) {
1581 dev_err(dev, "Invalid chip %x\n", val);
1582 return -ENODEV;
1583 }
1584
1585 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1586 if (ret < 0)
1587 return ret;
1588
1589 /* Set Bandwidth */
1590 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1591 if (ret < 0)
1592 return ret;
1593
1594 /* Set Default Range */
1595 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1596 BMC150_ACCEL_DEF_RANGE_4G);
1597 if (ret < 0) {
1598 dev_err(dev, "Error writing reg_pmu_range\n");
1599 return ret;
1600 }
1601
1602 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1603
1604 /* Set default slope duration and thresholds */
1605 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1606 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1607 ret = bmc150_accel_update_slope(data);
1608 if (ret < 0)
1609 return ret;
1610
1611 /* Set default as latched interrupts */
1612 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1613 BMC150_ACCEL_INT_MODE_LATCH_INT |
1614 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1615 if (ret < 0) {
1616 dev_err(dev, "Error writing reg_int_rst_latch\n");
1617 return ret;
1618 }
1619
1620 return 0;
1621 }
1622
1623 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1624 enum bmc150_type type, const char *name,
1625 bool block_supported)
1626 {
1627 const struct iio_dev_attr **fifo_attrs;
1628 struct bmc150_accel_data *data;
1629 struct iio_dev *indio_dev;
1630 int ret;
1631
1632 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1633 if (!indio_dev)
1634 return -ENOMEM;
1635
1636 data = iio_priv(indio_dev);
1637 dev_set_drvdata(dev, indio_dev);
1638
1639 data->regmap = regmap;
1640 data->type = type;
1641
1642 if (!bmc150_apply_acpi_orientation(dev, &data->orientation)) {
1643 ret = iio_read_mount_matrix(dev, &data->orientation);
1644 if (ret)
1645 return ret;
1646 }
1647
1648 /*
1649 * VDD is the analog and digital domain voltage supply
1650 * VDDIO is the digital I/O voltage supply
1651 */
1652 data->regulators[0].supply = "vdd";
1653 data->regulators[1].supply = "vddio";
1654 ret = devm_regulator_bulk_get(dev,
1655 ARRAY_SIZE(data->regulators),
1656 data->regulators);
1657 if (ret)
1658 return dev_err_probe(dev, ret, "failed to get regulators\n");
1659
1660 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
1661 data->regulators);
1662 if (ret) {
1663 dev_err(dev, "failed to enable regulators: %d\n", ret);
1664 return ret;
1665 }
1666 /*
1667 * 2ms or 3ms power-on time according to datasheets, let's better
1668 * be safe than sorry and set this delay to 5ms.
1669 */
1670 msleep(5);
1671
1672 ret = bmc150_accel_chip_init(data);
1673 if (ret < 0)
1674 goto err_disable_regulators;
1675
1676 mutex_init(&data->mutex);
1677
1678 indio_dev->channels = data->chip_info->channels;
1679 indio_dev->num_channels = data->chip_info->num_channels;
1680 indio_dev->name = name ? name : data->chip_info->name;
1681 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1682 indio_dev->modes = INDIO_DIRECT_MODE;
1683 indio_dev->info = &bmc150_accel_info;
1684
1685 if (block_supported) {
1686 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1687 indio_dev->info = &bmc150_accel_info_fifo;
1688 fifo_attrs = bmc150_accel_fifo_attributes;
1689 } else {
1690 fifo_attrs = NULL;
1691 }
1692
1693 ret = iio_triggered_buffer_setup_ext(indio_dev,
1694 &iio_pollfunc_store_time,
1695 bmc150_accel_trigger_handler,
1696 IIO_BUFFER_DIRECTION_IN,
1697 &bmc150_accel_buffer_ops,
1698 fifo_attrs);
1699 if (ret < 0) {
1700 dev_err(dev, "Failed: iio triggered buffer setup\n");
1701 goto err_disable_regulators;
1702 }
1703
1704 if (irq > 0) {
1705 ret = devm_request_threaded_irq(dev, irq,
1706 bmc150_accel_irq_handler,
1707 bmc150_accel_irq_thread_handler,
1708 IRQF_TRIGGER_RISING,
1709 BMC150_ACCEL_IRQ_NAME,
1710 indio_dev);
1711 if (ret)
1712 goto err_buffer_cleanup;
1713
1714 /*
1715 * Set latched mode interrupt. While certain interrupts are
1716 * non-latched regardless of this settings (e.g. new data) we
1717 * want to use latch mode when we can to prevent interrupt
1718 * flooding.
1719 */
1720 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1721 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1722 if (ret < 0) {
1723 dev_err(dev, "Error writing reg_int_rst_latch\n");
1724 goto err_buffer_cleanup;
1725 }
1726
1727 bmc150_accel_interrupts_setup(indio_dev, data, irq);
1728
1729 ret = bmc150_accel_triggers_setup(indio_dev, data);
1730 if (ret)
1731 goto err_buffer_cleanup;
1732 }
1733
1734 ret = pm_runtime_set_active(dev);
1735 if (ret)
1736 goto err_trigger_unregister;
1737
1738 pm_runtime_enable(dev);
1739 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1740 pm_runtime_use_autosuspend(dev);
1741
1742 ret = iio_device_register(indio_dev);
1743 if (ret < 0) {
1744 dev_err(dev, "Unable to register iio device\n");
1745 goto err_pm_cleanup;
1746 }
1747
1748 return 0;
1749
1750 err_pm_cleanup:
1751 pm_runtime_dont_use_autosuspend(dev);
1752 pm_runtime_disable(dev);
1753 err_trigger_unregister:
1754 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1755 err_buffer_cleanup:
1756 iio_triggered_buffer_cleanup(indio_dev);
1757 err_disable_regulators:
1758 regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1759 data->regulators);
1760
1761 return ret;
1762 }
1763 EXPORT_SYMBOL_NS_GPL(bmc150_accel_core_probe, "IIO_BMC150");
1764
1765 void bmc150_accel_core_remove(struct device *dev)
1766 {
1767 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1768 struct bmc150_accel_data *data = iio_priv(indio_dev);
1769
1770 iio_device_unregister(indio_dev);
1771
1772 pm_runtime_disable(dev);
1773 pm_runtime_set_suspended(dev);
1774
1775 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1776
1777 iio_triggered_buffer_cleanup(indio_dev);
1778
1779 mutex_lock(&data->mutex);
1780 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1781 mutex_unlock(&data->mutex);
1782
1783 regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1784 data->regulators);
1785 }
1786 EXPORT_SYMBOL_NS_GPL(bmc150_accel_core_remove, "IIO_BMC150");
1787
1788 #ifdef CONFIG_PM_SLEEP
1789 static int bmc150_accel_suspend(struct device *dev)
1790 {
1791 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1792 struct bmc150_accel_data *data = iio_priv(indio_dev);
1793
1794 mutex_lock(&data->mutex);
1795 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1796 mutex_unlock(&data->mutex);
1797
1798 return 0;
1799 }
1800
1801 static int bmc150_accel_resume(struct device *dev)
1802 {
1803 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1804 struct bmc150_accel_data *data = iio_priv(indio_dev);
1805
1806 mutex_lock(&data->mutex);
1807 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1808 bmc150_accel_fifo_set_mode(data);
1809 mutex_unlock(&data->mutex);
1810
1811 if (data->resume_callback)
1812 data->resume_callback(dev);
1813
1814 return 0;
1815 }
1816 #endif
1817
1818 #ifdef CONFIG_PM
1819 static int bmc150_accel_runtime_suspend(struct device *dev)
1820 {
1821 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1822 struct bmc150_accel_data *data = iio_priv(indio_dev);
1823 int ret;
1824
1825 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1826 if (ret < 0)
1827 return -EAGAIN;
1828
1829 return 0;
1830 }
1831
1832 static int bmc150_accel_runtime_resume(struct device *dev)
1833 {
1834 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1835 struct bmc150_accel_data *data = iio_priv(indio_dev);
1836 int ret;
1837 int sleep_val;
1838
1839 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1840 if (ret < 0)
1841 return ret;
1842 ret = bmc150_accel_fifo_set_mode(data);
1843 if (ret < 0)
1844 return ret;
1845
1846 sleep_val = bmc150_accel_get_startup_times(data);
1847 if (sleep_val < 20)
1848 usleep_range(sleep_val * 1000, 20000);
1849 else
1850 msleep_interruptible(sleep_val);
1851
1852 return 0;
1853 }
1854 #endif
1855
1856 const struct dev_pm_ops bmc150_accel_pm_ops = {
1857 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1858 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1859 bmc150_accel_runtime_resume, NULL)
1860 };
1861 EXPORT_SYMBOL_NS_GPL(bmc150_accel_pm_ops, "IIO_BMC150");
1862
1863 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1864 MODULE_LICENSE("GPL v2");
1865 MODULE_DESCRIPTION("BMC150 accelerometer driver");
Kernel DRM miscellaneous fixes and cross-tree changes