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drm/client: Fix drm client endless Kconfig loop
[drm/drm-misc.git] / drivers / iio / adc / ad7173.c
blob8a0c931ca83a83ad6302d7e90e834e09837c2f52
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD717x and AD411x family SPI ADC driver
4 *
5 * Supported devices:
6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116
7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2
8 * AD7175-8/AD7176-2/AD7177-2
9 *
10 * Copyright (C) 2015, 2024 Analog Devices, Inc.
11 */
12
13 #include <linux/array_size.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitmap.h>
16 #include <linux/container_of.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/regmap.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/math64.h>
27 #include <linux/module.h>
28 #include <linux/mod_devicetable.h>
29 #include <linux/property.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/types.h>
35 #include <linux/units.h>
36
37 #include <linux/iio/buffer.h>
38 #include <linux/iio/iio.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41
42 #include <linux/iio/adc/ad_sigma_delta.h>
43
44 #define AD7173_REG_COMMS 0x00
45 #define AD7173_REG_ADC_MODE 0x01
46 #define AD7173_REG_INTERFACE_MODE 0x02
47 #define AD7173_REG_CRC 0x03
48 #define AD7173_REG_DATA 0x04
49 #define AD7173_REG_GPIO 0x06
50 #define AD7173_REG_ID 0x07
51 #define AD7173_REG_CH(x) (0x10 + (x))
52 #define AD7173_REG_SETUP(x) (0x20 + (x))
53 #define AD7173_REG_FILTER(x) (0x28 + (x))
54 #define AD7173_REG_OFFSET(x) (0x30 + (x))
55 #define AD7173_REG_GAIN(x) (0x38 + (x))
56
57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64)
58
59 #define AD7173_CH_ENABLE BIT(15)
60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)
61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)
62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)
63
64 #define AD7173_NO_AINS_PER_CHANNEL 2
65 #define AD7173_CH_ADDRESS(pos, neg) \
66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
68 #define AD7173_AIN_TEMP_POS 17
69 #define AD7173_AIN_TEMP_NEG 18
70 #define AD7173_AIN_POW_MON_POS 19
71 #define AD7173_AIN_POW_MON_NEG 20
72 #define AD7173_AIN_REF_POS 21
73 #define AD7173_AIN_REF_NEG 22
74
75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \
76 (x) == AD7173_AIN_REF_NEG)
77
78 #define AD7172_2_ID 0x00d0
79 #define AD7176_ID 0x0c90
80 #define AD7175_ID 0x0cd0
81 #define AD7175_2_ID 0x0cd0
82 #define AD7172_4_ID 0x2050
83 #define AD7173_ID 0x30d0
84 #define AD4111_ID AD7173_ID
85 #define AD4112_ID AD7173_ID
86 #define AD4114_ID AD7173_ID
87 #define AD4113_ID 0x31d0
88 #define AD4116_ID 0x34d0
89 #define AD4115_ID 0x38d0
90 #define AD7175_8_ID 0x3cd0
91 #define AD7177_ID 0x4fd0
92 #define AD7173_ID_MASK GENMASK(15, 4)
93
94 #define AD7173_ADC_MODE_REF_EN BIT(15)
95 #define AD7173_ADC_MODE_SING_CYC BIT(13)
96 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)
97 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)
98 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0
99 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1
100 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2
101 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3
102
103 #define AD7173_GPIO_PDSW BIT(14)
104 #define AD7173_GPIO_OP_EN2_3 BIT(13)
105 #define AD7173_GPIO_MUX_IO BIT(12)
106 #define AD7173_GPIO_SYNC_EN BIT(11)
107 #define AD7173_GPIO_ERR_EN BIT(10)
108 #define AD7173_GPIO_ERR_DAT BIT(9)
109 #define AD7173_GPIO_GP_DATA3 BIT(7)
110 #define AD7173_GPIO_GP_DATA2 BIT(6)
111 #define AD7173_GPIO_IP_EN1 BIT(5)
112 #define AD7173_GPIO_IP_EN0 BIT(4)
113 #define AD7173_GPIO_OP_EN1 BIT(3)
114 #define AD7173_GPIO_OP_EN0 BIT(2)
115 #define AD7173_GPIO_GP_DATA1 BIT(1)
116 #define AD7173_GPIO_GP_DATA0 BIT(0)
117
118 #define AD7173_GPO12_DATA(x) BIT((x) + 0)
119 #define AD7173_GPO23_DATA(x) BIT((x) + 4)
120 #define AD4111_GPO01_DATA(x) BIT((x) + 6)
121 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
122
123 #define AD7173_INTERFACE_DATA_STAT BIT(6)
124 #define AD7173_INTERFACE_DATA_STAT_EN(x) \
125 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
126
127 #define AD7173_SETUP_BIPOLAR BIT(12)
128 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)
129 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)
130
131 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)
132 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3
133 #define AD7173_SETUP_REF_SEL_INT_REF 0x2
134 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1
135 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0
136 #define AD7173_VOLTAGE_INT_REF_uV 2500000
137 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477
138 #define AD7177_ODR_START_VALUE 0x07
139 #define AD4111_SHUNT_RESISTOR_OHM 50
140 #define AD4111_DIVIDER_RATIO 10
141 #define AD4111_CURRENT_CHAN_CUTOFF 16
142 #define AD4111_VINCOM_INPUT 0x10
143
144 /* pin < num_voltage_in is a normal voltage input */
145 /* pin >= num_voltage_in_div is a voltage input without a divider */
146 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \
147 (pin2) < st->info->num_voltage_in && \
148 (pin2) >= st->info->num_voltage_in_div)
149
150 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0)
151 #define AD7173_MAX_CONFIGS 8
152
153 struct ad7173_device_info {
154 const unsigned int *sinc5_data_rates;
155 unsigned int num_sinc5_data_rates;
156 unsigned int odr_start_value;
157 /*
158 * AD4116 has both inputs with a voltage divider and without.
159 * These inputs cannot be mixed in the channel configuration.
160 * Does not include the VINCOM input.
161 */
162 unsigned int num_voltage_in_div;
163 unsigned int num_channels;
164 unsigned int num_configs;
165 unsigned int num_voltage_in;
166 unsigned int clock;
167 unsigned int id;
168 char *name;
169 bool has_current_inputs;
170 bool has_vincom_input;
171 bool has_temp;
172 /* ((AVDD1 − AVSS)/5) */
173 bool has_pow_supply_monitoring;
174 bool data_reg_only_16bit;
175 bool has_input_buf;
176 bool has_int_ref;
177 bool has_ref2;
178 bool higher_gpio_bits;
179 u8 num_gpios;
180 };
181
182 struct ad7173_channel_config {
183 u8 cfg_slot;
184 bool live;
185
186 /* Following fields are used to compare equality. */
187 struct_group(config_props,
188 bool bipolar;
189 bool input_buf;
190 u8 odr;
191 u8 ref_sel;
192 );
193 };
194
195 struct ad7173_channel {
196 unsigned int chan_reg;
197 unsigned int ain;
198 struct ad7173_channel_config cfg;
199 };
200
201 struct ad7173_state {
202 struct ad_sigma_delta sd;
203 const struct ad7173_device_info *info;
204 struct ad7173_channel *channels;
205 struct regulator_bulk_data regulators[3];
206 unsigned int adc_mode;
207 unsigned int interface_mode;
208 unsigned int num_channels;
209 struct ida cfg_slots_status;
210 unsigned long long config_usage_counter;
211 unsigned long long *config_cnts;
212 struct clk *ext_clk;
213 struct clk_hw int_clk_hw;
214 #if IS_ENABLED(CONFIG_GPIOLIB)
215 struct regmap *reg_gpiocon_regmap;
216 struct gpio_regmap *gpio_regmap;
217 #endif
218 };
219
220 static unsigned int ad4115_sinc5_data_rates[] = {
221 24845000, 24845000, 20725000, 20725000, /* 0-3 */
222 15564000, 13841000, 10390000, 10390000, /* 4-7 */
223 4994000, 2499000, 1000000, 500000, /* 8-11 */
224 395500, 200000, 100000, 59890, /* 12-15 */
225 49920, 20000, 16660, 10000, /* 16-19 */
226 5000, 2500, 2500, /* 20-22 */
227 };
228
229 static unsigned int ad4116_sinc5_data_rates[] = {
230 12422360, 12422360, 12422360, 12422360, /* 0-3 */
231 10362690, 10362690, 7782100, 6290530, /* 4-7 */
232 5194800, 2496900, 1007600, 499900, /* 8-11 */
233 390600, 200300, 100000, 59750, /* 12-15 */
234 49840, 20000, 16650, 10000, /* 16-19 */
235 5000, 2500, 1250, /* 20-22 */
236 };
237
238 static const unsigned int ad7173_sinc5_data_rates[] = {
239 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */
240 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */
241 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */
242 };
243
244 static const unsigned int ad7175_sinc5_data_rates[] = {
245 50000000, 41667000, 31250000, 27778000, /* 0-3 */
246 20833000, 17857000, 12500000, 10000000, /* 4-7 */
247 5000000, 2500000, 1000000, 500000, /* 8-11 */
248 397500, 200000, 100000, 59920, /* 12-15 */
249 49960, 20000, 16666, 10000, /* 16-19 */
250 5000, /* 20 */
251 };
252
253 static unsigned int ad4111_current_channel_config[] = {
254 /* Ain sel: pos neg */
255 0x1E8, /* 15:IIN0+ 8:IIN0− */
256 0x1C9, /* 14:IIN1+ 9:IIN1− */
257 0x1AA, /* 13:IIN2+ 10:IIN2− */
258 0x18B, /* 12:IIN3+ 11:IIN3− */
259 };
260
261 static const struct ad7173_device_info ad4111_device_info = {
262 .name = "ad4111",
263 .id = AD4111_ID,
264 .num_voltage_in_div = 8,
265 .num_channels = 16,
266 .num_configs = 8,
267 .num_voltage_in = 8,
268 .num_gpios = 2,
269 .higher_gpio_bits = true,
270 .has_temp = true,
271 .has_vincom_input = true,
272 .has_input_buf = true,
273 .has_current_inputs = true,
274 .has_int_ref = true,
275 .clock = 2 * HZ_PER_MHZ,
276 .sinc5_data_rates = ad7173_sinc5_data_rates,
277 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
278 };
279
280 static const struct ad7173_device_info ad4112_device_info = {
281 .name = "ad4112",
282 .id = AD4112_ID,
283 .num_voltage_in_div = 8,
284 .num_channels = 16,
285 .num_configs = 8,
286 .num_voltage_in = 8,
287 .num_gpios = 2,
288 .higher_gpio_bits = true,
289 .has_vincom_input = true,
290 .has_temp = true,
291 .has_input_buf = true,
292 .has_current_inputs = true,
293 .has_int_ref = true,
294 .clock = 2 * HZ_PER_MHZ,
295 .sinc5_data_rates = ad7173_sinc5_data_rates,
296 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
297 };
298
299 static const struct ad7173_device_info ad4113_device_info = {
300 .name = "ad4113",
301 .id = AD4113_ID,
302 .num_voltage_in_div = 8,
303 .num_channels = 16,
304 .num_configs = 8,
305 .num_voltage_in = 8,
306 .num_gpios = 2,
307 .data_reg_only_16bit = true,
308 .higher_gpio_bits = true,
309 .has_vincom_input = true,
310 .has_input_buf = true,
311 .has_int_ref = true,
312 .clock = 2 * HZ_PER_MHZ,
313 .sinc5_data_rates = ad7173_sinc5_data_rates,
314 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
315 };
316
317 static const struct ad7173_device_info ad4114_device_info = {
318 .name = "ad4114",
319 .id = AD4114_ID,
320 .num_voltage_in_div = 16,
321 .num_channels = 16,
322 .num_configs = 8,
323 .num_voltage_in = 16,
324 .num_gpios = 4,
325 .has_vincom_input = true,
326 .has_temp = true,
327 .has_input_buf = true,
328 .has_int_ref = true,
329 .clock = 2 * HZ_PER_MHZ,
330 .sinc5_data_rates = ad7173_sinc5_data_rates,
331 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
332 };
333
334 static const struct ad7173_device_info ad4115_device_info = {
335 .name = "ad4115",
336 .id = AD4115_ID,
337 .num_voltage_in_div = 16,
338 .num_channels = 16,
339 .num_configs = 8,
340 .num_voltage_in = 16,
341 .num_gpios = 4,
342 .has_vincom_input = true,
343 .has_temp = true,
344 .has_input_buf = true,
345 .has_int_ref = true,
346 .clock = 8 * HZ_PER_MHZ,
347 .sinc5_data_rates = ad4115_sinc5_data_rates,
348 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates),
349 };
350
351 static const struct ad7173_device_info ad4116_device_info = {
352 .name = "ad4116",
353 .id = AD4116_ID,
354 .num_voltage_in_div = 11,
355 .num_channels = 16,
356 .num_configs = 8,
357 .num_voltage_in = 16,
358 .num_gpios = 4,
359 .has_vincom_input = true,
360 .has_temp = true,
361 .has_input_buf = true,
362 .has_int_ref = true,
363 .clock = 4 * HZ_PER_MHZ,
364 .sinc5_data_rates = ad4116_sinc5_data_rates,
365 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates),
366 };
367
368 static const struct ad7173_device_info ad7172_2_device_info = {
369 .name = "ad7172-2",
370 .id = AD7172_2_ID,
371 .num_voltage_in = 5,
372 .num_channels = 4,
373 .num_configs = 4,
374 .num_gpios = 2,
375 .has_temp = true,
376 .has_input_buf = true,
377 .has_int_ref = true,
378 .has_pow_supply_monitoring = true,
379 .clock = 2 * HZ_PER_MHZ,
380 .sinc5_data_rates = ad7173_sinc5_data_rates,
381 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
382 };
383
384 static const struct ad7173_device_info ad7172_4_device_info = {
385 .name = "ad7172-4",
386 .id = AD7172_4_ID,
387 .num_voltage_in = 9,
388 .num_channels = 8,
389 .num_configs = 8,
390 .num_gpios = 4,
391 .has_input_buf = true,
392 .has_ref2 = true,
393 .has_pow_supply_monitoring = true,
394 .clock = 2 * HZ_PER_MHZ,
395 .sinc5_data_rates = ad7173_sinc5_data_rates,
396 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
397 };
398
399 static const struct ad7173_device_info ad7173_8_device_info = {
400 .name = "ad7173-8",
401 .id = AD7173_ID,
402 .num_voltage_in = 17,
403 .num_channels = 16,
404 .num_configs = 8,
405 .num_gpios = 4,
406 .has_temp = true,
407 .has_input_buf = true,
408 .has_int_ref = true,
409 .has_ref2 = true,
410 .clock = 2 * HZ_PER_MHZ,
411 .sinc5_data_rates = ad7173_sinc5_data_rates,
412 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
413 };
414
415 static const struct ad7173_device_info ad7175_2_device_info = {
416 .name = "ad7175-2",
417 .id = AD7175_2_ID,
418 .num_voltage_in = 5,
419 .num_channels = 4,
420 .num_configs = 4,
421 .num_gpios = 2,
422 .has_temp = true,
423 .has_input_buf = true,
424 .has_int_ref = true,
425 .has_pow_supply_monitoring = true,
426 .clock = 16 * HZ_PER_MHZ,
427 .sinc5_data_rates = ad7175_sinc5_data_rates,
428 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
429 };
430
431 static const struct ad7173_device_info ad7175_8_device_info = {
432 .name = "ad7175-8",
433 .id = AD7175_8_ID,
434 .num_voltage_in = 17,
435 .num_channels = 16,
436 .num_configs = 8,
437 .num_gpios = 4,
438 .has_temp = true,
439 .has_input_buf = true,
440 .has_int_ref = true,
441 .has_ref2 = true,
442 .has_pow_supply_monitoring = true,
443 .clock = 16 * HZ_PER_MHZ,
444 .sinc5_data_rates = ad7175_sinc5_data_rates,
445 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
446 };
447
448 static const struct ad7173_device_info ad7176_2_device_info = {
449 .name = "ad7176-2",
450 .id = AD7176_ID,
451 .num_voltage_in = 5,
452 .num_channels = 4,
453 .num_configs = 4,
454 .num_gpios = 2,
455 .has_int_ref = true,
456 .clock = 16 * HZ_PER_MHZ,
457 .sinc5_data_rates = ad7175_sinc5_data_rates,
458 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
459 };
460
461 static const struct ad7173_device_info ad7177_2_device_info = {
462 .name = "ad7177-2",
463 .id = AD7177_ID,
464 .num_voltage_in = 5,
465 .num_channels = 4,
466 .num_configs = 4,
467 .num_gpios = 2,
468 .has_temp = true,
469 .has_input_buf = true,
470 .has_int_ref = true,
471 .has_pow_supply_monitoring = true,
472 .clock = 16 * HZ_PER_MHZ,
473 .odr_start_value = AD7177_ODR_START_VALUE,
474 .sinc5_data_rates = ad7175_sinc5_data_rates,
475 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
476 };
477
478 static const char *const ad7173_ref_sel_str[] = {
479 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref",
480 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2",
481 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss",
482 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
483 };
484
485 static const char *const ad7173_clk_sel[] = {
486 "ext-clk", "xtal"
487 };
488
489 #if IS_ENABLED(CONFIG_GPIOLIB)
490
491 static const struct regmap_range ad7173_range_gpio[] = {
492 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
493 };
494
495 static const struct regmap_access_table ad7173_access_table = {
496 .yes_ranges = ad7173_range_gpio,
497 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
498 };
499
500 static const struct regmap_config ad7173_regmap_config = {
501 .reg_bits = 8,
502 .val_bits = 16,
503 .rd_table = &ad7173_access_table,
504 .wr_table = &ad7173_access_table,
505 .read_flag_mask = BIT(6),
506 };
507
508 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
509 unsigned int offset, unsigned int *reg,
510 unsigned int *mask)
511 {
512 *mask = AD7173_GPO_DATA(offset);
513 *reg = base;
514 return 0;
515 }
516
517 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
518 unsigned int offset, unsigned int *reg,
519 unsigned int *mask)
520 {
521 *mask = AD4111_GPO01_DATA(offset);
522 *reg = base;
523 return 0;
524 }
525
526 static void ad7173_gpio_disable(void *data)
527 {
528 struct ad7173_state *st = data;
529 unsigned int mask;
530
531 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
532 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
533 }
534
535 static int ad7173_gpio_init(struct ad7173_state *st)
536 {
537 struct gpio_regmap_config gpio_regmap = {};
538 struct device *dev = &st->sd.spi->dev;
539 unsigned int mask;
540 int ret;
541
542 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
543 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
544 if (ret)
545 return dev_err_probe(dev, ret, "Unable to init regmap\n");
546
547 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
548 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
549
550 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
551 if (ret)
552 return ret;
553
554 gpio_regmap.parent = dev;
555 gpio_regmap.regmap = st->reg_gpiocon_regmap;
556 gpio_regmap.ngpio = st->info->num_gpios;
557 gpio_regmap.reg_set_base = AD7173_REG_GPIO;
558 if (st->info->higher_gpio_bits)
559 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate;
560 else
561 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
562
563 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
564 ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
565 if (ret)
566 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
567
568 return 0;
569 }
570 #else
571 static int ad7173_gpio_init(struct ad7173_state *st)
572 {
573 return 0;
574 }
575 #endif /* CONFIG_GPIOLIB */
576
577 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
578 {
579 return container_of(sd, struct ad7173_state, sd);
580 }
581
582 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
583 {
584 return container_of(hw, struct ad7173_state, int_clk_hw);
585 }
586
587 static void ad7173_ida_destroy(void *data)
588 {
589 struct ad7173_state *st = data;
590
591 ida_destroy(&st->cfg_slots_status);
592 }
593
594 static void ad7173_reset_usage_cnts(struct ad7173_state *st)
595 {
596 memset64(st->config_cnts, 0, st->info->num_configs);
597 st->config_usage_counter = 0;
598 }
599
600 static struct ad7173_channel_config *
601 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
602 {
603 struct ad7173_channel_config *cfg_aux;
604 ptrdiff_t cmp_size;
605 int i;
606
607 cmp_size = sizeof_field(struct ad7173_channel_config, config_props);
608 for (i = 0; i < st->num_channels; i++) {
609 cfg_aux = &st->channels[i].cfg;
610
611 if (cfg_aux->live &&
612 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
613 return cfg_aux;
614 }
615 return NULL;
616 }
617
618 /* Could be replaced with a generic LRU implementation */
619 static int ad7173_free_config_slot_lru(struct ad7173_state *st)
620 {
621 int i, lru_position = 0;
622
623 for (i = 1; i < st->info->num_configs; i++)
624 if (st->config_cnts[i] < st->config_cnts[lru_position])
625 lru_position = i;
626
627 for (i = 0; i < st->num_channels; i++)
628 if (st->channels[i].cfg.cfg_slot == lru_position)
629 st->channels[i].cfg.live = false;
630
631 ida_free(&st->cfg_slots_status, lru_position);
632 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
633 }
634
635 /* Could be replaced with a generic LRU implementation */
636 static int ad7173_load_config(struct ad7173_state *st,
637 struct ad7173_channel_config *cfg)
638 {
639 unsigned int config;
640 int free_cfg_slot, ret;
641
642 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
643 st->info->num_configs - 1, GFP_KERNEL);
644 if (free_cfg_slot < 0)
645 free_cfg_slot = ad7173_free_config_slot_lru(st);
646
647 cfg->cfg_slot = free_cfg_slot;
648 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
649
650 if (cfg->bipolar)
651 config |= AD7173_SETUP_BIPOLAR;
652
653 if (cfg->input_buf)
654 config |= AD7173_SETUP_AIN_BUF_MASK;
655
656 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
657 if (ret)
658 return ret;
659
660 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
661 AD7173_FILTER_ODR0_MASK & cfg->odr);
662 }
663
664 static int ad7173_config_channel(struct ad7173_state *st, int addr)
665 {
666 struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
667 struct ad7173_channel_config *live_cfg;
668 int ret;
669
670 if (!cfg->live) {
671 live_cfg = ad7173_find_live_config(st, cfg);
672 if (live_cfg) {
673 cfg->cfg_slot = live_cfg->cfg_slot;
674 } else {
675 ret = ad7173_load_config(st, cfg);
676 if (ret)
677 return ret;
678 cfg->live = true;
679 }
680 }
681
682 if (st->config_usage_counter == U64_MAX)
683 ad7173_reset_usage_cnts(st);
684
685 st->config_usage_counter++;
686 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
687
688 return 0;
689 }
690
691 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
692 {
693 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
694 unsigned int val;
695 int ret;
696
697 ret = ad7173_config_channel(st, channel);
698 if (ret)
699 return ret;
700
701 val = AD7173_CH_ENABLE |
702 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
703 st->channels[channel].ain;
704
705 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
706 }
707
708 static int ad7173_set_mode(struct ad_sigma_delta *sd,
709 enum ad_sigma_delta_mode mode)
710 {
711 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
712
713 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
714 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
715
716 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
717 }
718
719 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
720 {
721 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
722 unsigned int interface_mode = st->interface_mode;
723 int ret;
724
725 interface_mode &= ~AD7173_INTERFACE_DATA_STAT;
726 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
727 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
728 if (ret)
729 return ret;
730
731 st->interface_mode = interface_mode;
732
733 return 0;
734 }
735
736 static int ad7173_disable_all(struct ad_sigma_delta *sd)
737 {
738 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
739 int ret;
740 int i;
741
742 for (i = 0; i < st->num_channels; i++) {
743 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
744 if (ret < 0)
745 return ret;
746 }
747
748 return 0;
749 }
750
751 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
752 {
753 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0);
754 }
755
756 static struct ad_sigma_delta_info ad7173_sigma_delta_info = {
757 .set_channel = ad7173_set_channel,
758 .append_status = ad7173_append_status,
759 .disable_all = ad7173_disable_all,
760 .disable_one = ad7173_disable_one,
761 .set_mode = ad7173_set_mode,
762 .has_registers = true,
763 .addr_shift = 0,
764 .read_mask = BIT(6),
765 .status_ch_mask = GENMASK(3, 0),
766 .data_reg = AD7173_REG_DATA,
767 };
768
769 static int ad7173_setup(struct iio_dev *indio_dev)
770 {
771 struct ad7173_state *st = iio_priv(indio_dev);
772 struct device *dev = &st->sd.spi->dev;
773 u8 buf[AD7173_RESET_LENGTH];
774 unsigned int id;
775 int ret;
776
777 /* reset the serial interface */
778 memset(buf, 0xff, AD7173_RESET_LENGTH);
779 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
780 if (ret < 0)
781 return ret;
782
783 /* datasheet recommends a delay of at least 500us after reset */
784 fsleep(500);
785
786 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
787 if (ret)
788 return ret;
789
790 id &= AD7173_ID_MASK;
791 if (id != st->info->id)
792 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
793 id, st->info->id);
794
795 st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
796 st->interface_mode = 0x0;
797
798 st->config_usage_counter = 0;
799 st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
800 sizeof(*st->config_cnts), GFP_KERNEL);
801 if (!st->config_cnts)
802 return -ENOMEM;
803
804 /* All channels are enabled by default after a reset */
805 return ad7173_disable_all(&st->sd);
806 }
807
808 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
809 u8 reference_select)
810 {
811 int vref;
812
813 switch (reference_select) {
814 case AD7173_SETUP_REF_SEL_EXT_REF:
815 vref = regulator_get_voltage(st->regulators[0].consumer);
816 break;
817
818 case AD7173_SETUP_REF_SEL_EXT_REF2:
819 vref = regulator_get_voltage(st->regulators[1].consumer);
820 break;
821
822 case AD7173_SETUP_REF_SEL_INT_REF:
823 vref = AD7173_VOLTAGE_INT_REF_uV;
824 break;
825
826 case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
827 vref = regulator_get_voltage(st->regulators[2].consumer);
828 break;
829
830 default:
831 return -EINVAL;
832 }
833
834 if (vref < 0)
835 return vref;
836
837 return vref / (MICRO / MILLI);
838 }
839
840 static int ad7173_read_raw(struct iio_dev *indio_dev,
841 struct iio_chan_spec const *chan,
842 int *val, int *val2, long info)
843 {
844 struct ad7173_state *st = iio_priv(indio_dev);
845 struct ad7173_channel *ch = &st->channels[chan->address];
846 unsigned int reg;
847 u64 temp;
848 int ret;
849
850 switch (info) {
851 case IIO_CHAN_INFO_RAW:
852 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
853 if (ret < 0)
854 return ret;
855
856 return IIO_VAL_INT;
857 case IIO_CHAN_INFO_SCALE:
858
859 switch (chan->type) {
860 case IIO_TEMP:
861 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
862 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
863 *val = temp;
864 *val2 = chan->scan_type.realbits;
865 return IIO_VAL_FRACTIONAL_LOG2;
866 case IIO_VOLTAGE:
867 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
868 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
869
870 if (chan->channel < st->info->num_voltage_in_div)
871 *val *= AD4111_DIVIDER_RATIO;
872 return IIO_VAL_FRACTIONAL_LOG2;
873 case IIO_CURRENT:
874 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
875 *val /= AD4111_SHUNT_RESISTOR_OHM;
876 *val2 = chan->scan_type.realbits - ch->cfg.bipolar;
877 return IIO_VAL_FRACTIONAL_LOG2;
878 default:
879 return -EINVAL;
880 }
881 case IIO_CHAN_INFO_OFFSET:
882
883 switch (chan->type) {
884 case IIO_TEMP:
885 /* 0 Kelvin -> raw sample */
886 temp = -ABSOLUTE_ZERO_MILLICELSIUS;
887 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C;
888 temp <<= chan->scan_type.realbits;
889 temp = DIV_U64_ROUND_CLOSEST(temp,
890 AD7173_VOLTAGE_INT_REF_uV *
891 MILLI);
892 *val = -temp;
893 return IIO_VAL_INT;
894 case IIO_VOLTAGE:
895 case IIO_CURRENT:
896 *val = -BIT(chan->scan_type.realbits - 1);
897 return IIO_VAL_INT;
898 default:
899 return -EINVAL;
900 }
901 case IIO_CHAN_INFO_SAMP_FREQ:
902 reg = st->channels[chan->address].cfg.odr;
903
904 *val = st->info->sinc5_data_rates[reg] / MILLI;
905 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
906
907 return IIO_VAL_INT_PLUS_MICRO;
908 default:
909 return -EINVAL;
910 }
911 }
912
913 static int ad7173_write_raw(struct iio_dev *indio_dev,
914 struct iio_chan_spec const *chan,
915 int val, int val2, long info)
916 {
917 struct ad7173_state *st = iio_priv(indio_dev);
918 struct ad7173_channel_config *cfg;
919 unsigned int freq, i;
920 int ret;
921
922 ret = iio_device_claim_direct_mode(indio_dev);
923 if (ret)
924 return ret;
925
926 switch (info) {
927 /*
928 * This attribute sets the sampling frequency for each channel individually.
929 * There are no issues for raw or buffered reads of an individual channel.
930 *
931 * When multiple channels are enabled in buffered mode, the effective
932 * sampling rate of a channel is lowered in correlation to the number
933 * of channels enabled and the sampling rate of the other channels.
934 *
935 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps
936 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3
937 * will take 100ms each.
938 *
939 * This will cause the reading of CH1 to be actually done once every
940 * 200.16ms, an effective rate of 4.99sps.
941 */
942 case IIO_CHAN_INFO_SAMP_FREQ:
943 freq = val * MILLI + val2 / MILLI;
944 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++)
945 if (freq >= st->info->sinc5_data_rates[i])
946 break;
947
948 cfg = &st->channels[chan->address].cfg;
949 cfg->odr = i;
950 cfg->live = false;
951 break;
952
953 default:
954 ret = -EINVAL;
955 break;
956 }
957
958 iio_device_release_direct_mode(indio_dev);
959 return ret;
960 }
961
962 static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
963 const unsigned long *scan_mask)
964 {
965 struct ad7173_state *st = iio_priv(indio_dev);
966 int i, ret;
967
968 for (i = 0; i < indio_dev->num_channels; i++) {
969 if (test_bit(i, scan_mask))
970 ret = ad7173_set_channel(&st->sd, i);
971 else
972 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
973 if (ret < 0)
974 return ret;
975 }
976
977 return 0;
978 }
979
980 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
981 unsigned int writeval, unsigned int *readval)
982 {
983 struct ad7173_state *st = iio_priv(indio_dev);
984 u8 reg_size;
985
986 if (reg == AD7173_REG_COMMS)
987 reg_size = 1;
988 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
989 reg >= AD7173_REG_OFFSET(0))
990 reg_size = 3;
991 else
992 reg_size = 2;
993
994 if (readval)
995 return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
996
997 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
998 }
999
1000 static const struct iio_info ad7173_info = {
1001 .read_raw = &ad7173_read_raw,
1002 .write_raw = &ad7173_write_raw,
1003 .debugfs_reg_access = &ad7173_debug_reg_access,
1004 .validate_trigger = ad_sd_validate_trigger,
1005 .update_scan_mode = ad7173_update_scan_mode,
1006 };
1007
1008 static const struct iio_scan_type ad4113_scan_type = {
1009 .sign = 'u',
1010 .realbits = 16,
1011 .storagebits = 16,
1012 .endianness = IIO_BE,
1013 };
1014
1015 static const struct iio_chan_spec ad7173_channel_template = {
1016 .type = IIO_VOLTAGE,
1017 .indexed = 1,
1018 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1019 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
1020 .scan_type = {
1021 .sign = 'u',
1022 .realbits = 24,
1023 .storagebits = 32,
1024 .endianness = IIO_BE,
1025 },
1026 };
1027
1028 static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
1029 .type = IIO_TEMP,
1030 .channel = AD7173_AIN_TEMP_POS,
1031 .channel2 = AD7173_AIN_TEMP_NEG,
1032 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1033 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1034 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1035 .scan_type = {
1036 .sign = 'u',
1037 .realbits = 24,
1038 .storagebits = 32,
1039 .endianness = IIO_BE,
1040 },
1041 };
1042
1043 static void ad7173_disable_regulators(void *data)
1044 {
1045 struct ad7173_state *st = data;
1046
1047 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1048 }
1049
1050 static void ad7173_clk_disable_unprepare(void *clk)
1051 {
1052 clk_disable_unprepare(clk);
1053 }
1054
1055 static unsigned long ad7173_sel_clk(struct ad7173_state *st,
1056 unsigned int clk_sel)
1057 {
1058 int ret;
1059
1060 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK;
1061 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
1062 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
1063
1064 return ret;
1065 }
1066
1067 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
1068 unsigned long parent_rate)
1069 {
1070 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1071
1072 return st->info->clock / HZ_PER_KHZ;
1073 }
1074
1075 static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
1076 {
1077 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1078 u32 clk_sel;
1079
1080 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
1081 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
1082 }
1083
1084 static int ad7173_clk_output_prepare(struct clk_hw *hw)
1085 {
1086 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1087
1088 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
1089 }
1090
1091 static void ad7173_clk_output_unprepare(struct clk_hw *hw)
1092 {
1093 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1094
1095 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
1096 }
1097
1098 static const struct clk_ops ad7173_int_clk_ops = {
1099 .recalc_rate = ad7173_clk_recalc_rate,
1100 .is_enabled = ad7173_clk_output_is_enabled,
1101 .prepare = ad7173_clk_output_prepare,
1102 .unprepare = ad7173_clk_output_unprepare,
1103 };
1104
1105 static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
1106 {
1107 struct ad7173_state *st = iio_priv(indio_dev);
1108 struct device *dev = indio_dev->dev.parent;
1109 struct fwnode_handle *fwnode = dev_fwnode(dev);
1110 struct clk_init_data init = {};
1111 int ret;
1112
1113 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1114 return 0;
1115
1116 init.name = fwnode_get_name(fwnode);
1117 init.ops = &ad7173_int_clk_ops;
1118
1119 st->int_clk_hw.init = &init;
1120 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1121 if (ret)
1122 return ret;
1123
1124 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1125 &st->int_clk_hw);
1126 }
1127
1128 static int ad4111_validate_current_ain(struct ad7173_state *st,
1129 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])
1130 {
1131 struct device *dev = &st->sd.spi->dev;
1132
1133 if (!st->info->has_current_inputs)
1134 return dev_err_probe(dev, -EINVAL,
1135 "Model %s does not support current channels\n",
1136 st->info->name);
1137
1138 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config))
1139 return dev_err_probe(dev, -EINVAL,
1140 "For current channels single-channel must be <[0-3]>\n");
1141
1142 return 0;
1143 }
1144
1145 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st,
1146 unsigned int ain0, unsigned int ain1)
1147 {
1148 struct device *dev = &st->sd.spi->dev;
1149 bool special_input0, special_input1;
1150
1151 /* (AVDD1-AVSS)/5 power supply monitoring */
1152 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG &&
1153 st->info->has_pow_supply_monitoring)
1154 return 0;
1155
1156 special_input0 = AD7173_IS_REF_INPUT(ain0) ||
1157 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1158 special_input1 = AD7173_IS_REF_INPUT(ain1) ||
1159 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1160
1161 if ((ain0 >= st->info->num_voltage_in && !special_input0) ||
1162 (ain1 >= st->info->num_voltage_in && !special_input1)) {
1163 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT)
1164 return dev_err_probe(dev, -EINVAL,
1165 "VINCOM not supported for %s\n", st->info->name);
1166
1167 return dev_err_probe(dev, -EINVAL,
1168 "Input pin number out of range for pair (%d %d).\n",
1169 ain0, ain1);
1170 }
1171
1172 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) ||
1173 AD4111_IS_VINCOM_MISMATCH(ain1, ain0))
1174 return dev_err_probe(dev, -EINVAL,
1175 "VINCOM must be paired with inputs having divider.\n");
1176
1177 if (!special_input0 && !special_input1 &&
1178 ((ain0 >= st->info->num_voltage_in_div) !=
1179 (ain1 >= st->info->num_voltage_in_div)))
1180 return dev_err_probe(dev, -EINVAL,
1181 "Both inputs must either have a voltage divider or not have: (%d %d).\n",
1182 ain0, ain1);
1183
1184 return 0;
1185 }
1186
1187 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel)
1188 {
1189 struct device *dev = &st->sd.spi->dev;
1190 int ret;
1191
1192 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref)
1193 return dev_err_probe(dev, -EINVAL,
1194 "Internal reference is not available on current model.\n");
1195
1196 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2)
1197 return dev_err_probe(dev, -EINVAL,
1198 "External reference 2 is not available on current model.\n");
1199
1200 ret = ad7173_get_ref_voltage_milli(st, ref_sel);
1201 if (ret < 0)
1202 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1203 ref_sel);
1204
1205 return 0;
1206 }
1207
1208 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
1209 {
1210 struct ad7173_channel *chans_st_arr, *chan_st_priv;
1211 struct ad7173_state *st = iio_priv(indio_dev);
1212 struct device *dev = indio_dev->dev.parent;
1213 struct iio_chan_spec *chan_arr, *chan;
1214 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0;
1215 int ref_sel, ret, num_channels;
1216
1217 num_channels = device_get_child_node_count(dev);
1218
1219 if (st->info->has_temp)
1220 num_channels++;
1221
1222 if (num_channels == 0)
1223 return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1224
1225 if (num_channels > st->info->num_channels)
1226 return dev_err_probe(dev, -EINVAL,
1227 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n",
1228 st->info->num_channels);
1229
1230 indio_dev->num_channels = num_channels;
1231 st->num_channels = num_channels;
1232
1233 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
1234 st->num_channels, GFP_KERNEL);
1235 if (!chan_arr)
1236 return -ENOMEM;
1237
1238 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
1239 GFP_KERNEL);
1240 if (!chans_st_arr)
1241 return -ENOMEM;
1242
1243 indio_dev->channels = chan_arr;
1244 st->channels = chans_st_arr;
1245
1246 if (st->info->has_temp) {
1247 chan_arr[chan_index] = ad7173_temp_iio_channel_template;
1248 chan_st_priv = &chans_st_arr[chan_index];
1249 chan_st_priv->ain =
1250 AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
1251 chan_arr[chan_index].channel2);
1252 chan_st_priv->cfg.bipolar = false;
1253 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1254 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1255 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1256 if (st->info->data_reg_only_16bit)
1257 chan_arr[chan_index].scan_type = ad4113_scan_type;
1258
1259 chan_index++;
1260 }
1261
1262 device_for_each_child_node_scoped(dev, child) {
1263 bool is_current_chan = false;
1264
1265 chan = &chan_arr[chan_index];
1266 *chan = ad7173_channel_template;
1267 chan_st_priv = &chans_st_arr[chan_index];
1268 ret = fwnode_property_read_u32_array(child, "diff-channels",
1269 ain, ARRAY_SIZE(ain));
1270 if (ret) {
1271 ret = fwnode_property_read_u32(child, "single-channel",
1272 ain);
1273 if (ret)
1274 return dev_err_probe(dev, ret,
1275 "Channel must define one of diff-channels or single-channel.\n");
1276
1277 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel");
1278 } else {
1279 chan->differential = true;
1280 }
1281
1282 if (is_current_chan) {
1283 ret = ad4111_validate_current_ain(st, ain);
1284 if (ret)
1285 return ret;
1286 } else {
1287 if (!chan->differential) {
1288 ret = fwnode_property_read_u32(child,
1289 "common-mode-channel", ain + 1);
1290 if (ret)
1291 return dev_err_probe(dev, ret,
1292 "common-mode-channel must be defined for single-ended channels.\n");
1293 }
1294 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]);
1295 if (ret)
1296 return ret;
1297 }
1298
1299 ret = fwnode_property_match_property_string(child,
1300 "adi,reference-select",
1301 ad7173_ref_sel_str,
1302 ARRAY_SIZE(ad7173_ref_sel_str));
1303 if (ret < 0)
1304 ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1305 else
1306 ref_sel = ret;
1307
1308 ret = ad7173_validate_reference(st, ref_sel);
1309 if (ret)
1310 return ret;
1311
1312 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
1313 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1314 chan_st_priv->cfg.ref_sel = ref_sel;
1315
1316 chan->address = chan_index;
1317 chan->scan_index = chan_index;
1318 chan->channel = ain[0];
1319 chan_st_priv->chan_reg = chan_index;
1320 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1321 chan_st_priv->cfg.odr = 0;
1322
1323 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
1324 if (chan_st_priv->cfg.bipolar)
1325 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
1326
1327 if (is_current_chan) {
1328 chan->type = IIO_CURRENT;
1329 chan->differential = false;
1330 chan->channel2 = 0;
1331 chan_st_priv->ain = ad4111_current_channel_config[ain[0]];
1332 } else {
1333 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1334 chan->channel2 = ain[1];
1335 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
1336 }
1337
1338 if (st->info->data_reg_only_16bit)
1339 chan_arr[chan_index].scan_type = ad4113_scan_type;
1340
1341 chan_index++;
1342 }
1343 return 0;
1344 }
1345
1346 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
1347 {
1348 struct ad7173_state *st = iio_priv(indio_dev);
1349 struct device *dev = indio_dev->dev.parent;
1350 int ret;
1351
1352 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
1353 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
1354 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
1355
1356 /*
1357 * If a regulator is not available, it will be set to a dummy regulator.
1358 * Each channel reference is checked with regulator_get_voltage() before
1359 * setting attributes so if any channel uses a dummy supply the driver
1360 * probe will fail.
1361 */
1362 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1363 st->regulators);
1364 if (ret)
1365 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1366
1367 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1368 if (ret)
1369 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1370
1371 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
1372 if (ret)
1373 return dev_err_probe(dev, ret,
1374 "Failed to add regulators disable action\n");
1375
1376 ret = device_property_match_property_string(dev, "clock-names",
1377 ad7173_clk_sel,
1378 ARRAY_SIZE(ad7173_clk_sel));
1379 if (ret < 0) {
1380 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1381 AD7173_ADC_MODE_CLOCKSEL_INT);
1382 ad7173_register_clk_provider(indio_dev);
1383 } else {
1384 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1385 AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
1386 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]);
1387 if (IS_ERR(st->ext_clk))
1388 return dev_err_probe(dev, PTR_ERR(st->ext_clk),
1389 "Failed to get external clock\n");
1390
1391 ret = clk_prepare_enable(st->ext_clk);
1392 if (ret)
1393 return dev_err_probe(dev, ret,
1394 "Failed to enable external clock\n");
1395
1396 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare,
1397 st->ext_clk);
1398 if (ret)
1399 return ret;
1400 }
1401
1402 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy");
1403 if (ret < 0)
1404 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n");
1405
1406 ad7173_sigma_delta_info.irq_line = ret;
1407
1408 return ad7173_fw_parse_channel_config(indio_dev);
1409 }
1410
1411 static int ad7173_probe(struct spi_device *spi)
1412 {
1413 struct device *dev = &spi->dev;
1414 struct ad7173_state *st;
1415 struct iio_dev *indio_dev;
1416 int ret;
1417
1418 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1419 if (!indio_dev)
1420 return -ENOMEM;
1421
1422 st = iio_priv(indio_dev);
1423 st->info = spi_get_device_match_data(spi);
1424 if (!st->info)
1425 return -ENODEV;
1426
1427 ida_init(&st->cfg_slots_status);
1428 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
1429 if (ret)
1430 return ret;
1431
1432 indio_dev->name = st->info->name;
1433 indio_dev->modes = INDIO_DIRECT_MODE;
1434 indio_dev->info = &ad7173_info;
1435
1436 spi->mode = SPI_MODE_3;
1437 spi_setup(spi);
1438
1439 ad7173_sigma_delta_info.num_slots = st->info->num_configs;
1440 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7173_sigma_delta_info);
1441 if (ret)
1442 return ret;
1443
1444 ret = ad7173_fw_parse_device_config(indio_dev);
1445 if (ret)
1446 return ret;
1447
1448 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1449 if (ret)
1450 return ret;
1451
1452 ret = ad7173_setup(indio_dev);
1453 if (ret)
1454 return ret;
1455
1456 ret = devm_iio_device_register(dev, indio_dev);
1457 if (ret)
1458 return ret;
1459
1460 if (IS_ENABLED(CONFIG_GPIOLIB))
1461 return ad7173_gpio_init(st);
1462
1463 return 0;
1464 }
1465
1466 static const struct of_device_id ad7173_of_match[] = {
1467 { .compatible = "adi,ad4111", .data = &ad4111_device_info },
1468 { .compatible = "adi,ad4112", .data = &ad4112_device_info },
1469 { .compatible = "adi,ad4113", .data = &ad4113_device_info },
1470 { .compatible = "adi,ad4114", .data = &ad4114_device_info },
1471 { .compatible = "adi,ad4115", .data = &ad4115_device_info },
1472 { .compatible = "adi,ad4116", .data = &ad4116_device_info },
1473 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
1474 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
1475 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
1476 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info },
1477 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info },
1478 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info },
1479 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info },
1480 { }
1481 };
1482 MODULE_DEVICE_TABLE(of, ad7173_of_match);
1483
1484 static const struct spi_device_id ad7173_id_table[] = {
1485 { "ad4111", (kernel_ulong_t)&ad4111_device_info },
1486 { "ad4112", (kernel_ulong_t)&ad4112_device_info },
1487 { "ad4113", (kernel_ulong_t)&ad4113_device_info },
1488 { "ad4114", (kernel_ulong_t)&ad4114_device_info },
1489 { "ad4115", (kernel_ulong_t)&ad4115_device_info },
1490 { "ad4116", (kernel_ulong_t)&ad4116_device_info },
1491 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info },
1492 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info },
1493 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info },
1494 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info },
1495 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info },
1496 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info },
1497 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info },
1498 { }
1499 };
1500 MODULE_DEVICE_TABLE(spi, ad7173_id_table);
1501
1502 static struct spi_driver ad7173_driver = {
1503 .driver = {
1504 .name = "ad7173",
1505 .of_match_table = ad7173_of_match,
1506 },
1507 .probe = ad7173_probe,
1508 .id_table = ad7173_id_table,
1509 };
1510 module_spi_driver(ad7173_driver);
1511
1512 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1513 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>");
1514 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>");
1515 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver");
1516 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes