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drm/client: Fix drm client endless Kconfig loop
[drm/drm-misc.git] / drivers / iio / adc / at91-sama5d2_adc.c
blob8e5aaf15a9215083d90312e037b18c2b09e132e8
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Atmel ADC driver for SAMA5D2 devices and compatible.
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * 2021 Microchip Technology, Inc. and its subsidiaries
8 * 2021 Eugen Hristev <eugen.hristev@microchip.com>
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/sched.h>
23 #include <linux/units.h>
24 #include <linux/wait.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/nvmem-consumer.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
35
36 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
37
38 struct at91_adc_reg_layout {
39 /* Control Register */
40 u16 CR;
41 /* Software Reset */
42 #define AT91_SAMA5D2_CR_SWRST BIT(0)
43 /* Start Conversion */
44 #define AT91_SAMA5D2_CR_START BIT(1)
45 /* Touchscreen Calibration */
46 #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
47 /* Comparison Restart */
48 #define AT91_SAMA5D2_CR_CMPRST BIT(4)
49
50 /* Mode Register */
51 u16 MR;
52 /* Trigger Selection */
53 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
54 /* ADTRG */
55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
56 /* TIOA0 */
57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
58 /* TIOA1 */
59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
60 /* TIOA2 */
61 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
62 /* PWM event line 0 */
63 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
64 /* PWM event line 1 */
65 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
66 /* TIOA3 */
67 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
68 /* RTCOUT0 */
69 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
70 /* Sleep Mode */
71 #define AT91_SAMA5D2_MR_SLEEP BIT(5)
72 /* Fast Wake Up */
73 #define AT91_SAMA5D2_MR_FWUP BIT(6)
74 /* Prescaler Rate Selection */
75 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
76 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
77 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
78 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
79 /* Startup Time */
80 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
81 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
82 /* Minimum startup time for temperature sensor */
83 #define AT91_SAMA5D2_MR_STARTUP_TS_MIN (50)
84 /* Analog Change */
85 #define AT91_SAMA5D2_MR_ANACH BIT(23)
86 /* Tracking Time */
87 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
88 #define AT91_SAMA5D2_MR_TRACKTIM_TS 6
89 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf
90 /* Transfer Time */
91 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
92 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
93 /* Use Sequence Enable */
94 #define AT91_SAMA5D2_MR_USEQ BIT(31)
95
96 /* Channel Sequence Register 1 */
97 u16 SEQR1;
98 /* Channel Sequence Register 2 */
99 u16 SEQR2;
100 /* Channel Enable Register */
101 u16 CHER;
102 /* Channel Disable Register */
103 u16 CHDR;
104 /* Channel Status Register */
105 u16 CHSR;
106 /* Last Converted Data Register */
107 u16 LCDR;
108 /* Interrupt Enable Register */
109 u16 IER;
110 /* Interrupt Enable Register - TS X measurement ready */
111 #define AT91_SAMA5D2_IER_XRDY BIT(20)
112 /* Interrupt Enable Register - TS Y measurement ready */
113 #define AT91_SAMA5D2_IER_YRDY BIT(21)
114 /* Interrupt Enable Register - TS pressure measurement ready */
115 #define AT91_SAMA5D2_IER_PRDY BIT(22)
116 /* Interrupt Enable Register - Data ready */
117 #define AT91_SAMA5D2_IER_DRDY BIT(24)
118 /* Interrupt Enable Register - general overrun error */
119 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
120 /* Interrupt Enable Register - Pen detect */
121 #define AT91_SAMA5D2_IER_PEN BIT(29)
122 /* Interrupt Enable Register - No pen detect */
123 #define AT91_SAMA5D2_IER_NOPEN BIT(30)
124
125 /* Interrupt Disable Register */
126 u16 IDR;
127 /* Interrupt Mask Register */
128 u16 IMR;
129 /* Interrupt Status Register */
130 u16 ISR;
131 /* End of Conversion Interrupt Enable Register */
132 u16 EOC_IER;
133 /* End of Conversion Interrupt Disable Register */
134 u16 EOC_IDR;
135 /* End of Conversion Interrupt Mask Register */
136 u16 EOC_IMR;
137 /* End of Conversion Interrupt Status Register */
138 u16 EOC_ISR;
139 /* Interrupt Status Register - Pen touching sense status */
140 #define AT91_SAMA5D2_ISR_PENS BIT(31)
141 /* Last Channel Trigger Mode Register */
142 u16 LCTMR;
143 /* Last Channel Compare Window Register */
144 u16 LCCWR;
145 /* Overrun Status Register */
146 u16 OVER;
147 /* Extended Mode Register */
148 u16 EMR;
149 /* Extended Mode Register - Oversampling rate */
150 #define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M))
151 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
152 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
153 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
154 #define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3
155 #define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4
156
157 /* Extended Mode Register - TRACKX */
158 #define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22)
159 #define AT91_SAMA5D2_TRACKX(x) (((x) << 22) & \
160 AT91_SAMA5D2_TRACKX_MASK)
161 /* TRACKX for temperature sensor. */
162 #define AT91_SAMA5D2_TRACKX_TS (1)
163
164 /* Extended Mode Register - Averaging on single trigger event */
165 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
166
167 /* Compare Window Register */
168 u16 CWR;
169 /* Channel Gain Register */
170 u16 CGR;
171 /* Channel Offset Register */
172 u16 COR;
173 /* Channel Offset Register differential offset - constant, not a register */
174 u16 COR_diff_offset;
175 /* Analog Control Register */
176 u16 ACR;
177 /* Analog Control Register - Pen detect sensitivity mask */
178 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
179 /* Analog Control Register - Source last channel */
180 #define AT91_SAMA5D2_ACR_SRCLCH BIT(16)
181
182 /* Touchscreen Mode Register */
183 u16 TSMR;
184 /* Touchscreen Mode Register - No touch mode */
185 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
186 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
187 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
188 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
189 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
190 /* Touchscreen Mode Register - 5 wire screen */
191 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
192 /* Touchscreen Mode Register - Average samples mask */
193 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
194 /* Touchscreen Mode Register - Average samples */
195 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
196 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
197 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
198 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
199 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
200 /* Touchscreen Mode Register - Pen Debounce Time mask */
201 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
202 /* Touchscreen Mode Register - Pen Debounce Time */
203 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
204 /* Touchscreen Mode Register - No DMA for touch measurements */
205 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
206 /* Touchscreen Mode Register - Disable pen detection */
207 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
208 /* Touchscreen Mode Register - Enable pen detection */
209 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
210
211 /* Touchscreen X Position Register */
212 u16 XPOSR;
213 /* Touchscreen Y Position Register */
214 u16 YPOSR;
215 /* Touchscreen Pressure Register */
216 u16 PRESSR;
217 /* Trigger Register */
218 u16 TRGR;
219 /* Mask for TRGMOD field of TRGR register */
220 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
221 /* No trigger, only software trigger can start conversions */
222 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
223 /* Trigger Mode external trigger rising edge */
224 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
225 /* Trigger Mode external trigger falling edge */
226 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
227 /* Trigger Mode external trigger any edge */
228 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
229 /* Trigger Mode internal periodic */
230 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
231 /* Trigger Mode - trigger period mask */
232 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
233 /* Trigger Mode - trigger period */
234 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
235
236 /* Correction Select Register */
237 u16 COSR;
238 /* Correction Value Register */
239 u16 CVR;
240 /* Channel Error Correction Register */
241 u16 CECR;
242 /* Write Protection Mode Register */
243 u16 WPMR;
244 /* Write Protection Status Register */
245 u16 WPSR;
246 /* Version Register */
247 u16 VERSION;
248 /* Temperature Sensor Mode Register */
249 u16 TEMPMR;
250 /* Temperature Sensor Mode - Temperature sensor on */
251 #define AT91_SAMA5D2_TEMPMR_TEMPON BIT(0)
252 };
253
254 static const struct at91_adc_reg_layout sama5d2_layout = {
255 .CR = 0x00,
256 .MR = 0x04,
257 .SEQR1 = 0x08,
258 .SEQR2 = 0x0c,
259 .CHER = 0x10,
260 .CHDR = 0x14,
261 .CHSR = 0x18,
262 .LCDR = 0x20,
263 .IER = 0x24,
264 .IDR = 0x28,
265 .IMR = 0x2c,
266 .ISR = 0x30,
267 .LCTMR = 0x34,
268 .LCCWR = 0x38,
269 .OVER = 0x3c,
270 .EMR = 0x40,
271 .CWR = 0x44,
272 .CGR = 0x48,
273 .COR = 0x4c,
274 .COR_diff_offset = 16,
275 .ACR = 0x94,
276 .TSMR = 0xb0,
277 .XPOSR = 0xb4,
278 .YPOSR = 0xb8,
279 .PRESSR = 0xbc,
280 .TRGR = 0xc0,
281 .COSR = 0xd0,
282 .CVR = 0xd4,
283 .CECR = 0xd8,
284 .WPMR = 0xe4,
285 .WPSR = 0xe8,
286 .VERSION = 0xfc,
287 };
288
289 static const struct at91_adc_reg_layout sama7g5_layout = {
290 .CR = 0x00,
291 .MR = 0x04,
292 .SEQR1 = 0x08,
293 .SEQR2 = 0x0c,
294 .CHER = 0x10,
295 .CHDR = 0x14,
296 .CHSR = 0x18,
297 .LCDR = 0x20,
298 .IER = 0x24,
299 .IDR = 0x28,
300 .IMR = 0x2c,
301 .ISR = 0x30,
302 .EOC_IER = 0x34,
303 .EOC_IDR = 0x38,
304 .EOC_IMR = 0x3c,
305 .EOC_ISR = 0x40,
306 .TEMPMR = 0x44,
307 .OVER = 0x4c,
308 .EMR = 0x50,
309 .CWR = 0x54,
310 .COR = 0x5c,
311 .COR_diff_offset = 0,
312 .ACR = 0xe0,
313 .TRGR = 0x100,
314 .COSR = 0x104,
315 .CVR = 0x108,
316 .CECR = 0x10c,
317 .WPMR = 0x118,
318 .WPSR = 0x11c,
319 .VERSION = 0x130,
320 };
321
322 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
323 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
324
325 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
326
327 #define AT91_SAMA5D2_MAX_POS_BITS 12
328
329 #define AT91_HWFIFO_MAX_SIZE_STR "128"
330 #define AT91_HWFIFO_MAX_SIZE 128
331
332 #define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \
333 { \
334 .type = IIO_VOLTAGE, \
335 .channel = num, \
336 .address = addr, \
337 .scan_index = index, \
338 .scan_type = { \
339 .sign = 'u', \
340 .realbits = 14, \
341 .storagebits = 16, \
342 }, \
343 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
344 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
345 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
346 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
347 .info_mask_shared_by_all_available = \
348 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
349 .datasheet_name = "CH"#num, \
350 .indexed = 1, \
351 }
352
353 #define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \
354 { \
355 .type = IIO_VOLTAGE, \
356 .differential = 1, \
357 .channel = num, \
358 .channel2 = num2, \
359 .address = addr, \
360 .scan_index = index, \
361 .scan_type = { \
362 .sign = 's', \
363 .realbits = 14, \
364 .storagebits = 16, \
365 }, \
366 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
367 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
368 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
369 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
370 .info_mask_shared_by_all_available = \
371 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
372 .datasheet_name = "CH"#num"-CH"#num2, \
373 .indexed = 1, \
374 }
375
376 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
377 { \
378 .type = IIO_POSITIONRELATIVE, \
379 .modified = 1, \
380 .channel = num, \
381 .channel2 = mod, \
382 .scan_index = num, \
383 .scan_type = { \
384 .sign = 'u', \
385 .realbits = 12, \
386 .storagebits = 16, \
387 }, \
388 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
389 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
390 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
391 .info_mask_shared_by_all_available = \
392 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
393 .datasheet_name = name, \
394 }
395 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
396 { \
397 .type = IIO_PRESSURE, \
398 .channel = num, \
399 .scan_index = num, \
400 .scan_type = { \
401 .sign = 'u', \
402 .realbits = 12, \
403 .storagebits = 16, \
404 }, \
405 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
406 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
407 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
408 .info_mask_shared_by_all_available = \
409 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
410 .datasheet_name = name, \
411 }
412
413 #define AT91_SAMA5D2_CHAN_TEMP(num, name, addr) \
414 { \
415 .type = IIO_TEMP, \
416 .channel = num, \
417 .address = addr, \
418 .scan_index = num, \
419 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
420 .info_mask_shared_by_all = \
421 BIT(IIO_CHAN_INFO_PROCESSED) | \
422 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
423 .info_mask_shared_by_all_available = \
424 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
425 .datasheet_name = name, \
426 }
427
428 #define at91_adc_readl(st, reg) \
429 readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg)
430 #define at91_adc_read_chan(st, reg) \
431 readl_relaxed((st)->base + reg)
432 #define at91_adc_writel(st, reg, val) \
433 writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
434
435 /**
436 * struct at91_adc_platform - at91-sama5d2 platform information struct
437 * @layout: pointer to the reg layout struct
438 * @adc_channels: pointer to an array of channels for registering in
439 * the iio subsystem
440 * @nr_channels: number of physical channels available
441 * @touch_chan_x: index of the touchscreen X channel
442 * @touch_chan_y: index of the touchscreen Y channel
443 * @touch_chan_p: index of the touchscreen P channel
444 * @max_channels: number of total channels
445 * @max_index: highest channel index (highest index may be higher
446 * than the total channel number)
447 * @hw_trig_cnt: number of possible hardware triggers
448 * @osr_mask: oversampling ratio bitmask on EMR register
449 * @oversampling_avail: available oversampling values
450 * @oversampling_avail_no: number of available oversampling values
451 * @chan_realbits: realbits for registered channels
452 * @temp_chan: temperature channel index
453 * @temp_sensor: temperature sensor supported
454 */
455 struct at91_adc_platform {
456 const struct at91_adc_reg_layout *layout;
457 const struct iio_chan_spec (*adc_channels)[];
458 unsigned int nr_channels;
459 unsigned int touch_chan_x;
460 unsigned int touch_chan_y;
461 unsigned int touch_chan_p;
462 unsigned int max_channels;
463 unsigned int max_index;
464 unsigned int hw_trig_cnt;
465 unsigned int osr_mask;
466 unsigned int oversampling_avail[5];
467 unsigned int oversampling_avail_no;
468 unsigned int chan_realbits;
469 unsigned int temp_chan;
470 bool temp_sensor;
471 };
472
473 /**
474 * struct at91_adc_temp_sensor_clb - at91-sama5d2 temperature sensor
475 * calibration data structure
476 * @p1: P1 calibration temperature
477 * @p4: P4 calibration voltage
478 * @p6: P6 calibration voltage
479 */
480 struct at91_adc_temp_sensor_clb {
481 u32 p1;
482 u32 p4;
483 u32 p6;
484 };
485
486 /**
487 * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer
488 * @AT91_ADC_TS_CLB_IDX_P1: index for P1
489 * @AT91_ADC_TS_CLB_IDX_P4: index for P4
490 * @AT91_ADC_TS_CLB_IDX_P6: index for P6
491 * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP
492 */
493 enum at91_adc_ts_clb_idx {
494 AT91_ADC_TS_CLB_IDX_P1 = 2,
495 AT91_ADC_TS_CLB_IDX_P4 = 5,
496 AT91_ADC_TS_CLB_IDX_P6 = 7,
497 AT91_ADC_TS_CLB_IDX_MAX = 19,
498 };
499
500 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */
501 #define AT91_ADC_TS_VTEMP_DT (2080U)
502
503 /**
504 * struct at91_adc_soc_info - at91-sama5d2 soc information struct
505 * @startup_time: device startup time
506 * @min_sample_rate: minimum sample rate in Hz
507 * @max_sample_rate: maximum sample rate in Hz
508 * @platform: pointer to the platform structure
509 * @temp_sensor_clb: temperature sensor calibration data structure
510 */
511 struct at91_adc_soc_info {
512 unsigned startup_time;
513 unsigned min_sample_rate;
514 unsigned max_sample_rate;
515 const struct at91_adc_platform *platform;
516 struct at91_adc_temp_sensor_clb temp_sensor_clb;
517 };
518
519 struct at91_adc_trigger {
520 char *name;
521 unsigned int trgmod_value;
522 unsigned int edge_type;
523 bool hw_trig;
524 };
525
526 /**
527 * struct at91_adc_dma - at91-sama5d2 dma information struct
528 * @dma_chan: the dma channel acquired
529 * @rx_buf: dma coherent allocated area
530 * @rx_dma_buf: dma handler for the buffer
531 * @phys_addr: physical address of the ADC base register
532 * @buf_idx: index inside the dma buffer where reading was last done
533 * @rx_buf_sz: size of buffer used by DMA operation
534 * @watermark: number of conversions to copy before DMA triggers irq
535 * @dma_ts: hold the start timestamp of dma operation
536 */
537 struct at91_adc_dma {
538 struct dma_chan *dma_chan;
539 u8 *rx_buf;
540 dma_addr_t rx_dma_buf;
541 phys_addr_t phys_addr;
542 int buf_idx;
543 int rx_buf_sz;
544 int watermark;
545 s64 dma_ts;
546 };
547
548 /**
549 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
550 * @sample_period_val: the value for periodic trigger interval
551 * @touching: is the pen touching the screen or not
552 * @x_pos: temporary placeholder for pressure computation
553 * @channels_bitmask: bitmask with the touchscreen channels enabled
554 * @workq: workqueue for buffer data pushing
555 */
556 struct at91_adc_touch {
557 u16 sample_period_val;
558 bool touching;
559 u16 x_pos;
560 unsigned long channels_bitmask;
561 struct work_struct workq;
562 };
563
564 /**
565 * struct at91_adc_temp - at91-sama5d2 temperature information structure
566 * @sample_period_val: sample period value
567 * @saved_sample_rate: saved sample rate
568 * @saved_oversampling: saved oversampling
569 */
570 struct at91_adc_temp {
571 u16 sample_period_val;
572 u16 saved_sample_rate;
573 u16 saved_oversampling;
574 };
575
576 /*
577 * Buffer size requirements:
578 * No channels * bytes_per_channel(2) + timestamp bytes (8)
579 * Divided by 2 because we need half words.
580 * We assume 32 channels for now, has to be increased if needed.
581 * Nobody minds a buffer being too big.
582 */
583 #define AT91_BUFFER_MAX_HWORDS ((32 * 2 + 8) / 2)
584
585 struct at91_adc_state {
586 void __iomem *base;
587 int irq;
588 struct clk *per_clk;
589 struct regulator *reg;
590 struct regulator *vref;
591 int vref_uv;
592 unsigned int current_sample_rate;
593 struct iio_trigger *trig;
594 const struct at91_adc_trigger *selected_trig;
595 const struct iio_chan_spec *chan;
596 bool conversion_done;
597 u32 conversion_value;
598 unsigned int oversampling_ratio;
599 struct at91_adc_soc_info soc_info;
600 wait_queue_head_t wq_data_available;
601 struct at91_adc_dma dma_st;
602 struct at91_adc_touch touch_st;
603 struct at91_adc_temp temp_st;
604 struct iio_dev *indio_dev;
605 struct device *dev;
606 /* Ensure naturally aligned timestamp */
607 u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8);
608 /*
609 * lock to prevent concurrent 'single conversion' requests through
610 * sysfs.
611 */
612 struct mutex lock;
613 };
614
615 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
616 {
617 .name = "external_rising",
618 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
619 .edge_type = IRQ_TYPE_EDGE_RISING,
620 .hw_trig = true,
621 },
622 {
623 .name = "external_falling",
624 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
625 .edge_type = IRQ_TYPE_EDGE_FALLING,
626 .hw_trig = true,
627 },
628 {
629 .name = "external_any",
630 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
631 .edge_type = IRQ_TYPE_EDGE_BOTH,
632 .hw_trig = true,
633 },
634 {
635 .name = "software",
636 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
637 .edge_type = IRQ_TYPE_NONE,
638 .hw_trig = false,
639 },
640 };
641
642 static const struct iio_chan_spec at91_sama5d2_adc_channels[] = {
643 AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x50),
644 AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x54),
645 AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x58),
646 AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x5c),
647 AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x60),
648 AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x64),
649 AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x68),
650 AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x6c),
651 AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x70),
652 AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x74),
653 AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x78),
654 AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x7c),
655 /* original ABI has the differential channels with a gap in between */
656 AT91_SAMA5D2_CHAN_DIFF(12, 0, 1, 0x50),
657 AT91_SAMA5D2_CHAN_DIFF(14, 2, 3, 0x58),
658 AT91_SAMA5D2_CHAN_DIFF(16, 4, 5, 0x60),
659 AT91_SAMA5D2_CHAN_DIFF(18, 6, 7, 0x68),
660 AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x70),
661 AT91_SAMA5D2_CHAN_DIFF(22, 10, 11, 0x78),
662 IIO_CHAN_SOFT_TIMESTAMP(23),
663 AT91_SAMA5D2_CHAN_TOUCH(24, "x", IIO_MOD_X),
664 AT91_SAMA5D2_CHAN_TOUCH(25, "y", IIO_MOD_Y),
665 AT91_SAMA5D2_CHAN_PRESSURE(26, "pressure"),
666 };
667
668 static const struct iio_chan_spec at91_sama7g5_adc_channels[] = {
669 AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x60),
670 AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x64),
671 AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x68),
672 AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x6c),
673 AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x70),
674 AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x74),
675 AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x78),
676 AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x7c),
677 AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x80),
678 AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x84),
679 AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x88),
680 AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x8c),
681 AT91_SAMA5D2_CHAN_SINGLE(12, 12, 0x90),
682 AT91_SAMA5D2_CHAN_SINGLE(13, 13, 0x94),
683 AT91_SAMA5D2_CHAN_SINGLE(14, 14, 0x98),
684 AT91_SAMA5D2_CHAN_SINGLE(15, 15, 0x9c),
685 AT91_SAMA5D2_CHAN_DIFF(16, 0, 1, 0x60),
686 AT91_SAMA5D2_CHAN_DIFF(17, 2, 3, 0x68),
687 AT91_SAMA5D2_CHAN_DIFF(18, 4, 5, 0x70),
688 AT91_SAMA5D2_CHAN_DIFF(19, 6, 7, 0x78),
689 AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x80),
690 AT91_SAMA5D2_CHAN_DIFF(21, 10, 11, 0x88),
691 AT91_SAMA5D2_CHAN_DIFF(22, 12, 13, 0x90),
692 AT91_SAMA5D2_CHAN_DIFF(23, 14, 15, 0x98),
693 IIO_CHAN_SOFT_TIMESTAMP(24),
694 AT91_SAMA5D2_CHAN_TEMP(AT91_SAMA7G5_ADC_TEMP_CHANNEL, "temp", 0xdc),
695 };
696
697 static const struct at91_adc_platform sama5d2_platform = {
698 .layout = &sama5d2_layout,
699 .adc_channels = &at91_sama5d2_adc_channels,
700 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
701 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
702 .nr_channels = AT91_SAMA5D2_SINGLE_CHAN_CNT +
703 AT91_SAMA5D2_DIFF_CHAN_CNT,
704 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
705 AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
706 .touch_chan_x = AT91_SAMA5D2_TOUCH_X_CHAN_IDX,
707 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
708 .touch_chan_y = AT91_SAMA5D2_TOUCH_Y_CHAN_IDX,
709 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
710 .touch_chan_p = AT91_SAMA5D2_TOUCH_P_CHAN_IDX,
711 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
712 .max_channels = ARRAY_SIZE(at91_sama5d2_adc_channels),
713 .max_index = AT91_SAMA5D2_MAX_CHAN_IDX,
714 #define AT91_SAMA5D2_HW_TRIG_CNT 3
715 .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT,
716 .osr_mask = GENMASK(17, 16),
717 .oversampling_avail = { 1, 4, 16, },
718 .oversampling_avail_no = 3,
719 .chan_realbits = 14,
720 };
721
722 static const struct at91_adc_platform sama7g5_platform = {
723 .layout = &sama7g5_layout,
724 .adc_channels = &at91_sama7g5_adc_channels,
725 #define AT91_SAMA7G5_SINGLE_CHAN_CNT 16
726 #define AT91_SAMA7G5_DIFF_CHAN_CNT 8
727 #define AT91_SAMA7G5_TEMP_CHAN_CNT 1
728 .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT +
729 AT91_SAMA7G5_DIFF_CHAN_CNT +
730 AT91_SAMA7G5_TEMP_CHAN_CNT,
731 #define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \
732 AT91_SAMA7G5_DIFF_CHAN_CNT + \
733 AT91_SAMA7G5_TEMP_CHAN_CNT)
734 .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels),
735 .max_index = AT91_SAMA7G5_MAX_CHAN_IDX,
736 #define AT91_SAMA7G5_HW_TRIG_CNT 3
737 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT,
738 .osr_mask = GENMASK(18, 16),
739 .oversampling_avail = { 1, 4, 16, 64, 256, },
740 .oversampling_avail_no = 5,
741 .chan_realbits = 16,
742 .temp_sensor = true,
743 .temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL,
744 };
745
746 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
747 {
748 int i;
749
750 for (i = 0; i < indio_dev->num_channels; i++) {
751 if (indio_dev->channels[i].scan_index == chan)
752 return i;
753 }
754 return -EINVAL;
755 }
756
757 static inline struct iio_chan_spec const *
758 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
759 {
760 int index = at91_adc_chan_xlate(indio_dev, chan);
761
762 if (index < 0)
763 return NULL;
764 return indio_dev->channels + index;
765 }
766
767 static inline int at91_adc_fwnode_xlate(struct iio_dev *indio_dev,
768 const struct fwnode_reference_args *iiospec)
769 {
770 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
771 }
772
773 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
774 {
775 u32 mask = 0;
776 u8 bit;
777 struct at91_adc_state *st = iio_priv(indio_dev);
778
779 for_each_set_bit(bit, indio_dev->active_scan_mask,
780 indio_dev->num_channels) {
781 struct iio_chan_spec const *chan =
782 at91_adc_chan_get(indio_dev, bit);
783 mask |= BIT(chan->channel);
784 }
785
786 return mask & GENMASK(st->soc_info.platform->nr_channels, 0);
787 }
788
789 static void at91_adc_cor(struct at91_adc_state *st,
790 struct iio_chan_spec const *chan)
791 {
792 u32 cor, cur_cor;
793
794 cor = BIT(chan->channel) | BIT(chan->channel2);
795
796 cur_cor = at91_adc_readl(st, COR);
797 cor <<= st->soc_info.platform->layout->COR_diff_offset;
798 if (chan->differential)
799 at91_adc_writel(st, COR, cur_cor | cor);
800 else
801 at91_adc_writel(st, COR, cur_cor & ~cor);
802 }
803
804 static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status,
805 u32 *eoc)
806 {
807 *status = at91_adc_readl(st, ISR);
808 if (st->soc_info.platform->layout->EOC_ISR)
809 *eoc = at91_adc_readl(st, EOC_ISR);
810 else
811 *eoc = *status;
812 }
813
814 static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc)
815 {
816 *status = at91_adc_readl(st, IMR);
817 if (st->soc_info.platform->layout->EOC_IMR)
818 *eoc = at91_adc_readl(st, EOC_IMR);
819 else
820 *eoc = *status;
821 }
822
823 static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel)
824 {
825 /*
826 * On some products having the EOC bits in a separate register,
827 * errata recommends not writing this register (EOC_IDR).
828 * On products having the EOC bits in the IDR register, it's fine to write it.
829 */
830 if (!st->soc_info.platform->layout->EOC_IDR)
831 at91_adc_writel(st, IDR, BIT(channel));
832 }
833
834 static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel)
835 {
836 if (!st->soc_info.platform->layout->EOC_IDR)
837 at91_adc_writel(st, IER, BIT(channel));
838 else
839 at91_adc_writel(st, EOC_IER, BIT(channel));
840 }
841
842 static int at91_adc_config_emr(struct at91_adc_state *st,
843 u32 oversampling_ratio, u32 trackx)
844 {
845 /* configure the extended mode register */
846 unsigned int emr, osr;
847 unsigned int osr_mask = st->soc_info.platform->osr_mask;
848 int i, ret;
849
850 /* Check against supported oversampling values. */
851 for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) {
852 if (oversampling_ratio == st->soc_info.platform->oversampling_avail[i])
853 break;
854 }
855 if (i == st->soc_info.platform->oversampling_avail_no)
856 return -EINVAL;
857
858 /* select oversampling ratio from configuration */
859 switch (oversampling_ratio) {
860 case 1:
861 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES,
862 osr_mask);
863 break;
864 case 4:
865 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES,
866 osr_mask);
867 break;
868 case 16:
869 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES,
870 osr_mask);
871 break;
872 case 64:
873 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES,
874 osr_mask);
875 break;
876 case 256:
877 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES,
878 osr_mask);
879 break;
880 }
881
882 ret = pm_runtime_resume_and_get(st->dev);
883 if (ret < 0)
884 return ret;
885
886 emr = at91_adc_readl(st, EMR);
887 /* select oversampling per single trigger event */
888 emr |= AT91_SAMA5D2_EMR_ASTE(1);
889 /* delete leftover content if it's the case */
890 emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK);
891 /* Update osr and trackx. */
892 emr |= osr | AT91_SAMA5D2_TRACKX(trackx);
893 at91_adc_writel(st, EMR, emr);
894
895 pm_runtime_mark_last_busy(st->dev);
896 pm_runtime_put_autosuspend(st->dev);
897
898 st->oversampling_ratio = oversampling_ratio;
899
900 return 0;
901 }
902
903 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
904 {
905 int nbits, diff;
906
907 if (st->oversampling_ratio == 1)
908 nbits = 12;
909 else if (st->oversampling_ratio == 4)
910 nbits = 13;
911 else if (st->oversampling_ratio == 16)
912 nbits = 14;
913 else if (st->oversampling_ratio == 64)
914 nbits = 15;
915 else if (st->oversampling_ratio == 256)
916 nbits = 16;
917 else
918 /* Should not happen. */
919 return -EINVAL;
920
921 /*
922 * We have nbits of real data and channel is registered as
923 * st->soc_info.platform->chan_realbits, so shift left diff bits.
924 */
925 diff = st->soc_info.platform->chan_realbits - nbits;
926 *val <<= diff;
927
928 return IIO_VAL_INT;
929 }
930
931 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
932 int len)
933 {
934 int i = 0, val;
935 u16 *buf_u16 = (u16 *) buf;
936
937 /*
938 * We are converting each two bytes (each sample).
939 * First convert the byte based array to u16, and convert each sample
940 * separately.
941 * Each value is two bytes in an array of chars, so to not shift
942 * more than we need, save the value separately.
943 * len is in bytes, so divide by two to get number of samples.
944 */
945 while (i < len / 2) {
946 val = buf_u16[i];
947 at91_adc_adjust_val_osr(st, &val);
948 buf_u16[i] = val;
949 i++;
950 }
951 }
952
953 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
954 {
955 u32 clk_khz = st->current_sample_rate / 1000;
956 int i = 0, ret;
957 u16 pendbc;
958 u32 tsmr, acr;
959
960 if (state) {
961 ret = pm_runtime_resume_and_get(st->dev);
962 if (ret < 0)
963 return ret;
964 } else {
965 /* disabling touch IRQs and setting mode to no touch enabled */
966 at91_adc_writel(st, IDR,
967 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
968 at91_adc_writel(st, TSMR, 0);
969
970 pm_runtime_mark_last_busy(st->dev);
971 pm_runtime_put_autosuspend(st->dev);
972 return 0;
973 }
974 /*
975 * debounce time is in microseconds, we need it in milliseconds to
976 * multiply with kilohertz, so, divide by 1000, but after the multiply.
977 * round up to make sure pendbc is at least 1
978 */
979 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
980 clk_khz / 1000, 1);
981
982 /* get the required exponent */
983 while (pendbc >> i++)
984 ;
985
986 pendbc = i;
987
988 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
989
990 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
991 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
992 AT91_SAMA5D2_TSMR_PENDBC_MASK;
993 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
994 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
995 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
996
997 at91_adc_writel(st, TSMR, tsmr);
998
999 acr = at91_adc_readl(st, ACR);
1000 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
1001 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
1002 at91_adc_writel(st, ACR, acr);
1003
1004 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1005 st->touch_st.sample_period_val =
1006 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
1007 clk_khz / 1000) - 1, 1);
1008 /* enable pen detect IRQ */
1009 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
1010
1011 return 0;
1012 }
1013
1014 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
1015 {
1016 u32 val = 0;
1017 u32 scale, result, pos;
1018
1019 /*
1020 * to obtain the actual position we must divide by scale
1021 * and multiply with max, where
1022 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
1023 */
1024 /* first half of register is the x or y, second half is the scale */
1025 if (reg == st->soc_info.platform->layout->XPOSR)
1026 val = at91_adc_readl(st, XPOSR);
1027 else if (reg == st->soc_info.platform->layout->YPOSR)
1028 val = at91_adc_readl(st, YPOSR);
1029
1030 if (!val)
1031 dev_dbg(&st->indio_dev->dev, "pos is 0\n");
1032
1033 pos = val & AT91_SAMA5D2_XYZ_MASK;
1034 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
1035 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
1036 if (scale == 0) {
1037 dev_err(&st->indio_dev->dev, "scale is 0\n");
1038 return 0;
1039 }
1040 result /= scale;
1041
1042 return result;
1043 }
1044
1045 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
1046 {
1047 st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR);
1048 return st->touch_st.x_pos;
1049 }
1050
1051 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
1052 {
1053 return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR);
1054 }
1055
1056 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
1057 {
1058 u32 val;
1059 u32 z1, z2;
1060 u32 pres;
1061 u32 rxp = 1;
1062 u32 factor = 1000;
1063
1064 /* calculate the pressure */
1065 val = at91_adc_readl(st, PRESSR);
1066 z1 = val & AT91_SAMA5D2_XYZ_MASK;
1067 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
1068
1069 if (z1 != 0)
1070 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
1071 (z2 * factor / z1 - factor) /
1072 factor;
1073 else
1074 pres = 0xFFFF; /* no pen contact */
1075
1076 /*
1077 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
1078 * We compute it this way, but let's return it in the expected way,
1079 * growing from 0 to 0xFFFF.
1080 */
1081 return 0xFFFF - pres;
1082 }
1083
1084 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
1085 {
1086 *val = 0;
1087 if (!st->touch_st.touching)
1088 return -ENODATA;
1089 if (chan == st->soc_info.platform->touch_chan_x)
1090 *val = at91_adc_touch_x_pos(st);
1091 else if (chan == st->soc_info.platform->touch_chan_y)
1092 *val = at91_adc_touch_y_pos(st);
1093 else
1094 return -ENODATA;
1095
1096 return IIO_VAL_INT;
1097 }
1098
1099 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
1100 {
1101 *val = 0;
1102 if (!st->touch_st.touching)
1103 return -ENODATA;
1104 if (chan == st->soc_info.platform->touch_chan_p)
1105 *val = at91_adc_touch_pressure(st);
1106 else
1107 return -ENODATA;
1108
1109 return IIO_VAL_INT;
1110 }
1111
1112 static void at91_adc_configure_trigger_registers(struct at91_adc_state *st,
1113 bool state)
1114 {
1115 u32 status = at91_adc_readl(st, TRGR);
1116
1117 /* clear TRGMOD */
1118 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
1119
1120 if (state)
1121 status |= st->selected_trig->trgmod_value;
1122
1123 /* set/unset hw trigger */
1124 at91_adc_writel(st, TRGR, status);
1125 }
1126
1127 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
1128 {
1129 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1130 struct at91_adc_state *st = iio_priv(indio);
1131 int ret;
1132
1133 if (state) {
1134 ret = pm_runtime_resume_and_get(st->dev);
1135 if (ret < 0)
1136 return ret;
1137 }
1138
1139 at91_adc_configure_trigger_registers(st, state);
1140
1141 if (!state) {
1142 pm_runtime_mark_last_busy(st->dev);
1143 pm_runtime_put_autosuspend(st->dev);
1144 }
1145
1146 return 0;
1147 }
1148
1149 static void at91_adc_reenable_trigger(struct iio_trigger *trig)
1150 {
1151 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1152 struct at91_adc_state *st = iio_priv(indio);
1153
1154 /* if we are using DMA, we must not reenable irq after each trigger */
1155 if (st->dma_st.dma_chan)
1156 return;
1157
1158 enable_irq(st->irq);
1159
1160 /* Needed to ACK the DRDY interruption */
1161 at91_adc_readl(st, LCDR);
1162 }
1163
1164 static const struct iio_trigger_ops at91_adc_trigger_ops = {
1165 .set_trigger_state = &at91_adc_configure_trigger,
1166 .reenable = &at91_adc_reenable_trigger,
1167 .validate_device = iio_trigger_validate_own_device,
1168 };
1169
1170 static int at91_adc_dma_size_done(struct at91_adc_state *st)
1171 {
1172 struct dma_tx_state state;
1173 enum dma_status status;
1174 int i, size;
1175
1176 status = dmaengine_tx_status(st->dma_st.dma_chan,
1177 st->dma_st.dma_chan->cookie,
1178 &state);
1179 if (status != DMA_IN_PROGRESS)
1180 return 0;
1181
1182 /* Transferred length is size in bytes from end of buffer */
1183 i = st->dma_st.rx_buf_sz - state.residue;
1184
1185 /* Return available bytes */
1186 if (i >= st->dma_st.buf_idx)
1187 size = i - st->dma_st.buf_idx;
1188 else
1189 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
1190 return size;
1191 }
1192
1193 static void at91_dma_buffer_done(void *data)
1194 {
1195 struct iio_dev *indio_dev = data;
1196
1197 iio_trigger_poll_nested(indio_dev->trig);
1198 }
1199
1200 static int at91_adc_dma_start(struct iio_dev *indio_dev)
1201 {
1202 struct at91_adc_state *st = iio_priv(indio_dev);
1203 struct dma_async_tx_descriptor *desc;
1204 dma_cookie_t cookie;
1205 int ret;
1206 u8 bit;
1207
1208 if (!st->dma_st.dma_chan)
1209 return 0;
1210
1211 /* we start a new DMA, so set buffer index to start */
1212 st->dma_st.buf_idx = 0;
1213
1214 /*
1215 * compute buffer size w.r.t. watermark and enabled channels.
1216 * scan_bytes is aligned so we need an exact size for DMA
1217 */
1218 st->dma_st.rx_buf_sz = 0;
1219
1220 for_each_set_bit(bit, indio_dev->active_scan_mask,
1221 indio_dev->num_channels) {
1222 struct iio_chan_spec const *chan =
1223 at91_adc_chan_get(indio_dev, bit);
1224
1225 if (!chan)
1226 continue;
1227
1228 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
1229 }
1230 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
1231
1232 /* Prepare a DMA cyclic transaction */
1233 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
1234 st->dma_st.rx_dma_buf,
1235 st->dma_st.rx_buf_sz,
1236 st->dma_st.rx_buf_sz / 2,
1237 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1238
1239 if (!desc) {
1240 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
1241 return -EBUSY;
1242 }
1243
1244 desc->callback = at91_dma_buffer_done;
1245 desc->callback_param = indio_dev;
1246
1247 cookie = dmaengine_submit(desc);
1248 ret = dma_submit_error(cookie);
1249 if (ret) {
1250 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
1251 dmaengine_terminate_async(st->dma_st.dma_chan);
1252 return ret;
1253 }
1254
1255 /* enable general overrun error signaling */
1256 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);
1257 /* Issue pending DMA requests */
1258 dma_async_issue_pending(st->dma_st.dma_chan);
1259
1260 /* consider current time as DMA start time for timestamps */
1261 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1262
1263 dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
1264
1265 return 0;
1266 }
1267
1268 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
1269 struct at91_adc_state *st)
1270 {
1271 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */
1272 if (st->dma_st.dma_chan)
1273 return false;
1274 /* if the trigger is not ours, then it has its own IRQ */
1275 if (iio_trigger_validate_own_device(indio->trig, indio))
1276 return false;
1277 return true;
1278 }
1279
1280 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
1281 {
1282 struct at91_adc_state *st = iio_priv(indio_dev);
1283
1284 return !!bitmap_subset(indio_dev->active_scan_mask,
1285 &st->touch_st.channels_bitmask,
1286 st->soc_info.platform->max_index + 1);
1287 }
1288
1289 static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
1290 {
1291 int ret;
1292 u8 bit;
1293 struct at91_adc_state *st = iio_priv(indio_dev);
1294
1295 /* check if we are enabling triggered buffer or the touchscreen */
1296 if (at91_adc_current_chan_is_touch(indio_dev))
1297 return at91_adc_configure_touch(st, true);
1298
1299 /* if we are not in triggered mode, we cannot enable the buffer. */
1300 if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES))
1301 return -EINVAL;
1302
1303 ret = pm_runtime_resume_and_get(st->dev);
1304 if (ret < 0)
1305 return ret;
1306
1307 /* we continue with the triggered buffer */
1308 ret = at91_adc_dma_start(indio_dev);
1309 if (ret) {
1310 dev_err(&indio_dev->dev, "buffer prepare failed\n");
1311 goto pm_runtime_put;
1312 }
1313
1314 for_each_set_bit(bit, indio_dev->active_scan_mask,
1315 indio_dev->num_channels) {
1316 struct iio_chan_spec const *chan =
1317 at91_adc_chan_get(indio_dev, bit);
1318 if (!chan)
1319 continue;
1320 /* these channel types cannot be handled by this trigger */
1321 if (chan->type == IIO_POSITIONRELATIVE ||
1322 chan->type == IIO_PRESSURE ||
1323 chan->type == IIO_TEMP)
1324 continue;
1325
1326 at91_adc_cor(st, chan);
1327
1328 at91_adc_writel(st, CHER, BIT(chan->channel));
1329 }
1330
1331 if (at91_adc_buffer_check_use_irq(indio_dev, st))
1332 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);
1333
1334 pm_runtime_put:
1335 pm_runtime_mark_last_busy(st->dev);
1336 pm_runtime_put_autosuspend(st->dev);
1337 return ret;
1338 }
1339
1340 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
1341 {
1342 struct at91_adc_state *st = iio_priv(indio_dev);
1343 int ret;
1344 u8 bit;
1345
1346 /* check if we are disabling triggered buffer or the touchscreen */
1347 if (at91_adc_current_chan_is_touch(indio_dev))
1348 return at91_adc_configure_touch(st, false);
1349
1350 /* if we are not in triggered mode, nothing to do here */
1351 if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES))
1352 return -EINVAL;
1353
1354 ret = pm_runtime_resume_and_get(st->dev);
1355 if (ret < 0)
1356 return ret;
1357
1358 /*
1359 * For each enable channel we must disable it in hardware.
1360 * In the case of DMA, we must read the last converted value
1361 * to clear EOC status and not get a possible interrupt later.
1362 * This value is being read by DMA from LCDR anyway, so it's not lost.
1363 */
1364 for_each_set_bit(bit, indio_dev->active_scan_mask,
1365 indio_dev->num_channels) {
1366 struct iio_chan_spec const *chan =
1367 at91_adc_chan_get(indio_dev, bit);
1368
1369 if (!chan)
1370 continue;
1371 /* these channel types are virtual, no need to do anything */
1372 if (chan->type == IIO_POSITIONRELATIVE ||
1373 chan->type == IIO_PRESSURE ||
1374 chan->type == IIO_TEMP)
1375 continue;
1376
1377 at91_adc_writel(st, CHDR, BIT(chan->channel));
1378
1379 if (st->dma_st.dma_chan)
1380 at91_adc_read_chan(st, chan->address);
1381 }
1382
1383 if (at91_adc_buffer_check_use_irq(indio_dev, st))
1384 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);
1385
1386 /* read overflow register to clear possible overflow status */
1387 at91_adc_readl(st, OVER);
1388
1389 /* if we are using DMA we must clear registers and end DMA */
1390 if (st->dma_st.dma_chan)
1391 dmaengine_terminate_sync(st->dma_st.dma_chan);
1392
1393 pm_runtime_mark_last_busy(st->dev);
1394 pm_runtime_put_autosuspend(st->dev);
1395
1396 return 0;
1397 }
1398
1399 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
1400 .postdisable = &at91_adc_buffer_postdisable,
1401 };
1402
1403 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
1404 char *trigger_name)
1405 {
1406 struct iio_trigger *trig;
1407 int ret;
1408
1409 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
1410 iio_device_id(indio), trigger_name);
1411 if (!trig)
1412 return ERR_PTR(-ENOMEM);
1413
1414 trig->dev.parent = indio->dev.parent;
1415 iio_trigger_set_drvdata(trig, indio);
1416 trig->ops = &at91_adc_trigger_ops;
1417
1418 ret = devm_iio_trigger_register(&indio->dev, trig);
1419 if (ret)
1420 return ERR_PTR(ret);
1421
1422 return trig;
1423 }
1424
1425 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1426 struct iio_poll_func *pf)
1427 {
1428 struct at91_adc_state *st = iio_priv(indio_dev);
1429 int i = 0;
1430 int val;
1431 u8 bit;
1432 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
1433 unsigned int timeout = 50;
1434 u32 status, imr, eoc = 0, eoc_imr;
1435
1436 /*
1437 * Check if the conversion is ready. If not, wait a little bit, and
1438 * in case of timeout exit with an error.
1439 */
1440 while (((eoc & mask) != mask) && timeout) {
1441 at91_adc_irq_status(st, &status, &eoc);
1442 at91_adc_irq_mask(st, &imr, &eoc_imr);
1443 usleep_range(50, 100);
1444 timeout--;
1445 }
1446
1447 /* Cannot read data, not ready. Continue without reporting data */
1448 if (!timeout)
1449 return;
1450
1451 for_each_set_bit(bit, indio_dev->active_scan_mask,
1452 indio_dev->num_channels) {
1453 struct iio_chan_spec const *chan =
1454 at91_adc_chan_get(indio_dev, bit);
1455
1456 if (!chan)
1457 continue;
1458 /*
1459 * Our external trigger only supports the voltage channels.
1460 * In case someone requested a different type of channel
1461 * just put zeroes to buffer.
1462 * This should not happen because we check the scan mode
1463 * and scan mask when we enable the buffer, and we don't allow
1464 * the buffer to start with a mixed mask (voltage and something
1465 * else).
1466 * Thus, emit a warning.
1467 */
1468 if (chan->type == IIO_VOLTAGE) {
1469 val = at91_adc_read_chan(st, chan->address);
1470 at91_adc_adjust_val_osr(st, &val);
1471 st->buffer[i] = val;
1472 } else {
1473 st->buffer[i] = 0;
1474 WARN(true, "This trigger cannot handle this type of channel");
1475 }
1476 i++;
1477 }
1478 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1479 pf->timestamp);
1480 }
1481
1482 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1483 {
1484 struct at91_adc_state *st = iio_priv(indio_dev);
1485 int transferred_len = at91_adc_dma_size_done(st);
1486 s64 ns = iio_get_time_ns(indio_dev);
1487 s64 interval;
1488 int sample_index = 0, sample_count, sample_size;
1489
1490 u32 status = at91_adc_readl(st, ISR);
1491 /* if we reached this point, we cannot sample faster */
1492 if (status & AT91_SAMA5D2_IER_GOVRE)
1493 pr_info_ratelimited("%s: conversion overrun detected\n",
1494 indio_dev->name);
1495
1496 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1497
1498 sample_count = div_s64(transferred_len, sample_size);
1499
1500 /*
1501 * interval between samples is total time since last transfer handling
1502 * divided by the number of samples (total size divided by sample size)
1503 */
1504 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1505
1506 while (transferred_len >= sample_size) {
1507 /*
1508 * for all the values in the current sample,
1509 * adjust the values inside the buffer for oversampling
1510 */
1511 at91_adc_adjust_val_osr_array(st,
1512 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1513 sample_size);
1514
1515 iio_push_to_buffers_with_timestamp(indio_dev,
1516 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1517 (st->dma_st.dma_ts + interval * sample_index));
1518 /* adjust remaining length */
1519 transferred_len -= sample_size;
1520 /* adjust buffer index */
1521 st->dma_st.buf_idx += sample_size;
1522 /* in case of reaching end of buffer, reset index */
1523 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1524 st->dma_st.buf_idx = 0;
1525 sample_index++;
1526 }
1527 /* adjust saved time for next transfer handling */
1528 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1529 }
1530
1531 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1532 {
1533 struct iio_poll_func *pf = p;
1534 struct iio_dev *indio_dev = pf->indio_dev;
1535 struct at91_adc_state *st = iio_priv(indio_dev);
1536
1537 /*
1538 * If it's not our trigger, start a conversion now, as we are
1539 * actually polling the trigger now.
1540 */
1541 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
1542 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
1543
1544 if (st->dma_st.dma_chan)
1545 at91_adc_trigger_handler_dma(indio_dev);
1546 else
1547 at91_adc_trigger_handler_nodma(indio_dev, pf);
1548
1549 iio_trigger_notify_done(indio_dev->trig);
1550
1551 return IRQ_HANDLED;
1552 }
1553
1554 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1555 unsigned adc_clk_khz)
1556 {
1557 static const unsigned int startup_lookup[] = {
1558 0, 8, 16, 24,
1559 64, 80, 96, 112,
1560 512, 576, 640, 704,
1561 768, 832, 896, 960
1562 };
1563 unsigned ticks_min, i;
1564
1565 /*
1566 * Since the adc frequency is checked before, there is no reason
1567 * to not meet the startup time constraint.
1568 */
1569
1570 ticks_min = startup_time_min * adc_clk_khz / 1000;
1571 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1572 if (startup_lookup[i] > ticks_min)
1573 break;
1574
1575 return i;
1576 }
1577
1578 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq,
1579 unsigned int startup_time,
1580 unsigned int tracktim)
1581 {
1582 struct at91_adc_state *st = iio_priv(indio_dev);
1583 unsigned f_per, prescal, startup, mr;
1584 int ret;
1585
1586 f_per = clk_get_rate(st->per_clk);
1587 prescal = (f_per / (2 * freq)) - 1;
1588
1589 startup = at91_adc_startup_time(startup_time, freq / 1000);
1590
1591 ret = pm_runtime_resume_and_get(st->dev);
1592 if (ret < 0)
1593 return;
1594
1595 mr = at91_adc_readl(st, MR);
1596 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1597 mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1598 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1599 mr |= AT91_SAMA5D2_MR_TRACKTIM(tracktim);
1600 at91_adc_writel(st, MR, mr);
1601
1602 pm_runtime_mark_last_busy(st->dev);
1603 pm_runtime_put_autosuspend(st->dev);
1604
1605 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u, tracktim=%u\n",
1606 freq, startup, prescal, tracktim);
1607 st->current_sample_rate = freq;
1608 }
1609
1610 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1611 {
1612 return st->current_sample_rate;
1613 }
1614
1615 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1616 {
1617 struct at91_adc_state *st = iio_priv(indio_dev);
1618 u8 bit;
1619 u16 val;
1620 int i = 0;
1621
1622 for_each_set_bit(bit, indio_dev->active_scan_mask,
1623 st->soc_info.platform->max_index + 1) {
1624 struct iio_chan_spec const *chan =
1625 at91_adc_chan_get(indio_dev, bit);
1626
1627 if (chan->type == IIO_POSITIONRELATIVE)
1628 at91_adc_read_position(st, chan->channel, &val);
1629 else if (chan->type == IIO_PRESSURE)
1630 at91_adc_read_pressure(st, chan->channel, &val);
1631 else
1632 continue;
1633 st->buffer[i] = val;
1634 i++;
1635 }
1636 /*
1637 * Schedule work to push to buffers.
1638 * This is intended to push to the callback buffer that another driver
1639 * registered. We are still in a handler from our IRQ. If we push
1640 * directly, it means the other driver has it's callback called
1641 * from our IRQ context. Which is something we better avoid.
1642 * Let's schedule it after our IRQ is completed.
1643 */
1644 schedule_work(&st->touch_st.workq);
1645 }
1646
1647 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1648 {
1649 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);
1650 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |
1651 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1652 AT91_SAMA5D2_IER_PRDY);
1653 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1654 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1655 st->touch_st.touching = true;
1656 }
1657
1658 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
1659 {
1660 struct at91_adc_state *st = iio_priv(indio_dev);
1661
1662 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1663 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |
1664 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1665 AT91_SAMA5D2_IER_PRDY);
1666 st->touch_st.touching = false;
1667
1668 at91_adc_touch_data_handler(indio_dev);
1669
1670 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
1671 }
1672
1673 static void at91_adc_workq_handler(struct work_struct *workq)
1674 {
1675 struct at91_adc_touch *touch_st = container_of(workq,
1676 struct at91_adc_touch, workq);
1677 struct at91_adc_state *st = container_of(touch_st,
1678 struct at91_adc_state, touch_st);
1679 struct iio_dev *indio_dev = st->indio_dev;
1680
1681 iio_push_to_buffers(indio_dev, st->buffer);
1682 }
1683
1684 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1685 {
1686 struct iio_dev *indio = private;
1687 struct at91_adc_state *st = iio_priv(indio);
1688 u32 status, eoc, imr, eoc_imr;
1689 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1690 AT91_SAMA5D2_IER_PRDY;
1691
1692 at91_adc_irq_status(st, &status, &eoc);
1693 at91_adc_irq_mask(st, &imr, &eoc_imr);
1694
1695 if (!(status & imr) && !(eoc & eoc_imr))
1696 return IRQ_NONE;
1697 if (status & AT91_SAMA5D2_IER_PEN) {
1698 /* pen detected IRQ */
1699 at91_adc_pen_detect_interrupt(st);
1700 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1701 /* nopen detected IRQ */
1702 at91_adc_no_pen_detect_interrupt(indio);
1703 } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1704 ((status & rdy_mask) == rdy_mask)) {
1705 /* periodic trigger IRQ - during pen sense */
1706 at91_adc_touch_data_handler(indio);
1707 } else if (status & AT91_SAMA5D2_ISR_PENS) {
1708 /*
1709 * touching, but the measurements are not ready yet.
1710 * read and ignore.
1711 */
1712 status = at91_adc_readl(st, XPOSR);
1713 status = at91_adc_readl(st, YPOSR);
1714 status = at91_adc_readl(st, PRESSR);
1715 } else if (iio_buffer_enabled(indio) &&
1716 (status & AT91_SAMA5D2_IER_DRDY)) {
1717 /* triggered buffer without DMA */
1718 disable_irq_nosync(irq);
1719 iio_trigger_poll(indio->trig);
1720 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1721 /* triggered buffer with DMA - should not happen */
1722 disable_irq_nosync(irq);
1723 WARN(true, "Unexpected irq occurred\n");
1724 } else if (!iio_buffer_enabled(indio)) {
1725 /* software requested conversion */
1726 st->conversion_value = at91_adc_read_chan(st, st->chan->address);
1727 st->conversion_done = true;
1728 wake_up_interruptible(&st->wq_data_available);
1729 }
1730 return IRQ_HANDLED;
1731 }
1732
1733 /* This needs to be called with direct mode claimed and st->lock locked. */
1734 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1735 struct iio_chan_spec const *chan, int *val)
1736 {
1737 struct at91_adc_state *st = iio_priv(indio_dev);
1738 u16 tmp_val;
1739 int ret;
1740
1741 ret = pm_runtime_resume_and_get(st->dev);
1742 if (ret < 0)
1743 return ret;
1744
1745 /*
1746 * Keep in mind that we cannot use software trigger or touchscreen
1747 * if external trigger is enabled
1748 */
1749 if (chan->type == IIO_POSITIONRELATIVE) {
1750 ret = at91_adc_read_position(st, chan->channel,
1751 &tmp_val);
1752 *val = tmp_val;
1753 if (ret > 0)
1754 ret = at91_adc_adjust_val_osr(st, val);
1755
1756 goto pm_runtime_put;
1757 }
1758 if (chan->type == IIO_PRESSURE) {
1759 ret = at91_adc_read_pressure(st, chan->channel,
1760 &tmp_val);
1761 *val = tmp_val;
1762 if (ret > 0)
1763 ret = at91_adc_adjust_val_osr(st, val);
1764
1765 goto pm_runtime_put;
1766 }
1767
1768 /* in this case we have a voltage or temperature channel */
1769
1770 st->chan = chan;
1771
1772 at91_adc_cor(st, chan);
1773 at91_adc_writel(st, CHER, BIT(chan->channel));
1774 /*
1775 * TEMPMR.TEMPON needs to update after CHER otherwise if none
1776 * of the channels are enabled and TEMPMR.TEMPON = 1 will
1777 * trigger DRDY interruption while preparing for temperature read.
1778 */
1779 if (chan->type == IIO_TEMP)
1780 at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON);
1781 at91_adc_eoc_ena(st, chan->channel);
1782 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
1783
1784 ret = wait_event_interruptible_timeout(st->wq_data_available,
1785 st->conversion_done,
1786 msecs_to_jiffies(1000));
1787 if (ret == 0)
1788 ret = -ETIMEDOUT;
1789
1790 if (ret > 0) {
1791 *val = st->conversion_value;
1792 ret = at91_adc_adjust_val_osr(st, val);
1793 if (chan->scan_type.sign == 's')
1794 *val = sign_extend32(*val,
1795 chan->scan_type.realbits - 1);
1796 st->conversion_done = false;
1797 }
1798
1799 at91_adc_eoc_dis(st, st->chan->channel);
1800 if (chan->type == IIO_TEMP)
1801 at91_adc_writel(st, TEMPMR, 0U);
1802 at91_adc_writel(st, CHDR, BIT(chan->channel));
1803
1804 /* Needed to ACK the DRDY interruption */
1805 at91_adc_readl(st, LCDR);
1806
1807 pm_runtime_put:
1808 pm_runtime_mark_last_busy(st->dev);
1809 pm_runtime_put_autosuspend(st->dev);
1810 return ret;
1811 }
1812
1813 static int at91_adc_read_info_locked(struct iio_dev *indio_dev,
1814 struct iio_chan_spec const *chan, int *val)
1815 {
1816 struct at91_adc_state *st = iio_priv(indio_dev);
1817 int ret;
1818
1819 ret = iio_device_claim_direct_mode(indio_dev);
1820 if (ret)
1821 return ret;
1822
1823 mutex_lock(&st->lock);
1824 ret = at91_adc_read_info_raw(indio_dev, chan, val);
1825 mutex_unlock(&st->lock);
1826
1827 iio_device_release_direct_mode(indio_dev);
1828
1829 return ret;
1830 }
1831
1832 static void at91_adc_temp_sensor_configure(struct at91_adc_state *st,
1833 bool start)
1834 {
1835 u32 sample_rate, oversampling_ratio;
1836 u32 startup_time, tracktim, trackx;
1837
1838 if (start) {
1839 /*
1840 * Configure the sensor for best accuracy: 10MHz frequency,
1841 * oversampling rate of 256, tracktim=0xf and trackx=1.
1842 */
1843 sample_rate = 10 * MEGA;
1844 oversampling_ratio = 256;
1845 startup_time = AT91_SAMA5D2_MR_STARTUP_TS_MIN;
1846 tracktim = AT91_SAMA5D2_MR_TRACKTIM_TS;
1847 trackx = AT91_SAMA5D2_TRACKX_TS;
1848
1849 st->temp_st.saved_sample_rate = st->current_sample_rate;
1850 st->temp_st.saved_oversampling = st->oversampling_ratio;
1851 } else {
1852 /* Go back to previous settings. */
1853 sample_rate = st->temp_st.saved_sample_rate;
1854 oversampling_ratio = st->temp_st.saved_oversampling;
1855 startup_time = st->soc_info.startup_time;
1856 tracktim = 0;
1857 trackx = 0;
1858 }
1859
1860 at91_adc_setup_samp_freq(st->indio_dev, sample_rate, startup_time,
1861 tracktim);
1862 at91_adc_config_emr(st, oversampling_ratio, trackx);
1863 }
1864
1865 static int at91_adc_read_temp(struct iio_dev *indio_dev,
1866 struct iio_chan_spec const *chan, int *val)
1867 {
1868 struct at91_adc_state *st = iio_priv(indio_dev);
1869 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
1870 u64 div1, div2;
1871 u32 tmp;
1872 int ret, vbg, vtemp;
1873
1874 ret = iio_device_claim_direct_mode(indio_dev);
1875 if (ret)
1876 return ret;
1877 mutex_lock(&st->lock);
1878
1879 ret = pm_runtime_resume_and_get(st->dev);
1880 if (ret < 0)
1881 goto unlock;
1882
1883 at91_adc_temp_sensor_configure(st, true);
1884
1885 /* Read VBG. */
1886 tmp = at91_adc_readl(st, ACR);
1887 tmp |= AT91_SAMA5D2_ACR_SRCLCH;
1888 at91_adc_writel(st, ACR, tmp);
1889 ret = at91_adc_read_info_raw(indio_dev, chan, &vbg);
1890 if (ret < 0)
1891 goto restore_config;
1892
1893 /* Read VTEMP. */
1894 tmp &= ~AT91_SAMA5D2_ACR_SRCLCH;
1895 at91_adc_writel(st, ACR, tmp);
1896 ret = at91_adc_read_info_raw(indio_dev, chan, &vtemp);
1897
1898 restore_config:
1899 /* Revert previous settings. */
1900 at91_adc_temp_sensor_configure(st, false);
1901 pm_runtime_mark_last_busy(st->dev);
1902 pm_runtime_put_autosuspend(st->dev);
1903 unlock:
1904 mutex_unlock(&st->lock);
1905 iio_device_release_direct_mode(indio_dev);
1906 if (ret < 0)
1907 return ret;
1908
1909 /*
1910 * Temp[milli] = p1[milli] + (vtemp * clb->p6 - clb->p4 * vbg)/
1911 * (vbg * AT91_ADC_TS_VTEMP_DT)
1912 */
1913 div1 = DIV_ROUND_CLOSEST_ULL(((u64)vtemp * clb->p6), vbg);
1914 div1 = DIV_ROUND_CLOSEST_ULL((div1 * 1000), AT91_ADC_TS_VTEMP_DT);
1915 div2 = DIV_ROUND_CLOSEST_ULL((u64)clb->p4, AT91_ADC_TS_VTEMP_DT);
1916 div2 *= 1000;
1917 *val = clb->p1 + (int)div1 - (int)div2;
1918
1919 return ret;
1920 }
1921
1922 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1923 struct iio_chan_spec const *chan,
1924 int *val, int *val2, long mask)
1925 {
1926 struct at91_adc_state *st = iio_priv(indio_dev);
1927
1928 switch (mask) {
1929 case IIO_CHAN_INFO_RAW:
1930 return at91_adc_read_info_locked(indio_dev, chan, val);
1931
1932 case IIO_CHAN_INFO_SCALE:
1933 *val = st->vref_uv / 1000;
1934 if (chan->differential)
1935 *val *= 2;
1936 *val2 = chan->scan_type.realbits;
1937 return IIO_VAL_FRACTIONAL_LOG2;
1938
1939 case IIO_CHAN_INFO_PROCESSED:
1940 if (chan->type != IIO_TEMP)
1941 return -EINVAL;
1942 return at91_adc_read_temp(indio_dev, chan, val);
1943
1944 case IIO_CHAN_INFO_SAMP_FREQ:
1945 *val = at91_adc_get_sample_freq(st);
1946 return IIO_VAL_INT;
1947
1948 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1949 *val = st->oversampling_ratio;
1950 return IIO_VAL_INT;
1951
1952 default:
1953 return -EINVAL;
1954 }
1955 }
1956
1957 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1958 struct iio_chan_spec const *chan,
1959 int val, int val2, long mask)
1960 {
1961 struct at91_adc_state *st = iio_priv(indio_dev);
1962 int ret;
1963
1964 switch (mask) {
1965 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1966 /* if no change, optimize out */
1967 if (val == st->oversampling_ratio)
1968 return 0;
1969
1970 ret = iio_device_claim_direct_mode(indio_dev);
1971 if (ret)
1972 return ret;
1973 mutex_lock(&st->lock);
1974 /* update ratio */
1975 ret = at91_adc_config_emr(st, val, 0);
1976 mutex_unlock(&st->lock);
1977 iio_device_release_direct_mode(indio_dev);
1978 return ret;
1979 case IIO_CHAN_INFO_SAMP_FREQ:
1980 if (val < st->soc_info.min_sample_rate ||
1981 val > st->soc_info.max_sample_rate)
1982 return -EINVAL;
1983
1984 ret = iio_device_claim_direct_mode(indio_dev);
1985 if (ret)
1986 return ret;
1987 mutex_lock(&st->lock);
1988 at91_adc_setup_samp_freq(indio_dev, val,
1989 st->soc_info.startup_time, 0);
1990 mutex_unlock(&st->lock);
1991 iio_device_release_direct_mode(indio_dev);
1992 return 0;
1993 default:
1994 return -EINVAL;
1995 }
1996 }
1997
1998 static int at91_adc_read_avail(struct iio_dev *indio_dev,
1999 struct iio_chan_spec const *chan,
2000 const int **vals, int *type, int *length,
2001 long mask)
2002 {
2003 struct at91_adc_state *st = iio_priv(indio_dev);
2004
2005 switch (mask) {
2006 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
2007 *vals = (int *)st->soc_info.platform->oversampling_avail;
2008 *type = IIO_VAL_INT;
2009 *length = st->soc_info.platform->oversampling_avail_no;
2010 return IIO_AVAIL_LIST;
2011 default:
2012 return -EINVAL;
2013 }
2014 }
2015
2016 static void at91_adc_dma_init(struct at91_adc_state *st)
2017 {
2018 struct device *dev = &st->indio_dev->dev;
2019 struct dma_slave_config config = {0};
2020 /* we have 2 bytes for each channel */
2021 unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
2022 /*
2023 * We make the buffer double the size of the fifo,
2024 * such that DMA uses one half of the buffer (full fifo size)
2025 * and the software uses the other half to read/write.
2026 */
2027 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
2028 sample_size * 2, PAGE_SIZE);
2029
2030 if (st->dma_st.dma_chan)
2031 return;
2032
2033 st->dma_st.dma_chan = dma_request_chan(dev, "rx");
2034 if (IS_ERR(st->dma_st.dma_chan)) {
2035 dev_info(dev, "can't get DMA channel\n");
2036 st->dma_st.dma_chan = NULL;
2037 goto dma_exit;
2038 }
2039
2040 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
2041 pages * PAGE_SIZE,
2042 &st->dma_st.rx_dma_buf,
2043 GFP_KERNEL);
2044 if (!st->dma_st.rx_buf) {
2045 dev_info(dev, "can't allocate coherent DMA area\n");
2046 goto dma_chan_disable;
2047 }
2048
2049 /* Configure DMA channel to read data register */
2050 config.direction = DMA_DEV_TO_MEM;
2051 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
2052 + st->soc_info.platform->layout->LCDR);
2053 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
2054 config.src_maxburst = 1;
2055 config.dst_maxburst = 1;
2056
2057 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
2058 dev_info(dev, "can't configure DMA slave\n");
2059 goto dma_free_area;
2060 }
2061
2062 dev_info(dev, "using %s for rx DMA transfers\n",
2063 dma_chan_name(st->dma_st.dma_chan));
2064
2065 return;
2066
2067 dma_free_area:
2068 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
2069 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
2070 dma_chan_disable:
2071 dma_release_channel(st->dma_st.dma_chan);
2072 st->dma_st.dma_chan = NULL;
2073 dma_exit:
2074 dev_info(dev, "continuing without DMA support\n");
2075 }
2076
2077 static void at91_adc_dma_disable(struct at91_adc_state *st)
2078 {
2079 struct device *dev = &st->indio_dev->dev;
2080 /* we have 2 bytes for each channel */
2081 unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
2082 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
2083 sample_size * 2, PAGE_SIZE);
2084
2085 /* if we are not using DMA, just return */
2086 if (!st->dma_st.dma_chan)
2087 return;
2088
2089 /* wait for all transactions to be terminated first*/
2090 dmaengine_terminate_sync(st->dma_st.dma_chan);
2091
2092 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
2093 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
2094 dma_release_channel(st->dma_st.dma_chan);
2095 st->dma_st.dma_chan = NULL;
2096
2097 dev_info(dev, "continuing without DMA support\n");
2098 }
2099
2100 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
2101 {
2102 struct at91_adc_state *st = iio_priv(indio_dev);
2103 int ret;
2104
2105 if (val > AT91_HWFIFO_MAX_SIZE)
2106 val = AT91_HWFIFO_MAX_SIZE;
2107
2108 if (!st->selected_trig->hw_trig) {
2109 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
2110 return 0;
2111 }
2112
2113 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
2114 st->dma_st.watermark = val;
2115
2116 /*
2117 * The logic here is: if we have watermark 1, it means we do
2118 * each conversion with it's own IRQ, thus we don't need DMA.
2119 * If the watermark is higher, we do DMA to do all the transfers in bulk
2120 */
2121
2122 if (val == 1)
2123 at91_adc_dma_disable(st);
2124 else if (val > 1)
2125 at91_adc_dma_init(st);
2126
2127 /*
2128 * We can start the DMA only after setting the watermark and
2129 * having the DMA initialization completed
2130 */
2131 ret = at91_adc_buffer_prepare(indio_dev);
2132 if (ret)
2133 at91_adc_dma_disable(st);
2134
2135 return ret;
2136 }
2137
2138 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
2139 const unsigned long *scan_mask)
2140 {
2141 struct at91_adc_state *st = iio_priv(indio_dev);
2142
2143 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
2144 st->soc_info.platform->max_index + 1))
2145 return 0;
2146 /*
2147 * if the new bitmap is a combination of touchscreen and regular
2148 * channels, then we are not fine
2149 */
2150 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
2151 st->soc_info.platform->max_index + 1))
2152 return -EINVAL;
2153 return 0;
2154 }
2155
2156 static void at91_adc_hw_init(struct iio_dev *indio_dev)
2157 {
2158 struct at91_adc_state *st = iio_priv(indio_dev);
2159
2160 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
2161 if (st->soc_info.platform->layout->EOC_IDR)
2162 at91_adc_writel(st, EOC_IDR, 0xffffffff);
2163 at91_adc_writel(st, IDR, 0xffffffff);
2164 /*
2165 * Transfer field must be set to 2 according to the datasheet and
2166 * allows different analog settings for each channel.
2167 */
2168 at91_adc_writel(st, MR,
2169 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
2170
2171 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate,
2172 st->soc_info.startup_time, 0);
2173
2174 /* configure extended mode register */
2175 at91_adc_config_emr(st, st->oversampling_ratio, 0);
2176 }
2177
2178 static ssize_t at91_adc_get_fifo_state(struct device *dev,
2179 struct device_attribute *attr, char *buf)
2180 {
2181 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
2182 struct at91_adc_state *st = iio_priv(indio_dev);
2183
2184 return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan);
2185 }
2186
2187 static ssize_t at91_adc_get_watermark(struct device *dev,
2188 struct device_attribute *attr, char *buf)
2189 {
2190 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
2191 struct at91_adc_state *st = iio_priv(indio_dev);
2192
2193 return sysfs_emit(buf, "%d\n", st->dma_st.watermark);
2194 }
2195
2196 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
2197 at91_adc_get_fifo_state, NULL, 0);
2198 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
2199 at91_adc_get_watermark, NULL, 0);
2200
2201 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "2");
2202 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
2203
2204 static const struct iio_dev_attr *at91_adc_fifo_attributes[] = {
2205 &iio_dev_attr_hwfifo_watermark_min,
2206 &iio_dev_attr_hwfifo_watermark_max,
2207 &iio_dev_attr_hwfifo_watermark,
2208 &iio_dev_attr_hwfifo_enabled,
2209 NULL,
2210 };
2211
2212 static const struct iio_info at91_adc_info = {
2213 .read_avail = &at91_adc_read_avail,
2214 .read_raw = &at91_adc_read_raw,
2215 .write_raw = &at91_adc_write_raw,
2216 .update_scan_mode = &at91_adc_update_scan_mode,
2217 .fwnode_xlate = &at91_adc_fwnode_xlate,
2218 .hwfifo_set_watermark = &at91_adc_set_watermark,
2219 };
2220
2221 static int at91_adc_buffer_and_trigger_init(struct device *dev,
2222 struct iio_dev *indio)
2223 {
2224 struct at91_adc_state *st = iio_priv(indio);
2225 const struct iio_dev_attr **fifo_attrs;
2226 int ret;
2227
2228 if (st->selected_trig->hw_trig)
2229 fifo_attrs = at91_adc_fifo_attributes;
2230 else
2231 fifo_attrs = NULL;
2232
2233 ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio,
2234 &iio_pollfunc_store_time, &at91_adc_trigger_handler,
2235 IIO_BUFFER_DIRECTION_IN, &at91_buffer_setup_ops, fifo_attrs);
2236 if (ret < 0) {
2237 dev_err(dev, "couldn't initialize the buffer.\n");
2238 return ret;
2239 }
2240
2241 if (!st->selected_trig->hw_trig)
2242 return 0;
2243
2244 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
2245 if (IS_ERR(st->trig)) {
2246 dev_err(dev, "could not allocate trigger\n");
2247 return PTR_ERR(st->trig);
2248 }
2249
2250 /*
2251 * Initially the iio buffer has a length of 2 and
2252 * a watermark of 1
2253 */
2254 st->dma_st.watermark = 1;
2255
2256 return 0;
2257 }
2258
2259 static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
2260 struct device *dev)
2261 {
2262 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
2263 struct nvmem_cell *temp_calib;
2264 u32 *buf;
2265 size_t len;
2266 int ret = 0;
2267
2268 if (!st->soc_info.platform->temp_sensor)
2269 return 0;
2270
2271 /* Get the calibration data from NVMEM. */
2272 temp_calib = devm_nvmem_cell_get(dev, "temperature_calib");
2273 if (IS_ERR(temp_calib)) {
2274 ret = PTR_ERR(temp_calib);
2275 if (ret != -ENOENT)
2276 dev_err(dev, "Failed to get temperature_calib cell!\n");
2277 return ret;
2278 }
2279
2280 buf = nvmem_cell_read(temp_calib, &len);
2281 if (IS_ERR(buf)) {
2282 dev_err(dev, "Failed to read calibration data!\n");
2283 return PTR_ERR(buf);
2284 }
2285 if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) {
2286 dev_err(dev, "Invalid calibration data!\n");
2287 ret = -EINVAL;
2288 goto free_buf;
2289 }
2290
2291 /* Store calibration data for later use. */
2292 clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1];
2293 clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4];
2294 clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6];
2295
2296 /*
2297 * We prepare here the conversion to milli to avoid doing it on hotpath.
2298 */
2299 clb->p1 = clb->p1 * 1000;
2300
2301 free_buf:
2302 kfree(buf);
2303 return ret;
2304 }
2305
2306 static int at91_adc_probe(struct platform_device *pdev)
2307 {
2308 struct device *dev = &pdev->dev;
2309 struct iio_dev *indio_dev;
2310 struct at91_adc_state *st;
2311 struct resource *res;
2312 int ret, i, num_channels;
2313 u32 edge_type = IRQ_TYPE_NONE;
2314
2315 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
2316 if (!indio_dev)
2317 return -ENOMEM;
2318
2319 st = iio_priv(indio_dev);
2320 st->indio_dev = indio_dev;
2321
2322 st->soc_info.platform = device_get_match_data(dev);
2323
2324 ret = at91_adc_temp_sensor_init(st, &pdev->dev);
2325 /* Don't register temperature channel if initialization failed. */
2326 if (ret)
2327 num_channels = st->soc_info.platform->max_channels - 1;
2328 else
2329 num_channels = st->soc_info.platform->max_channels;
2330
2331 indio_dev->name = dev_name(&pdev->dev);
2332 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
2333 indio_dev->info = &at91_adc_info;
2334 indio_dev->channels = *st->soc_info.platform->adc_channels;
2335 indio_dev->num_channels = num_channels;
2336
2337 bitmap_set(&st->touch_st.channels_bitmask,
2338 st->soc_info.platform->touch_chan_x, 1);
2339 bitmap_set(&st->touch_st.channels_bitmask,
2340 st->soc_info.platform->touch_chan_y, 1);
2341 bitmap_set(&st->touch_st.channels_bitmask,
2342 st->soc_info.platform->touch_chan_p, 1);
2343
2344 st->oversampling_ratio = 1;
2345
2346 ret = device_property_read_u32(dev, "atmel,min-sample-rate-hz",
2347 &st->soc_info.min_sample_rate);
2348 if (ret) {
2349 dev_err(&pdev->dev,
2350 "invalid or missing value for atmel,min-sample-rate-hz\n");
2351 return ret;
2352 }
2353
2354 ret = device_property_read_u32(dev, "atmel,max-sample-rate-hz",
2355 &st->soc_info.max_sample_rate);
2356 if (ret) {
2357 dev_err(&pdev->dev,
2358 "invalid or missing value for atmel,max-sample-rate-hz\n");
2359 return ret;
2360 }
2361
2362 ret = device_property_read_u32(dev, "atmel,startup-time-ms",
2363 &st->soc_info.startup_time);
2364 if (ret) {
2365 dev_err(&pdev->dev,
2366 "invalid or missing value for atmel,startup-time-ms\n");
2367 return ret;
2368 }
2369
2370 ret = device_property_read_u32(dev, "atmel,trigger-edge-type",
2371 &edge_type);
2372 if (ret) {
2373 dev_dbg(&pdev->dev,
2374 "atmel,trigger-edge-type not specified, only software trigger available\n");
2375 }
2376
2377 st->selected_trig = NULL;
2378
2379 /* find the right trigger, or no trigger at all */
2380 for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++)
2381 if (at91_adc_trigger_list[i].edge_type == edge_type) {
2382 st->selected_trig = &at91_adc_trigger_list[i];
2383 break;
2384 }
2385
2386 if (!st->selected_trig) {
2387 dev_err(&pdev->dev, "invalid external trigger edge value\n");
2388 return -EINVAL;
2389 }
2390
2391 init_waitqueue_head(&st->wq_data_available);
2392 mutex_init(&st->lock);
2393 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
2394
2395 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2396 if (IS_ERR(st->base))
2397 return PTR_ERR(st->base);
2398
2399 /* if we plan to use DMA, we need the physical address of the regs */
2400 st->dma_st.phys_addr = res->start;
2401
2402 st->irq = platform_get_irq(pdev, 0);
2403 if (st->irq < 0)
2404 return st->irq;
2405
2406 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
2407 if (IS_ERR(st->per_clk))
2408 return PTR_ERR(st->per_clk);
2409
2410 st->reg = devm_regulator_get(&pdev->dev, "vddana");
2411 if (IS_ERR(st->reg))
2412 return PTR_ERR(st->reg);
2413
2414 st->vref = devm_regulator_get(&pdev->dev, "vref");
2415 if (IS_ERR(st->vref))
2416 return PTR_ERR(st->vref);
2417
2418 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
2419 pdev->dev.driver->name, indio_dev);
2420 if (ret)
2421 return ret;
2422
2423 ret = regulator_enable(st->reg);
2424 if (ret)
2425 return ret;
2426
2427 ret = regulator_enable(st->vref);
2428 if (ret)
2429 goto reg_disable;
2430
2431 st->vref_uv = regulator_get_voltage(st->vref);
2432 if (st->vref_uv <= 0) {
2433 ret = -EINVAL;
2434 goto vref_disable;
2435 }
2436
2437 ret = clk_prepare_enable(st->per_clk);
2438 if (ret)
2439 goto vref_disable;
2440
2441 platform_set_drvdata(pdev, indio_dev);
2442 st->dev = &pdev->dev;
2443 pm_runtime_set_autosuspend_delay(st->dev, 500);
2444 pm_runtime_use_autosuspend(st->dev);
2445 pm_runtime_set_active(st->dev);
2446 pm_runtime_enable(st->dev);
2447 pm_runtime_get_noresume(st->dev);
2448
2449 at91_adc_hw_init(indio_dev);
2450
2451 ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev);
2452 if (ret < 0)
2453 goto err_pm_disable;
2454
2455 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
2456 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
2457
2458 ret = iio_device_register(indio_dev);
2459 if (ret < 0)
2460 goto dma_disable;
2461
2462 if (st->selected_trig->hw_trig)
2463 dev_info(&pdev->dev, "setting up trigger as %s\n",
2464 st->selected_trig->name);
2465
2466 dev_info(&pdev->dev, "version: %x\n",
2467 readl_relaxed(st->base + st->soc_info.platform->layout->VERSION));
2468
2469 pm_runtime_mark_last_busy(st->dev);
2470 pm_runtime_put_autosuspend(st->dev);
2471
2472 return 0;
2473
2474 dma_disable:
2475 at91_adc_dma_disable(st);
2476 err_pm_disable:
2477 pm_runtime_put_noidle(st->dev);
2478 pm_runtime_disable(st->dev);
2479 pm_runtime_set_suspended(st->dev);
2480 pm_runtime_dont_use_autosuspend(st->dev);
2481 clk_disable_unprepare(st->per_clk);
2482 vref_disable:
2483 regulator_disable(st->vref);
2484 reg_disable:
2485 regulator_disable(st->reg);
2486 return ret;
2487 }
2488
2489 static void at91_adc_remove(struct platform_device *pdev)
2490 {
2491 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
2492 struct at91_adc_state *st = iio_priv(indio_dev);
2493
2494 iio_device_unregister(indio_dev);
2495
2496 at91_adc_dma_disable(st);
2497
2498 pm_runtime_disable(st->dev);
2499 pm_runtime_set_suspended(st->dev);
2500 clk_disable_unprepare(st->per_clk);
2501
2502 regulator_disable(st->vref);
2503 regulator_disable(st->reg);
2504 }
2505
2506 static int at91_adc_suspend(struct device *dev)
2507 {
2508 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2509 struct at91_adc_state *st = iio_priv(indio_dev);
2510 int ret;
2511
2512 ret = pm_runtime_resume_and_get(st->dev);
2513 if (ret < 0)
2514 return ret;
2515
2516 if (iio_buffer_enabled(indio_dev))
2517 at91_adc_buffer_postdisable(indio_dev);
2518
2519 /*
2520 * Do a sofware reset of the ADC before we go to suspend.
2521 * this will ensure that all pins are free from being muxed by the ADC
2522 * and can be used by for other devices.
2523 * Otherwise, ADC will hog them and we can't go to suspend mode.
2524 */
2525 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
2526
2527 pm_runtime_mark_last_busy(st->dev);
2528 pm_runtime_put_noidle(st->dev);
2529 clk_disable_unprepare(st->per_clk);
2530 regulator_disable(st->vref);
2531 regulator_disable(st->reg);
2532
2533 return pinctrl_pm_select_sleep_state(dev);
2534 }
2535
2536 static int at91_adc_resume(struct device *dev)
2537 {
2538 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2539 struct at91_adc_state *st = iio_priv(indio_dev);
2540 int ret;
2541
2542 ret = pinctrl_pm_select_default_state(dev);
2543 if (ret)
2544 goto resume_failed;
2545
2546 ret = regulator_enable(st->reg);
2547 if (ret)
2548 goto resume_failed;
2549
2550 ret = regulator_enable(st->vref);
2551 if (ret)
2552 goto reg_disable_resume;
2553
2554 ret = clk_prepare_enable(st->per_clk);
2555 if (ret)
2556 goto vref_disable_resume;
2557
2558 pm_runtime_get_noresume(st->dev);
2559
2560 at91_adc_hw_init(indio_dev);
2561
2562 /* reconfiguring trigger hardware state */
2563 if (iio_buffer_enabled(indio_dev)) {
2564 ret = at91_adc_buffer_prepare(indio_dev);
2565 if (ret)
2566 goto pm_runtime_put;
2567
2568 at91_adc_configure_trigger_registers(st, true);
2569 }
2570
2571 pm_runtime_mark_last_busy(st->dev);
2572 pm_runtime_put_autosuspend(st->dev);
2573
2574 return 0;
2575
2576 pm_runtime_put:
2577 pm_runtime_mark_last_busy(st->dev);
2578 pm_runtime_put_noidle(st->dev);
2579 clk_disable_unprepare(st->per_clk);
2580 vref_disable_resume:
2581 regulator_disable(st->vref);
2582 reg_disable_resume:
2583 regulator_disable(st->reg);
2584 resume_failed:
2585 dev_err(&indio_dev->dev, "failed to resume\n");
2586 return ret;
2587 }
2588
2589 static int at91_adc_runtime_suspend(struct device *dev)
2590 {
2591 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2592 struct at91_adc_state *st = iio_priv(indio_dev);
2593
2594 clk_disable(st->per_clk);
2595
2596 return 0;
2597 }
2598
2599 static int at91_adc_runtime_resume(struct device *dev)
2600 {
2601 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2602 struct at91_adc_state *st = iio_priv(indio_dev);
2603
2604 return clk_enable(st->per_clk);
2605 }
2606
2607 static const struct dev_pm_ops at91_adc_pm_ops = {
2608 SYSTEM_SLEEP_PM_OPS(at91_adc_suspend, at91_adc_resume)
2609 RUNTIME_PM_OPS(at91_adc_runtime_suspend, at91_adc_runtime_resume,
2610 NULL)
2611 };
2612
2613 static const struct of_device_id at91_adc_dt_match[] = {
2614 {
2615 .compatible = "atmel,sama5d2-adc",
2616 .data = (const void *)&sama5d2_platform,
2617 }, {
2618 .compatible = "microchip,sama7g5-adc",
2619 .data = (const void *)&sama7g5_platform,
2620 }, {
2621 /* sentinel */
2622 }
2623 };
2624 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
2625
2626 static struct platform_driver at91_adc_driver = {
2627 .probe = at91_adc_probe,
2628 .remove = at91_adc_remove,
2629 .driver = {
2630 .name = "at91-sama5d2_adc",
2631 .of_match_table = at91_adc_dt_match,
2632 .pm = pm_ptr(&at91_adc_pm_ops),
2633 },
2634 };
2635 module_platform_driver(at91_adc_driver)
2636
2637 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@microchip.com>");
2638 MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com");
2639 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
2640 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes