drivers/iio/adc/cc10001_adc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2015 Imagination Technologies Ltd.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regulator/consumer.h>
  14 #include <linux/slab.h>
  15
  16 #include <linux/iio/buffer.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/iio/trigger.h>
  20 #include <linux/iio/trigger_consumer.h>
  21 #include <linux/iio/triggered_buffer.h>
  22
  23 /* Registers */
  24 #define CC10001_ADC_CONFIG              0x00
  25 #define CC10001_ADC_START_CONV          BIT(4)
  26 #define CC10001_ADC_MODE_SINGLE_CONV    BIT(5)
  27
  28 #define CC10001_ADC_DDATA_OUT           0x04
  29 #define CC10001_ADC_EOC                 0x08
  30 #define CC10001_ADC_EOC_SET             BIT(0)
  31
  32 #define CC10001_ADC_CHSEL_SAMPLED       0x0c
  33 #define CC10001_ADC_POWER_DOWN          0x10
  34 #define CC10001_ADC_POWER_DOWN_SET      BIT(0)
  35
  36 #define CC10001_ADC_DEBUG               0x14
  37 #define CC10001_ADC_DATA_COUNT          0x20
  38
  39 #define CC10001_ADC_DATA_MASK           GENMASK(9, 0)
  40 #define CC10001_ADC_NUM_CHANNELS        8
  41 #define CC10001_ADC_CH_MASK             GENMASK(2, 0)
  42
  43 #define CC10001_INVALID_SAMPLED         0xffff
  44 #define CC10001_MAX_POLL_COUNT          20
  45
  46 /*
  47  * As per device specification, wait six clock cycles after power-up to
  48  * activate START. Since adding two more clock cycles delay does not
  49  * impact the performance too much, we are adding two additional cycles delay
  50  * intentionally here.
  51  */
  52 #define CC10001_WAIT_CYCLES             8
  53
  54 struct cc10001_adc_device {
  55         void __iomem *reg_base;
  56         struct clk *adc_clk;
  57         struct regulator *reg;
  58         u16 *buf;
  59
  60         bool shared;
  61         struct mutex lock;
  62         unsigned int start_delay_ns;
  63         unsigned int eoc_delay_ns;
  64 };
  65
  66 static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
  67                                          u32 reg, u32 val)
  68 {
  69         writel(val, adc_dev->reg_base + reg);
  70 }
  71
  72 static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
  73                                        u32 reg)
  74 {
  75         return readl(adc_dev->reg_base + reg);
  76 }
  77
  78 static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
  79 {
  80         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
  81         ndelay(adc_dev->start_delay_ns);
  82 }
  83
  84 static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
  85 {
  86         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
  87                               CC10001_ADC_POWER_DOWN_SET);
  88 }
  89
  90 static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
  91                               unsigned int channel)
  92 {
  93         u32 val;
  94
  95         /* Channel selection and mode of operation */
  96         val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
  97         cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
  98
  99         udelay(1);
 100         val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
 101         val = val | CC10001_ADC_START_CONV;
 102         cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
 103 }
 104
 105 static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
 106                                  unsigned int channel,
 107                                  unsigned int delay)
 108 {
 109         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 110         unsigned int poll_count = 0;
 111
 112         while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
 113                         CC10001_ADC_EOC_SET)) {
 114
 115                 ndelay(delay);
 116                 if (poll_count++ == CC10001_MAX_POLL_COUNT)
 117                         return CC10001_INVALID_SAMPLED;
 118         }
 119
 120         poll_count = 0;
 121         while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
 122                         CC10001_ADC_CH_MASK) != channel) {
 123
 124                 ndelay(delay);
 125                 if (poll_count++ == CC10001_MAX_POLL_COUNT)
 126                         return CC10001_INVALID_SAMPLED;
 127         }
 128
 129         /* Read the 10 bit output register */
 130         return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
 131                                CC10001_ADC_DATA_MASK;
 132 }
 133
 134 static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
 135 {
 136         struct cc10001_adc_device *adc_dev;
 137         struct iio_poll_func *pf = p;
 138         struct iio_dev *indio_dev;
 139         unsigned int delay_ns;
 140         unsigned int channel;
 141         unsigned int scan_idx;
 142         bool sample_invalid;
 143         u16 *data;
 144         int i;
 145
 146         indio_dev = pf->indio_dev;
 147         adc_dev = iio_priv(indio_dev);
 148         data = adc_dev->buf;
 149
 150         mutex_lock(&adc_dev->lock);
 151
 152         if (!adc_dev->shared)
 153                 cc10001_adc_power_up(adc_dev);
 154
 155         /* Calculate delay step for eoc and sampled data */
 156         delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
 157
 158         i = 0;
 159         sample_invalid = false;
 160         iio_for_each_active_channel(indio_dev, scan_idx) {
 161                 channel = indio_dev->channels[scan_idx].channel;
 162                 cc10001_adc_start(adc_dev, channel);
 163
 164                 data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
 165                 if (data[i] == CC10001_INVALID_SAMPLED) {
 166                         dev_warn(&indio_dev->dev,
 167                                  "invalid sample on channel %d\n", channel);
 168                         sample_invalid = true;
 169                         goto done;
 170                 }
 171                 i++;
 172         }
 173
 174 done:
 175         if (!adc_dev->shared)
 176                 cc10001_adc_power_down(adc_dev);
 177
 178         mutex_unlock(&adc_dev->lock);
 179
 180         if (!sample_invalid)
 181                 iio_push_to_buffers_with_timestamp(indio_dev, data,
 182                                                    iio_get_time_ns(indio_dev));
 183         iio_trigger_notify_done(indio_dev->trig);
 184
 185         return IRQ_HANDLED;
 186 }
 187
 188 static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
 189                                         struct iio_chan_spec const *chan)
 190 {
 191         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 192         unsigned int delay_ns;
 193         u16 val;
 194
 195         if (!adc_dev->shared)
 196                 cc10001_adc_power_up(adc_dev);
 197
 198         /* Calculate delay step for eoc and sampled data */
 199         delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
 200
 201         cc10001_adc_start(adc_dev, chan->channel);
 202
 203         val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
 204
 205         if (!adc_dev->shared)
 206                 cc10001_adc_power_down(adc_dev);
 207
 208         return val;
 209 }
 210
 211 static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
 212                                  struct iio_chan_spec const *chan,
 213                                  int *val, int *val2, long mask)
 214 {
 215         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 216         int ret;
 217
 218         switch (mask) {
 219         case IIO_CHAN_INFO_RAW:
 220                 if (iio_buffer_enabled(indio_dev))
 221                         return -EBUSY;
 222                 mutex_lock(&adc_dev->lock);
 223                 *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
 224                 mutex_unlock(&adc_dev->lock);
 225
 226                 if (*val == CC10001_INVALID_SAMPLED)
 227                         return -EIO;
 228                 return IIO_VAL_INT;
 229
 230         case IIO_CHAN_INFO_SCALE:
 231                 ret = regulator_get_voltage(adc_dev->reg);
 232                 if (ret < 0)
 233                         return ret;
 234
 235                 *val = ret / 1000;
 236                 *val2 = chan->scan_type.realbits;
 237                 return IIO_VAL_FRACTIONAL_LOG2;
 238
 239         default:
 240                 return -EINVAL;
 241         }
 242 }
 243
 244 static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
 245                                     const unsigned long *scan_mask)
 246 {
 247         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 248
 249         kfree(adc_dev->buf);
 250         adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
 251         if (!adc_dev->buf)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static const struct iio_info cc10001_adc_info = {
 258         .read_raw = &cc10001_adc_read_raw,
 259         .update_scan_mode = &cc10001_update_scan_mode,
 260 };
 261
 262 static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
 263                                     unsigned long channel_map)
 264 {
 265         struct iio_chan_spec *chan_array, *timestamp;
 266         unsigned int bit, idx = 0;
 267
 268         indio_dev->num_channels = bitmap_weight(&channel_map,
 269                                                 CC10001_ADC_NUM_CHANNELS) + 1;
 270
 271         chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
 272                                   sizeof(struct iio_chan_spec),
 273                                   GFP_KERNEL);
 274         if (!chan_array)
 275                 return -ENOMEM;
 276
 277         for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
 278                 struct iio_chan_spec *chan = &chan_array[idx];
 279
 280                 chan->type = IIO_VOLTAGE;
 281                 chan->indexed = 1;
 282                 chan->channel = bit;
 283                 chan->scan_index = idx;
 284                 chan->scan_type.sign = 'u';
 285                 chan->scan_type.realbits = 10;
 286                 chan->scan_type.storagebits = 16;
 287                 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
 288                 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 289                 idx++;
 290         }
 291
 292         timestamp = &chan_array[idx];
 293         timestamp->type = IIO_TIMESTAMP;
 294         timestamp->channel = -1;
 295         timestamp->scan_index = idx;
 296         timestamp->scan_type.sign = 's';
 297         timestamp->scan_type.realbits = 64;
 298         timestamp->scan_type.storagebits = 64;
 299
 300         indio_dev->channels = chan_array;
 301
 302         return 0;
 303 }
 304
 305 static void cc10001_reg_disable(void *priv)
 306 {
 307         regulator_disable(priv);
 308 }
 309
 310 static void cc10001_pd_cb(void *priv)
 311 {
 312         cc10001_adc_power_down(priv);
 313 }
 314
 315 static int cc10001_adc_probe(struct platform_device *pdev)
 316 {
 317         struct device *dev = &pdev->dev;
 318         struct device_node *node = dev->of_node;
 319         struct cc10001_adc_device *adc_dev;
 320         unsigned long adc_clk_rate;
 321         struct iio_dev *indio_dev;
 322         unsigned long channel_map;
 323         int ret;
 324
 325         indio_dev = devm_iio_device_alloc(dev, sizeof(*adc_dev));
 326         if (indio_dev == NULL)
 327                 return -ENOMEM;
 328
 329         adc_dev = iio_priv(indio_dev);
 330
 331         channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
 332         if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
 333                 adc_dev->shared = true;
 334                 channel_map &= ~ret;
 335         }
 336
 337         adc_dev->reg = devm_regulator_get(dev, "vref");
 338         if (IS_ERR(adc_dev->reg))
 339                 return PTR_ERR(adc_dev->reg);
 340
 341         ret = regulator_enable(adc_dev->reg);
 342         if (ret)
 343                 return ret;
 344
 345         ret = devm_add_action_or_reset(dev, cc10001_reg_disable, adc_dev->reg);
 346         if (ret)
 347                 return ret;
 348
 349         indio_dev->name = dev_name(dev);
 350         indio_dev->info = &cc10001_adc_info;
 351         indio_dev->modes = INDIO_DIRECT_MODE;
 352
 353         adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
 354         if (IS_ERR(adc_dev->reg_base))
 355                 return PTR_ERR(adc_dev->reg_base);
 356
 357         adc_dev->adc_clk = devm_clk_get_enabled(dev, "adc");
 358         if (IS_ERR(adc_dev->adc_clk)) {
 359                 dev_err(dev, "failed to get/enable the clock\n");
 360                 return PTR_ERR(adc_dev->adc_clk);
 361         }
 362
 363         adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
 364         if (!adc_clk_rate) {
 365                 dev_err(dev, "null clock rate!\n");
 366                 return -EINVAL;
 367         }
 368
 369         adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
 370         adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
 371
 372         /*
 373          * There is only one register to power-up/power-down the AUX ADC.
 374          * If the ADC is shared among multiple CPUs, always power it up here.
 375          * If the ADC is used only by the MIPS, power-up/power-down at runtime.
 376          */
 377         if (adc_dev->shared)
 378                 cc10001_adc_power_up(adc_dev);
 379
 380         ret = devm_add_action_or_reset(dev, cc10001_pd_cb, adc_dev);
 381         if (ret)
 382                 return ret;
 383         /* Setup the ADC channels available on the device */
 384         ret = cc10001_adc_channel_init(indio_dev, channel_map);
 385         if (ret < 0)
 386                 return ret;
 387
 388         mutex_init(&adc_dev->lock);
 389
 390         ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
 391                                               &cc10001_adc_trigger_h, NULL);
 392         if (ret < 0)
 393                 return ret;
 394
 395         return devm_iio_device_register(dev, indio_dev);
 396 }
 397
 398 static const struct of_device_id cc10001_adc_dt_ids[] = {
 399         { .compatible = "cosmic,10001-adc", },
 400         { }
 401 };
 402 MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
 403
 404 static struct platform_driver cc10001_adc_driver = {
 405         .driver = {
 406                 .name   = "cc10001-adc",
 407                 .of_match_table = cc10001_adc_dt_ids,
 408         },
 409         .probe  = cc10001_adc_probe,
 410 };
 411 module_platform_driver(cc10001_adc_driver);
 412
 413 MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
 414 MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
 415 MODULE_LICENSE("GPL v2");