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drm/client: Fix drm client endless Kconfig loop
[drm/drm-misc.git] / drivers / iio / adc / max1363.c
blob9a0baea08ab6162b024932f3f65c8a68d156672d
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * iio/adc/max1363.c
4 * Copyright (C) 2008-2010 Jonathan Cameron
5 *
6 * based on linux/drivers/i2c/chips/max123x
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
8 *
9 * based on linux/drivers/acron/char/pcf8583.c
10 * Copyright (C) 2000 Russell King
11 *
12 * Driver for max1363 and similar chips.
13 */
14
15 #include <linux/interrupt.h>
16 #include <linux/cleanup.h>
17 #include <linux/device.h>
18 #include <linux/kernel.h>
19 #include <linux/sysfs.h>
20 #include <linux/list.h>
21 #include <linux/i2c.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/property.h>
28 #include <linux/unaligned.h>
29
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/events.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/kfifo_buf.h>
35 #include <linux/iio/trigger_consumer.h>
36 #include <linux/iio/triggered_buffer.h>
37
38 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
39
40 /* There is a fair bit more defined here than currently
41 * used, but the intention is to support everything these
42 * chips do in the long run */
43
44 /* see data sheets */
45 /* max1363 and max1236, max1237, max1238, max1239 */
46 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
47 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
48 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
49 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
50 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
51 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
52
53 /* think about including max11600 etc - more settings */
54 #define MAX1363_SETUP_EXT_CLOCK 0x08
55 #define MAX1363_SETUP_INT_CLOCK 0x00
56 #define MAX1363_SETUP_UNIPOLAR 0x00
57 #define MAX1363_SETUP_BIPOLAR 0x04
58 #define MAX1363_SETUP_RESET 0x00
59 #define MAX1363_SETUP_NORESET 0x02
60 /* max1363 only - though don't care on others.
61 * For now monitor modes are not implemented as the relevant
62 * line is not connected on my test board.
63 * The definitions are here as I intend to add this soon.
64 */
65 #define MAX1363_SETUP_MONITOR_SETUP 0x01
66
67 /* Specific to the max1363 */
68 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
69 #define MAX1363_MON_INT_ENABLE 0x01
70
71 /* defined for readability reasons */
72 /* All chips */
73 #define MAX1363_CONFIG_BYTE(a) ((a))
74
75 #define MAX1363_CONFIG_SE 0x01
76 #define MAX1363_CONFIG_DE 0x00
77 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
78 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
79 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
80 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
81 /* max123{6-9} only */
82 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
83
84 /* max1363 only - merely part of channel selects or don't care for others */
85 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
86
87 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
88
89 /* max1363 strictly 0x06 - but doesn't matter */
90 #define MAX1363_CHANNEL_SEL_MASK 0x1E
91 #define MAX1363_SCAN_MASK 0x60
92 #define MAX1363_SE_DE_MASK 0x01
93
94 #define MAX1363_MAX_CHANNELS 25
95 /**
96 * struct max1363_mode - scan mode information
97 * @conf: The corresponding value of the configuration register
98 * @modemask: Bit mask corresponding to channels enabled in this mode
99 */
100 struct max1363_mode {
101 int8_t conf;
102 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
103 };
104
105 /* This must be maintained along side the max1363_mode_table in max1363_core */
106 enum max1363_modes {
107 /* Single read of a single channel */
108 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
109 /* Differential single read */
110 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
111 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
112 /* Scan to channel and mid to channel where overlapping */
113 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
114 s6to7, s0to7, s6to8, s0to8, s6to9,
115 s0to9, s6to10, s0to10, s6to11, s0to11,
116 /* Differential scan to channel and mid to channel where overlapping */
117 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
118 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
119 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
120 d7m6to11m10, d1m0to11m10,
121 };
122
123 /**
124 * struct max1363_chip_info - chip specifc information
125 * @info: iio core function callbacks structure
126 * @channels: channel specification
127 * @num_channels: number of channels
128 * @mode_list: array of available scan modes
129 * @default_mode: the scan mode in which the chip starts up
130 * @int_vref_mv: the internal reference voltage
131 * @num_modes: number of modes
132 * @bits: accuracy of the adc in bits
133 */
134 struct max1363_chip_info {
135 const struct iio_info *info;
136 const struct iio_chan_spec *channels;
137 int num_channels;
138 const enum max1363_modes *mode_list;
139 enum max1363_modes default_mode;
140 u16 int_vref_mv;
141 u8 num_modes;
142 u8 bits;
143 };
144
145 /**
146 * struct max1363_state - driver instance specific data
147 * @client: i2c_client
148 * @setupbyte: cache of current device setup byte
149 * @configbyte: cache of current device config byte
150 * @chip_info: chip model specific constants, available modes, etc.
151 * @current_mode: the scan mode of this chip
152 * @requestedmask: a valid requested set of channels
153 * @lock: lock to ensure state is consistent
154 * @monitor_on: whether monitor mode is enabled
155 * @monitor_speed: parameter corresponding to device monitor speed setting
156 * @mask_high: bitmask for enabled high thresholds
157 * @mask_low: bitmask for enabled low thresholds
158 * @thresh_high: high threshold values
159 * @thresh_low: low threshold values
160 * @vref: Reference voltage regulator
161 * @vref_uv: Actual (external or internal) reference voltage
162 * @send: function used to send data to the chip
163 * @recv: function used to receive data from the chip
164 */
165 struct max1363_state {
166 struct i2c_client *client;
167 u8 setupbyte;
168 u8 configbyte;
169 const struct max1363_chip_info *chip_info;
170 const struct max1363_mode *current_mode;
171 u32 requestedmask;
172 struct mutex lock;
173
174 /* Using monitor modes and buffer at the same time is
175 currently not supported */
176 bool monitor_on;
177 unsigned int monitor_speed:3;
178 u8 mask_high;
179 u8 mask_low;
180 /* 4x unipolar first then the fours bipolar ones */
181 s16 thresh_high[8];
182 s16 thresh_low[8];
183 struct regulator *vref;
184 u32 vref_uv;
185 int (*send)(const struct i2c_client *client,
186 const char *buf, int count);
187 int (*recv)(const struct i2c_client *client,
188 char *buf, int count);
189 };
190
191 #define MAX1363_MODE_SINGLE(_num, _mask) { \
192 .conf = MAX1363_CHANNEL_SEL(_num) \
193 | MAX1363_CONFIG_SCAN_SINGLE_1 \
194 | MAX1363_CONFIG_SE, \
195 .modemask[0] = _mask, \
196 }
197
198 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
199 .conf = MAX1363_CHANNEL_SEL(_num) \
200 | MAX1363_CONFIG_SCAN_TO_CS \
201 | MAX1363_CONFIG_SE, \
202 .modemask[0] = _mask, \
203 }
204
205 /* note not available for max1363 hence naming */
206 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
207 .conf = MAX1363_CHANNEL_SEL(_num) \
208 | MAX1236_SCAN_MID_TO_CHANNEL \
209 | MAX1363_CONFIG_SE, \
210 .modemask[0] = _mask \
211 }
212
213 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
214 .conf = MAX1363_CHANNEL_SEL(_nump) \
215 | MAX1363_CONFIG_SCAN_SINGLE_1 \
216 | MAX1363_CONFIG_DE, \
217 .modemask[0] = _mask \
218 }
219
220 /* Can't think how to automate naming so specify for now */
221 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
222 .conf = MAX1363_CHANNEL_SEL(_num) \
223 | MAX1363_CONFIG_SCAN_TO_CS \
224 | MAX1363_CONFIG_DE, \
225 .modemask[0] = _mask \
226 }
227
228 /* note only available for max1363 hence naming */
229 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
230 .conf = MAX1363_CHANNEL_SEL(_num) \
231 | MAX1236_SCAN_MID_TO_CHANNEL \
232 | MAX1363_CONFIG_SE, \
233 .modemask[0] = _mask \
234 }
235
236 static const struct max1363_mode max1363_mode_table[] = {
237 /* All of the single channel options first */
238 MAX1363_MODE_SINGLE(0, 1 << 0),
239 MAX1363_MODE_SINGLE(1, 1 << 1),
240 MAX1363_MODE_SINGLE(2, 1 << 2),
241 MAX1363_MODE_SINGLE(3, 1 << 3),
242 MAX1363_MODE_SINGLE(4, 1 << 4),
243 MAX1363_MODE_SINGLE(5, 1 << 5),
244 MAX1363_MODE_SINGLE(6, 1 << 6),
245 MAX1363_MODE_SINGLE(7, 1 << 7),
246 MAX1363_MODE_SINGLE(8, 1 << 8),
247 MAX1363_MODE_SINGLE(9, 1 << 9),
248 MAX1363_MODE_SINGLE(10, 1 << 10),
249 MAX1363_MODE_SINGLE(11, 1 << 11),
250
251 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
252 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
253 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
254 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
255 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
256 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
257 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
258 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
259 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
260 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
261 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
262 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
263
264 /* The multichannel scans next */
265 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
266 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
268 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
282
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
297 };
298
299 static const struct max1363_mode
300 *max1363_match_mode(const unsigned long *mask,
301 const struct max1363_chip_info *ci)
302 {
303 int i;
304 if (mask)
305 for (i = 0; i < ci->num_modes; i++)
306 if (bitmap_subset(mask,
307 max1363_mode_table[ci->mode_list[i]].
308 modemask,
309 MAX1363_MAX_CHANNELS))
310 return &max1363_mode_table[ci->mode_list[i]];
311 return NULL;
312 }
313
314 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
315 int count)
316 {
317 int i, err;
318
319 for (i = err = 0; err == 0 && i < count; ++i)
320 err = i2c_smbus_write_byte(client, buf[i]);
321
322 return err ? err : count;
323 }
324
325 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
326 int count)
327 {
328 int i, ret;
329
330 for (i = 0; i < count; ++i) {
331 ret = i2c_smbus_read_byte(client);
332 if (ret < 0)
333 return ret;
334 buf[i] = ret;
335 }
336
337 return count;
338 }
339
340 static int max1363_write_basic_config(struct max1363_state *st)
341 {
342 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
343
344 return st->send(st->client, tx_buf, 2);
345 }
346
347 static int max1363_set_scan_mode(struct max1363_state *st)
348 {
349 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
350 | MAX1363_SCAN_MASK
351 | MAX1363_SE_DE_MASK);
352 st->configbyte |= st->current_mode->conf;
353
354 return max1363_write_basic_config(st);
355 }
356
357 static int max1363_read_single_chan(struct iio_dev *indio_dev,
358 struct iio_chan_spec const *chan,
359 int *val,
360 long m)
361 {
362 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
363 s32 data;
364 u8 rxbuf[2];
365 struct max1363_state *st = iio_priv(indio_dev);
366 struct i2c_client *client = st->client;
367
368 guard(mutex)(&st->lock);
369
370 /*
371 * If monitor mode is enabled, the method for reading a single
372 * channel will have to be rather different and has not yet
373 * been implemented.
374 *
375 * Also, cannot read directly if buffered capture enabled.
376 */
377 if (st->monitor_on)
378 return -EBUSY;
379
380 /* Check to see if current scan mode is correct */
381 if (st->current_mode != &max1363_mode_table[chan->address]) {
382 int ret;
383
384 /* Update scan mode if needed */
385 st->current_mode = &max1363_mode_table[chan->address];
386 ret = max1363_set_scan_mode(st);
387 if (ret < 0)
388 return ret;
389 }
390 if (st->chip_info->bits != 8) {
391 /* Get reading */
392 data = st->recv(client, rxbuf, 2);
393 if (data < 0)
394 return data;
395
396 data = get_unaligned_be16(rxbuf) &
397 ((1 << st->chip_info->bits) - 1);
398 } else {
399 /* Get reading */
400 data = st->recv(client, rxbuf, 1);
401 if (data < 0)
402 return data;
403
404 data = rxbuf[0];
405 }
406 *val = data;
407
408 return 0;
409 }
410 unreachable();
411 }
412
413 static int max1363_read_raw(struct iio_dev *indio_dev,
414 struct iio_chan_spec const *chan,
415 int *val,
416 int *val2,
417 long m)
418 {
419 struct max1363_state *st = iio_priv(indio_dev);
420 int ret;
421
422 switch (m) {
423 case IIO_CHAN_INFO_RAW:
424 ret = max1363_read_single_chan(indio_dev, chan, val, m);
425 if (ret < 0)
426 return ret;
427 return IIO_VAL_INT;
428 case IIO_CHAN_INFO_SCALE:
429 *val = st->vref_uv / 1000;
430 *val2 = st->chip_info->bits;
431 return IIO_VAL_FRACTIONAL_LOG2;
432 default:
433 return -EINVAL;
434 }
435 return 0;
436 }
437
438 /* Applies to max1363 */
439 static const enum max1363_modes max1363_mode_list[] = {
440 _s0, _s1, _s2, _s3,
441 s0to1, s0to2, s0to3,
442 d0m1, d2m3, d1m0, d3m2,
443 d0m1to2m3, d1m0to3m2,
444 };
445
446 static const struct iio_event_spec max1363_events[] = {
447 {
448 .type = IIO_EV_TYPE_THRESH,
449 .dir = IIO_EV_DIR_RISING,
450 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
451 BIT(IIO_EV_INFO_ENABLE),
452 }, {
453 .type = IIO_EV_TYPE_THRESH,
454 .dir = IIO_EV_DIR_FALLING,
455 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
456 BIT(IIO_EV_INFO_ENABLE),
457 },
458 };
459
460 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
461 { \
462 .type = IIO_VOLTAGE, \
463 .indexed = 1, \
464 .channel = num, \
465 .address = addr, \
466 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
467 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
468 .datasheet_name = "AIN"#num, \
469 .scan_type = { \
470 .sign = 'u', \
471 .realbits = bits, \
472 .storagebits = (bits > 8) ? 16 : 8, \
473 .endianness = IIO_BE, \
474 }, \
475 .scan_index = si, \
476 .event_spec = ev_spec, \
477 .num_event_specs = num_ev_spec, \
478 }
479
480 /* bipolar channel */
481 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
482 { \
483 .type = IIO_VOLTAGE, \
484 .differential = 1, \
485 .indexed = 1, \
486 .channel = num, \
487 .channel2 = num2, \
488 .address = addr, \
489 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
490 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
491 .datasheet_name = "AIN"#num"-AIN"#num2, \
492 .scan_type = { \
493 .sign = 's', \
494 .realbits = bits, \
495 .storagebits = (bits > 8) ? 16 : 8, \
496 .endianness = IIO_BE, \
497 }, \
498 .scan_index = si, \
499 .event_spec = ev_spec, \
500 .num_event_specs = num_ev_spec, \
501 }
502
503 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
504 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
505 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
512 IIO_CHAN_SOFT_TIMESTAMP(8) \
513 }
514
515 static const struct iio_chan_spec max1036_channels[] =
516 MAX1363_4X_CHANS(8, NULL, 0);
517 static const struct iio_chan_spec max1136_channels[] =
518 MAX1363_4X_CHANS(10, NULL, 0);
519 static const struct iio_chan_spec max1236_channels[] =
520 MAX1363_4X_CHANS(12, NULL, 0);
521 static const struct iio_chan_spec max1361_channels[] =
522 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
523 static const struct iio_chan_spec max1363_channels[] =
524 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
525
526 /* Applies to max1236, max1237 */
527 static const enum max1363_modes max1236_mode_list[] = {
528 _s0, _s1, _s2, _s3,
529 s0to1, s0to2, s0to3,
530 d0m1, d2m3, d1m0, d3m2,
531 d0m1to2m3, d1m0to3m2,
532 s2to3,
533 };
534
535 /* Applies to max1238, max1239 */
536 static const enum max1363_modes max1238_mode_list[] = {
537 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
538 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
539 s0to7, s0to8, s0to9, s0to10, s0to11,
540 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
541 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
542 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
543 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
544 s6to7, s6to8, s6to9, s6to10, s6to11,
545 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
546 };
547
548 #define MAX1363_12X_CHANS(bits) { \
549 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
550 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
551 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
552 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
553 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
554 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
555 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
556 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
557 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
558 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
559 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
560 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
561 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
562 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
563 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
564 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
565 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
566 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
567 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
568 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
569 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
570 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
571 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
572 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
573 IIO_CHAN_SOFT_TIMESTAMP(24) \
574 }
575 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
576 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
577 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
578
579 static const enum max1363_modes max11607_mode_list[] = {
580 _s0, _s1, _s2, _s3,
581 s0to1, s0to2, s0to3,
582 s2to3,
583 d0m1, d2m3, d1m0, d3m2,
584 d0m1to2m3, d1m0to3m2,
585 };
586
587 static const enum max1363_modes max11608_mode_list[] = {
588 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
589 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
590 s6to7,
591 d0m1, d2m3, d4m5, d6m7,
592 d1m0, d3m2, d5m4, d7m6,
593 d0m1to2m3, d0m1to4m5, d0m1to6m7,
594 d1m0to3m2, d1m0to5m4, d1m0to7m6,
595 };
596
597 #define MAX1363_8X_CHANS(bits) { \
598 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
599 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
600 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
601 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
602 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
603 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
604 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
605 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
606 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
607 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
608 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
609 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
610 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
611 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
612 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
613 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
614 IIO_CHAN_SOFT_TIMESTAMP(16) \
615 }
616 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
617 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
618 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
619
620 static const enum max1363_modes max11644_mode_list[] = {
621 _s0, _s1, s0to1, d0m1, d1m0,
622 };
623
624 #define MAX1363_2X_CHANS(bits) { \
625 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
626 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
627 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
628 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
629 IIO_CHAN_SOFT_TIMESTAMP(4) \
630 }
631
632 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
633 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
634
635 enum { max1361,
636 max1362,
637 max1363,
638 max1364,
639 max1036,
640 max1037,
641 max1038,
642 max1039,
643 max1136,
644 max1137,
645 max1138,
646 max1139,
647 max1236,
648 max1237,
649 max1238,
650 max1239,
651 max11600,
652 max11601,
653 max11602,
654 max11603,
655 max11604,
656 max11605,
657 max11606,
658 max11607,
659 max11608,
660 max11609,
661 max11610,
662 max11611,
663 max11612,
664 max11613,
665 max11614,
666 max11615,
667 max11616,
668 max11617,
669 max11644,
670 max11645,
671 max11646,
672 max11647
673 };
674
675 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
676 8300, 4200, 2000, 1000 };
677
678 static ssize_t max1363_monitor_show_freq(struct device *dev,
679 struct device_attribute *attr,
680 char *buf)
681 {
682 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
683 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
684 }
685
686 static ssize_t max1363_monitor_store_freq(struct device *dev,
687 struct device_attribute *attr,
688 const char *buf,
689 size_t len)
690 {
691 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
692 struct max1363_state *st = iio_priv(indio_dev);
693 int i, ret;
694 unsigned long val;
695 bool found = false;
696
697 ret = kstrtoul(buf, 10, &val);
698 if (ret)
699 return -EINVAL;
700 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
701 if (val == max1363_monitor_speeds[i]) {
702 found = true;
703 break;
704 }
705 if (!found)
706 return -EINVAL;
707
708 scoped_guard(mutex, &st->lock)
709 st->monitor_speed = i;
710
711 return 0;
712 }
713
714 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
715 max1363_monitor_show_freq,
716 max1363_monitor_store_freq);
717
718 static IIO_CONST_ATTR(sampling_frequency_available,
719 "133000 665000 33300 16600 8300 4200 2000 1000");
720
721 static int max1363_read_thresh(struct iio_dev *indio_dev,
722 const struct iio_chan_spec *chan, enum iio_event_type type,
723 enum iio_event_direction dir, enum iio_event_info info, int *val,
724 int *val2)
725 {
726 struct max1363_state *st = iio_priv(indio_dev);
727 if (dir == IIO_EV_DIR_FALLING)
728 *val = st->thresh_low[chan->channel];
729 else
730 *val = st->thresh_high[chan->channel];
731 return IIO_VAL_INT;
732 }
733
734 static int max1363_write_thresh(struct iio_dev *indio_dev,
735 const struct iio_chan_spec *chan, enum iio_event_type type,
736 enum iio_event_direction dir, enum iio_event_info info, int val,
737 int val2)
738 {
739 struct max1363_state *st = iio_priv(indio_dev);
740 /* make it handle signed correctly as well */
741 switch (st->chip_info->bits) {
742 case 10:
743 if (val > 0x3FF)
744 return -EINVAL;
745 break;
746 case 12:
747 if (val > 0xFFF)
748 return -EINVAL;
749 break;
750 }
751
752 switch (dir) {
753 case IIO_EV_DIR_FALLING:
754 st->thresh_low[chan->channel] = val;
755 break;
756 case IIO_EV_DIR_RISING:
757 st->thresh_high[chan->channel] = val;
758 break;
759 default:
760 return -EINVAL;
761 }
762
763 return 0;
764 }
765
766 static const u64 max1363_event_codes[] = {
767 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
768 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
769 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
770 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
771 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
772 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
783 };
784
785 static irqreturn_t max1363_event_handler(int irq, void *private)
786 {
787 struct iio_dev *indio_dev = private;
788 struct max1363_state *st = iio_priv(indio_dev);
789 s64 timestamp = iio_get_time_ns(indio_dev);
790 unsigned long mask, loc;
791 u8 rx;
792 u8 tx[2] = { st->setupbyte,
793 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
794
795 st->recv(st->client, &rx, 1);
796 mask = rx;
797 for_each_set_bit(loc, &mask, 8)
798 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
799 st->send(st->client, tx, 2);
800
801 return IRQ_HANDLED;
802 }
803
804 static int max1363_read_event_config(struct iio_dev *indio_dev,
805 const struct iio_chan_spec *chan, enum iio_event_type type,
806 enum iio_event_direction dir)
807 {
808 struct max1363_state *st = iio_priv(indio_dev);
809 int val;
810 int number = chan->channel;
811
812 guard(mutex)(&st->lock);
813 if (dir == IIO_EV_DIR_FALLING)
814 val = (1 << number) & st->mask_low;
815 else
816 val = (1 << number) & st->mask_high;
817
818 return val;
819 }
820
821 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
822 {
823 int ret, i = 3, j;
824 unsigned long numelements;
825 int len;
826 const long *modemask;
827
828 if (!enabled) {
829 /* transition to buffered capture is not currently supported */
830 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
831 st->configbyte &= ~MAX1363_SCAN_MASK;
832 st->monitor_on = false;
833 return max1363_write_basic_config(st);
834 }
835
836 /* Ensure we are in the relevant mode */
837 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
838 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
839 | MAX1363_SCAN_MASK
840 | MAX1363_SE_DE_MASK);
841 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
842 if ((st->mask_low | st->mask_high) & 0x0F) {
843 st->configbyte |= max1363_mode_table[s0to3].conf;
844 modemask = max1363_mode_table[s0to3].modemask;
845 } else if ((st->mask_low | st->mask_high) & 0x30) {
846 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
847 modemask = max1363_mode_table[d0m1to2m3].modemask;
848 } else {
849 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
850 modemask = max1363_mode_table[d1m0to3m2].modemask;
851 }
852 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
853 len = 3 * numelements + 3;
854 u8 *tx_buf __free(kfree) = kmalloc(len, GFP_KERNEL);
855 if (!tx_buf)
856 return -ENOMEM;
857
858 tx_buf[0] = st->configbyte;
859 tx_buf[1] = st->setupbyte;
860 tx_buf[2] = (st->monitor_speed << 1);
861
862 /*
863 * So we need to do yet another bit of nefarious scan mode
864 * setup to match what we need.
865 */
866 for (j = 0; j < 8; j++)
867 if (test_bit(j, modemask)) {
868 /* Establish the mode is in the scan */
869 if (st->mask_low & (1 << j)) {
870 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
871 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
872 } else if (j < 4) {
873 tx_buf[i] = 0;
874 tx_buf[i + 1] = 0;
875 } else {
876 tx_buf[i] = 0x80;
877 tx_buf[i + 1] = 0;
878 }
879 if (st->mask_high & (1 << j)) {
880 tx_buf[i + 1] |=
881 (st->thresh_high[j] >> 8) & 0x0F;
882 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
883 } else if (j < 4) {
884 tx_buf[i + 1] |= 0x0F;
885 tx_buf[i + 2] = 0xFF;
886 } else {
887 tx_buf[i + 1] |= 0x07;
888 tx_buf[i + 2] = 0xFF;
889 }
890 i += 3;
891 }
892
893
894 ret = st->send(st->client, tx_buf, len);
895 if (ret < 0)
896 return ret;
897 if (ret != len)
898 return -EIO;
899
900 /*
901 * Now that we hopefully have sensible thresholds in place it is
902 * time to turn the interrupts on.
903 * It is unclear from the data sheet if this should be necessary
904 * (i.e. whether monitor mode setup is atomic) but it appears to
905 * be in practice.
906 */
907 tx_buf[0] = st->setupbyte;
908 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
909 ret = st->send(st->client, tx_buf, 2);
910 if (ret < 0)
911 return ret;
912 if (ret != 2)
913 return -EIO;
914
915 st->monitor_on = true;
916
917 return 0;
918 }
919
920 /*
921 * To keep this manageable we always use one of 3 scan modes.
922 * Scan 0...3, 0-1,2-3 and 1-0,3-2
923 */
924
925 static inline int __max1363_check_event_mask(int thismask, int checkmask)
926 {
927 int ret = 0;
928 /* Is it unipolar */
929 if (thismask < 4) {
930 if (checkmask & ~0x0F) {
931 ret = -EBUSY;
932 goto error_ret;
933 }
934 } else if (thismask < 6) {
935 if (checkmask & ~0x30) {
936 ret = -EBUSY;
937 goto error_ret;
938 }
939 } else if (checkmask & ~0xC0)
940 ret = -EBUSY;
941 error_ret:
942 return ret;
943 }
944
945 static int max1363_write_event_config(struct iio_dev *indio_dev,
946 const struct iio_chan_spec *chan, enum iio_event_type type,
947 enum iio_event_direction dir, bool state)
948 {
949 struct max1363_state *st = iio_priv(indio_dev);
950
951 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
952 int number = chan->channel;
953 u16 unifiedmask;
954 int ret;
955
956 guard(mutex)(&st->lock);
957
958 unifiedmask = st->mask_low | st->mask_high;
959 if (dir == IIO_EV_DIR_FALLING) {
960
961 if (state == 0)
962 st->mask_low &= ~(1 << number);
963 else {
964 ret = __max1363_check_event_mask((1 << number),
965 unifiedmask);
966 if (ret)
967 return ret;
968 st->mask_low |= (1 << number);
969 }
970 } else {
971 if (state == 0)
972 st->mask_high &= ~(1 << number);
973 else {
974 ret = __max1363_check_event_mask((1 << number),
975 unifiedmask);
976 if (ret)
977 return ret;
978 st->mask_high |= (1 << number);
979 }
980 }
981 }
982 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
983
984 return 0;
985 }
986
987 /*
988 * As with scan_elements, only certain sets of these can
989 * be combined.
990 */
991 static struct attribute *max1363_event_attributes[] = {
992 &iio_dev_attr_sampling_frequency.dev_attr.attr,
993 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
994 NULL,
995 };
996
997 static const struct attribute_group max1363_event_attribute_group = {
998 .attrs = max1363_event_attributes,
999 };
1000
1001 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1002 const unsigned long *scan_mask)
1003 {
1004 struct max1363_state *st = iio_priv(indio_dev);
1005
1006 /*
1007 * Need to figure out the current mode based upon the requested
1008 * scan mask in iio_dev
1009 */
1010 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1011 if (!st->current_mode)
1012 return -EINVAL;
1013 max1363_set_scan_mode(st);
1014 return 0;
1015 }
1016
1017 static const struct iio_info max1238_info = {
1018 .read_raw = &max1363_read_raw,
1019 .update_scan_mode = &max1363_update_scan_mode,
1020 };
1021
1022 static const struct iio_info max1363_info = {
1023 .read_event_value = &max1363_read_thresh,
1024 .write_event_value = &max1363_write_thresh,
1025 .read_event_config = &max1363_read_event_config,
1026 .write_event_config = &max1363_write_event_config,
1027 .read_raw = &max1363_read_raw,
1028 .update_scan_mode = &max1363_update_scan_mode,
1029 .event_attrs = &max1363_event_attribute_group,
1030 };
1031
1032 /* max1363 and max1368 tested - rest from data sheet */
1033 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1034 [max1361] = {
1035 .bits = 10,
1036 .int_vref_mv = 2048,
1037 .mode_list = max1363_mode_list,
1038 .num_modes = ARRAY_SIZE(max1363_mode_list),
1039 .default_mode = s0to3,
1040 .channels = max1361_channels,
1041 .num_channels = ARRAY_SIZE(max1361_channels),
1042 .info = &max1363_info,
1043 },
1044 [max1362] = {
1045 .bits = 10,
1046 .int_vref_mv = 4096,
1047 .mode_list = max1363_mode_list,
1048 .num_modes = ARRAY_SIZE(max1363_mode_list),
1049 .default_mode = s0to3,
1050 .channels = max1361_channels,
1051 .num_channels = ARRAY_SIZE(max1361_channels),
1052 .info = &max1363_info,
1053 },
1054 [max1363] = {
1055 .bits = 12,
1056 .int_vref_mv = 2048,
1057 .mode_list = max1363_mode_list,
1058 .num_modes = ARRAY_SIZE(max1363_mode_list),
1059 .default_mode = s0to3,
1060 .channels = max1363_channels,
1061 .num_channels = ARRAY_SIZE(max1363_channels),
1062 .info = &max1363_info,
1063 },
1064 [max1364] = {
1065 .bits = 12,
1066 .int_vref_mv = 4096,
1067 .mode_list = max1363_mode_list,
1068 .num_modes = ARRAY_SIZE(max1363_mode_list),
1069 .default_mode = s0to3,
1070 .channels = max1363_channels,
1071 .num_channels = ARRAY_SIZE(max1363_channels),
1072 .info = &max1363_info,
1073 },
1074 [max1036] = {
1075 .bits = 8,
1076 .int_vref_mv = 4096,
1077 .mode_list = max1236_mode_list,
1078 .num_modes = ARRAY_SIZE(max1236_mode_list),
1079 .default_mode = s0to3,
1080 .info = &max1238_info,
1081 .channels = max1036_channels,
1082 .num_channels = ARRAY_SIZE(max1036_channels),
1083 },
1084 [max1037] = {
1085 .bits = 8,
1086 .int_vref_mv = 2048,
1087 .mode_list = max1236_mode_list,
1088 .num_modes = ARRAY_SIZE(max1236_mode_list),
1089 .default_mode = s0to3,
1090 .info = &max1238_info,
1091 .channels = max1036_channels,
1092 .num_channels = ARRAY_SIZE(max1036_channels),
1093 },
1094 [max1038] = {
1095 .bits = 8,
1096 .int_vref_mv = 4096,
1097 .mode_list = max1238_mode_list,
1098 .num_modes = ARRAY_SIZE(max1238_mode_list),
1099 .default_mode = s0to11,
1100 .info = &max1238_info,
1101 .channels = max1038_channels,
1102 .num_channels = ARRAY_SIZE(max1038_channels),
1103 },
1104 [max1039] = {
1105 .bits = 8,
1106 .int_vref_mv = 2048,
1107 .mode_list = max1238_mode_list,
1108 .num_modes = ARRAY_SIZE(max1238_mode_list),
1109 .default_mode = s0to11,
1110 .info = &max1238_info,
1111 .channels = max1038_channels,
1112 .num_channels = ARRAY_SIZE(max1038_channels),
1113 },
1114 [max1136] = {
1115 .bits = 10,
1116 .int_vref_mv = 4096,
1117 .mode_list = max1236_mode_list,
1118 .num_modes = ARRAY_SIZE(max1236_mode_list),
1119 .default_mode = s0to3,
1120 .info = &max1238_info,
1121 .channels = max1136_channels,
1122 .num_channels = ARRAY_SIZE(max1136_channels),
1123 },
1124 [max1137] = {
1125 .bits = 10,
1126 .int_vref_mv = 2048,
1127 .mode_list = max1236_mode_list,
1128 .num_modes = ARRAY_SIZE(max1236_mode_list),
1129 .default_mode = s0to3,
1130 .info = &max1238_info,
1131 .channels = max1136_channels,
1132 .num_channels = ARRAY_SIZE(max1136_channels),
1133 },
1134 [max1138] = {
1135 .bits = 10,
1136 .int_vref_mv = 4096,
1137 .mode_list = max1238_mode_list,
1138 .num_modes = ARRAY_SIZE(max1238_mode_list),
1139 .default_mode = s0to11,
1140 .info = &max1238_info,
1141 .channels = max1138_channels,
1142 .num_channels = ARRAY_SIZE(max1138_channels),
1143 },
1144 [max1139] = {
1145 .bits = 10,
1146 .int_vref_mv = 2048,
1147 .mode_list = max1238_mode_list,
1148 .num_modes = ARRAY_SIZE(max1238_mode_list),
1149 .default_mode = s0to11,
1150 .info = &max1238_info,
1151 .channels = max1138_channels,
1152 .num_channels = ARRAY_SIZE(max1138_channels),
1153 },
1154 [max1236] = {
1155 .bits = 12,
1156 .int_vref_mv = 4096,
1157 .mode_list = max1236_mode_list,
1158 .num_modes = ARRAY_SIZE(max1236_mode_list),
1159 .default_mode = s0to3,
1160 .info = &max1238_info,
1161 .channels = max1236_channels,
1162 .num_channels = ARRAY_SIZE(max1236_channels),
1163 },
1164 [max1237] = {
1165 .bits = 12,
1166 .int_vref_mv = 2048,
1167 .mode_list = max1236_mode_list,
1168 .num_modes = ARRAY_SIZE(max1236_mode_list),
1169 .default_mode = s0to3,
1170 .info = &max1238_info,
1171 .channels = max1236_channels,
1172 .num_channels = ARRAY_SIZE(max1236_channels),
1173 },
1174 [max1238] = {
1175 .bits = 12,
1176 .int_vref_mv = 4096,
1177 .mode_list = max1238_mode_list,
1178 .num_modes = ARRAY_SIZE(max1238_mode_list),
1179 .default_mode = s0to11,
1180 .info = &max1238_info,
1181 .channels = max1238_channels,
1182 .num_channels = ARRAY_SIZE(max1238_channels),
1183 },
1184 [max1239] = {
1185 .bits = 12,
1186 .int_vref_mv = 2048,
1187 .mode_list = max1238_mode_list,
1188 .num_modes = ARRAY_SIZE(max1238_mode_list),
1189 .default_mode = s0to11,
1190 .info = &max1238_info,
1191 .channels = max1238_channels,
1192 .num_channels = ARRAY_SIZE(max1238_channels),
1193 },
1194 [max11600] = {
1195 .bits = 8,
1196 .int_vref_mv = 4096,
1197 .mode_list = max11607_mode_list,
1198 .num_modes = ARRAY_SIZE(max11607_mode_list),
1199 .default_mode = s0to3,
1200 .info = &max1238_info,
1201 .channels = max1036_channels,
1202 .num_channels = ARRAY_SIZE(max1036_channels),
1203 },
1204 [max11601] = {
1205 .bits = 8,
1206 .int_vref_mv = 2048,
1207 .mode_list = max11607_mode_list,
1208 .num_modes = ARRAY_SIZE(max11607_mode_list),
1209 .default_mode = s0to3,
1210 .info = &max1238_info,
1211 .channels = max1036_channels,
1212 .num_channels = ARRAY_SIZE(max1036_channels),
1213 },
1214 [max11602] = {
1215 .bits = 8,
1216 .int_vref_mv = 4096,
1217 .mode_list = max11608_mode_list,
1218 .num_modes = ARRAY_SIZE(max11608_mode_list),
1219 .default_mode = s0to7,
1220 .info = &max1238_info,
1221 .channels = max11602_channels,
1222 .num_channels = ARRAY_SIZE(max11602_channels),
1223 },
1224 [max11603] = {
1225 .bits = 8,
1226 .int_vref_mv = 2048,
1227 .mode_list = max11608_mode_list,
1228 .num_modes = ARRAY_SIZE(max11608_mode_list),
1229 .default_mode = s0to7,
1230 .info = &max1238_info,
1231 .channels = max11602_channels,
1232 .num_channels = ARRAY_SIZE(max11602_channels),
1233 },
1234 [max11604] = {
1235 .bits = 8,
1236 .int_vref_mv = 4096,
1237 .mode_list = max1238_mode_list,
1238 .num_modes = ARRAY_SIZE(max1238_mode_list),
1239 .default_mode = s0to11,
1240 .info = &max1238_info,
1241 .channels = max1038_channels,
1242 .num_channels = ARRAY_SIZE(max1038_channels),
1243 },
1244 [max11605] = {
1245 .bits = 8,
1246 .int_vref_mv = 2048,
1247 .mode_list = max1238_mode_list,
1248 .num_modes = ARRAY_SIZE(max1238_mode_list),
1249 .default_mode = s0to11,
1250 .info = &max1238_info,
1251 .channels = max1038_channels,
1252 .num_channels = ARRAY_SIZE(max1038_channels),
1253 },
1254 [max11606] = {
1255 .bits = 10,
1256 .int_vref_mv = 4096,
1257 .mode_list = max11607_mode_list,
1258 .num_modes = ARRAY_SIZE(max11607_mode_list),
1259 .default_mode = s0to3,
1260 .info = &max1238_info,
1261 .channels = max1136_channels,
1262 .num_channels = ARRAY_SIZE(max1136_channels),
1263 },
1264 [max11607] = {
1265 .bits = 10,
1266 .int_vref_mv = 2048,
1267 .mode_list = max11607_mode_list,
1268 .num_modes = ARRAY_SIZE(max11607_mode_list),
1269 .default_mode = s0to3,
1270 .info = &max1238_info,
1271 .channels = max1136_channels,
1272 .num_channels = ARRAY_SIZE(max1136_channels),
1273 },
1274 [max11608] = {
1275 .bits = 10,
1276 .int_vref_mv = 4096,
1277 .mode_list = max11608_mode_list,
1278 .num_modes = ARRAY_SIZE(max11608_mode_list),
1279 .default_mode = s0to7,
1280 .info = &max1238_info,
1281 .channels = max11608_channels,
1282 .num_channels = ARRAY_SIZE(max11608_channels),
1283 },
1284 [max11609] = {
1285 .bits = 10,
1286 .int_vref_mv = 2048,
1287 .mode_list = max11608_mode_list,
1288 .num_modes = ARRAY_SIZE(max11608_mode_list),
1289 .default_mode = s0to7,
1290 .info = &max1238_info,
1291 .channels = max11608_channels,
1292 .num_channels = ARRAY_SIZE(max11608_channels),
1293 },
1294 [max11610] = {
1295 .bits = 10,
1296 .int_vref_mv = 4096,
1297 .mode_list = max1238_mode_list,
1298 .num_modes = ARRAY_SIZE(max1238_mode_list),
1299 .default_mode = s0to11,
1300 .info = &max1238_info,
1301 .channels = max1138_channels,
1302 .num_channels = ARRAY_SIZE(max1138_channels),
1303 },
1304 [max11611] = {
1305 .bits = 10,
1306 .int_vref_mv = 2048,
1307 .mode_list = max1238_mode_list,
1308 .num_modes = ARRAY_SIZE(max1238_mode_list),
1309 .default_mode = s0to11,
1310 .info = &max1238_info,
1311 .channels = max1138_channels,
1312 .num_channels = ARRAY_SIZE(max1138_channels),
1313 },
1314 [max11612] = {
1315 .bits = 12,
1316 .int_vref_mv = 4096,
1317 .mode_list = max11607_mode_list,
1318 .num_modes = ARRAY_SIZE(max11607_mode_list),
1319 .default_mode = s0to3,
1320 .info = &max1238_info,
1321 .channels = max1363_channels,
1322 .num_channels = ARRAY_SIZE(max1363_channels),
1323 },
1324 [max11613] = {
1325 .bits = 12,
1326 .int_vref_mv = 2048,
1327 .mode_list = max11607_mode_list,
1328 .num_modes = ARRAY_SIZE(max11607_mode_list),
1329 .default_mode = s0to3,
1330 .info = &max1238_info,
1331 .channels = max1363_channels,
1332 .num_channels = ARRAY_SIZE(max1363_channels),
1333 },
1334 [max11614] = {
1335 .bits = 12,
1336 .int_vref_mv = 4096,
1337 .mode_list = max11608_mode_list,
1338 .num_modes = ARRAY_SIZE(max11608_mode_list),
1339 .default_mode = s0to7,
1340 .info = &max1238_info,
1341 .channels = max11614_channels,
1342 .num_channels = ARRAY_SIZE(max11614_channels),
1343 },
1344 [max11615] = {
1345 .bits = 12,
1346 .int_vref_mv = 2048,
1347 .mode_list = max11608_mode_list,
1348 .num_modes = ARRAY_SIZE(max11608_mode_list),
1349 .default_mode = s0to7,
1350 .info = &max1238_info,
1351 .channels = max11614_channels,
1352 .num_channels = ARRAY_SIZE(max11614_channels),
1353 },
1354 [max11616] = {
1355 .bits = 12,
1356 .int_vref_mv = 4096,
1357 .mode_list = max1238_mode_list,
1358 .num_modes = ARRAY_SIZE(max1238_mode_list),
1359 .default_mode = s0to11,
1360 .info = &max1238_info,
1361 .channels = max1238_channels,
1362 .num_channels = ARRAY_SIZE(max1238_channels),
1363 },
1364 [max11617] = {
1365 .bits = 12,
1366 .int_vref_mv = 2048,
1367 .mode_list = max1238_mode_list,
1368 .num_modes = ARRAY_SIZE(max1238_mode_list),
1369 .default_mode = s0to11,
1370 .info = &max1238_info,
1371 .channels = max1238_channels,
1372 .num_channels = ARRAY_SIZE(max1238_channels),
1373 },
1374 [max11644] = {
1375 .bits = 12,
1376 .int_vref_mv = 4096,
1377 .mode_list = max11644_mode_list,
1378 .num_modes = ARRAY_SIZE(max11644_mode_list),
1379 .default_mode = s0to1,
1380 .info = &max1238_info,
1381 .channels = max11644_channels,
1382 .num_channels = ARRAY_SIZE(max11644_channels),
1383 },
1384 [max11645] = {
1385 .bits = 12,
1386 .int_vref_mv = 2048,
1387 .mode_list = max11644_mode_list,
1388 .num_modes = ARRAY_SIZE(max11644_mode_list),
1389 .default_mode = s0to1,
1390 .info = &max1238_info,
1391 .channels = max11644_channels,
1392 .num_channels = ARRAY_SIZE(max11644_channels),
1393 },
1394 [max11646] = {
1395 .bits = 10,
1396 .int_vref_mv = 4096,
1397 .mode_list = max11644_mode_list,
1398 .num_modes = ARRAY_SIZE(max11644_mode_list),
1399 .default_mode = s0to1,
1400 .info = &max1238_info,
1401 .channels = max11646_channels,
1402 .num_channels = ARRAY_SIZE(max11646_channels),
1403 },
1404 [max11647] = {
1405 .bits = 10,
1406 .int_vref_mv = 2048,
1407 .mode_list = max11644_mode_list,
1408 .num_modes = ARRAY_SIZE(max11644_mode_list),
1409 .default_mode = s0to1,
1410 .info = &max1238_info,
1411 .channels = max11646_channels,
1412 .num_channels = ARRAY_SIZE(max11646_channels),
1413 },
1414 };
1415
1416 static int max1363_initial_setup(struct max1363_state *st)
1417 {
1418 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1419 | MAX1363_SETUP_UNIPOLAR
1420 | MAX1363_SETUP_NORESET;
1421
1422 if (st->vref)
1423 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1424 else
1425 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1426 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1427
1428 /* Set scan mode writes the config anyway so wait until then */
1429 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1430 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1431 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1432
1433 return max1363_set_scan_mode(st);
1434 }
1435
1436 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1437 {
1438 struct max1363_state *st = iio_priv(indio_dev);
1439 unsigned long *masks;
1440 int i;
1441
1442 masks = devm_kzalloc(&indio_dev->dev,
1443 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1444 sizeof(long),
1445 st->chip_info->num_modes + 1),
1446 GFP_KERNEL);
1447 if (!masks)
1448 return -ENOMEM;
1449
1450 for (i = 0; i < st->chip_info->num_modes; i++)
1451 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1452 max1363_mode_table[st->chip_info->mode_list[i]]
1453 .modemask, MAX1363_MAX_CHANNELS);
1454
1455 indio_dev->available_scan_masks = masks;
1456
1457 return 0;
1458 }
1459
1460 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1461 {
1462 struct iio_poll_func *pf = p;
1463 struct iio_dev *indio_dev = pf->indio_dev;
1464 struct max1363_state *st = iio_priv(indio_dev);
1465 __u8 *rxbuf;
1466 int b_sent;
1467 size_t d_size;
1468 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1469 MAX1363_MAX_CHANNELS);
1470
1471 /* Ensure the timestamp is 8 byte aligned */
1472 if (st->chip_info->bits != 8)
1473 d_size = numvals*2;
1474 else
1475 d_size = numvals;
1476 if (indio_dev->scan_timestamp) {
1477 d_size += sizeof(s64);
1478 if (d_size % sizeof(s64))
1479 d_size += sizeof(s64) - (d_size % sizeof(s64));
1480 }
1481 /* Monitor mode prevents reading. Whilst not currently implemented
1482 * might as well have this test in here in the meantime as it does
1483 * no harm.
1484 */
1485 if (numvals == 0)
1486 goto done;
1487
1488 rxbuf = kmalloc(d_size, GFP_KERNEL);
1489 if (rxbuf == NULL)
1490 goto done;
1491 if (st->chip_info->bits != 8)
1492 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1493 else
1494 b_sent = st->recv(st->client, rxbuf, numvals);
1495 if (b_sent < 0)
1496 goto done_free;
1497
1498 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1499 iio_get_time_ns(indio_dev));
1500
1501 done_free:
1502 kfree(rxbuf);
1503 done:
1504 iio_trigger_notify_done(indio_dev->trig);
1505
1506 return IRQ_HANDLED;
1507 }
1508
1509 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1510 .compatible = of_compatible, \
1511 .data = &max1363_chip_info_tbl[cfg], \
1512 }
1513
1514 static const struct of_device_id max1363_of_match[] = {
1515 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1516 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1517 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1518 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1519 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1520 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1521 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1522 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1523 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1524 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1525 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1526 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1527 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1528 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1529 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1530 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1531 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1532 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1533 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1534 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1535 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1536 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1537 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1538 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1539 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1540 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1541 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1542 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1543 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1544 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1545 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1546 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1547 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1548 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1549 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1550 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1551 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1552 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1553 { /* sentinel */ }
1554 };
1555 MODULE_DEVICE_TABLE(of, max1363_of_match);
1556
1557 static int max1363_probe(struct i2c_client *client)
1558 {
1559 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1560 int ret;
1561 struct max1363_state *st;
1562 struct iio_dev *indio_dev;
1563
1564 indio_dev = devm_iio_device_alloc(&client->dev,
1565 sizeof(struct max1363_state));
1566 if (!indio_dev)
1567 return -ENOMEM;
1568
1569 st = iio_priv(indio_dev);
1570
1571 mutex_init(&st->lock);
1572 ret = devm_regulator_get_enable(&client->dev, "vcc");
1573 if (ret)
1574 return ret;
1575
1576 st->chip_info = i2c_get_match_data(client);
1577 st->client = client;
1578
1579 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref");
1580 if (ret < 0 && ret != -ENODEV)
1581 return ret;
1582
1583
1584 st->vref_uv = ret == -ENODEV ? st->chip_info->int_vref_mv * 1000 : ret;
1585
1586 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1587 st->send = i2c_master_send;
1588 st->recv = i2c_master_recv;
1589 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1590 && st->chip_info->bits == 8) {
1591 st->send = max1363_smbus_send;
1592 st->recv = max1363_smbus_recv;
1593 } else {
1594 return -EOPNOTSUPP;
1595 }
1596
1597 ret = max1363_alloc_scan_masks(indio_dev);
1598 if (ret)
1599 return ret;
1600
1601 indio_dev->name = id->name;
1602 indio_dev->channels = st->chip_info->channels;
1603 indio_dev->num_channels = st->chip_info->num_channels;
1604 indio_dev->info = st->chip_info->info;
1605 indio_dev->modes = INDIO_DIRECT_MODE;
1606 ret = max1363_initial_setup(st);
1607 if (ret < 0)
1608 return ret;
1609
1610 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1611 &max1363_trigger_handler, NULL);
1612 if (ret)
1613 return ret;
1614
1615 if (client->irq) {
1616 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1617 NULL,
1618 &max1363_event_handler,
1619 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1620 "max1363_event",
1621 indio_dev);
1622
1623 if (ret)
1624 return ret;
1625 }
1626
1627 return devm_iio_device_register(&client->dev, indio_dev);
1628 }
1629
1630 #define MAX1363_ID_TABLE(_name, cfg) { \
1631 .name = _name, \
1632 .driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \
1633 }
1634
1635 static const struct i2c_device_id max1363_id[] = {
1636 MAX1363_ID_TABLE("max1361", max1361),
1637 MAX1363_ID_TABLE("max1362", max1362),
1638 MAX1363_ID_TABLE("max1363", max1363),
1639 MAX1363_ID_TABLE("max1364", max1364),
1640 MAX1363_ID_TABLE("max1036", max1036),
1641 MAX1363_ID_TABLE("max1037", max1037),
1642 MAX1363_ID_TABLE("max1038", max1038),
1643 MAX1363_ID_TABLE("max1039", max1039),
1644 MAX1363_ID_TABLE("max1136", max1136),
1645 MAX1363_ID_TABLE("max1137", max1137),
1646 MAX1363_ID_TABLE("max1138", max1138),
1647 MAX1363_ID_TABLE("max1139", max1139),
1648 MAX1363_ID_TABLE("max1236", max1236),
1649 MAX1363_ID_TABLE("max1237", max1237),
1650 MAX1363_ID_TABLE("max1238", max1238),
1651 MAX1363_ID_TABLE("max1239", max1239),
1652 MAX1363_ID_TABLE("max11600", max11600),
1653 MAX1363_ID_TABLE("max11601", max11601),
1654 MAX1363_ID_TABLE("max11602", max11602),
1655 MAX1363_ID_TABLE("max11603", max11603),
1656 MAX1363_ID_TABLE("max11604", max11604),
1657 MAX1363_ID_TABLE("max11605", max11605),
1658 MAX1363_ID_TABLE("max11606", max11606),
1659 MAX1363_ID_TABLE("max11607", max11607),
1660 MAX1363_ID_TABLE("max11608", max11608),
1661 MAX1363_ID_TABLE("max11609", max11609),
1662 MAX1363_ID_TABLE("max11610", max11610),
1663 MAX1363_ID_TABLE("max11611", max11611),
1664 MAX1363_ID_TABLE("max11612", max11612),
1665 MAX1363_ID_TABLE("max11613", max11613),
1666 MAX1363_ID_TABLE("max11614", max11614),
1667 MAX1363_ID_TABLE("max11615", max11615),
1668 MAX1363_ID_TABLE("max11616", max11616),
1669 MAX1363_ID_TABLE("max11617", max11617),
1670 MAX1363_ID_TABLE("max11644", max11644),
1671 MAX1363_ID_TABLE("max11645", max11645),
1672 MAX1363_ID_TABLE("max11646", max11646),
1673 MAX1363_ID_TABLE("max11647", max11647),
1674 { /* sentinel */ }
1675 };
1676
1677 MODULE_DEVICE_TABLE(i2c, max1363_id);
1678
1679 static struct i2c_driver max1363_driver = {
1680 .driver = {
1681 .name = "max1363",
1682 .of_match_table = max1363_of_match,
1683 },
1684 .probe = max1363_probe,
1685 .id_table = max1363_id,
1686 };
1687 module_i2c_driver(max1363_driver);
1688
1689 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1690 MODULE_DESCRIPTION("Maxim 1363 ADC");
1691 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes