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drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / infiniband / hw / bnxt_re / roce_hsi.h
bloba98fc9c2313e7e0cb8b38dc09afcfeaa8c3a51e6
1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: RoCE HSI File - Autogenerated
37 */
38
39 #ifndef __BNXT_RE_HSI_H__
40 #define __BNXT_RE_HSI_H__
41
42 /* include bnxt_hsi.h from bnxt_en driver */
43 #include "bnxt_hsi.h"
44
45 /* tx_doorbell (size:32b/4B) */
46 struct tx_doorbell {
47 __le32 key_idx;
48 #define TX_DOORBELL_IDX_MASK 0xffffffUL
49 #define TX_DOORBELL_IDX_SFT 0
50 #define TX_DOORBELL_KEY_MASK 0xf0000000UL
51 #define TX_DOORBELL_KEY_SFT 28
52 #define TX_DOORBELL_KEY_TX (0x0UL << 28)
53 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX
54 };
55
56 /* rx_doorbell (size:32b/4B) */
57 struct rx_doorbell {
58 __le32 key_idx;
59 #define RX_DOORBELL_IDX_MASK 0xffffffUL
60 #define RX_DOORBELL_IDX_SFT 0
61 #define RX_DOORBELL_KEY_MASK 0xf0000000UL
62 #define RX_DOORBELL_KEY_SFT 28
63 #define RX_DOORBELL_KEY_RX (0x1UL << 28)
64 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX
65 };
66
67 /* cmpl_doorbell (size:32b/4B) */
68 struct cmpl_doorbell {
69 __le32 key_mask_valid_idx;
70 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL
71 #define CMPL_DOORBELL_IDX_SFT 0
72 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL
73 #define CMPL_DOORBELL_MASK 0x8000000UL
74 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL
75 #define CMPL_DOORBELL_KEY_SFT 28
76 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
77 #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL
78 };
79
80 /* status_doorbell (size:32b/4B) */
81 struct status_doorbell {
82 __le32 key_idx;
83 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL
84 #define STATUS_DOORBELL_IDX_SFT 0
85 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL
86 #define STATUS_DOORBELL_KEY_SFT 28
87 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28)
88 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT
89 };
90
91 /* cmdq_init (size:128b/16B) */
92 struct cmdq_init {
93 __le64 cmdq_pbl;
94 __le16 cmdq_size_cmdq_lvl;
95 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL
96 #define CMDQ_INIT_CMDQ_LVL_SFT 0
97 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL
98 #define CMDQ_INIT_CMDQ_SIZE_SFT 2
99 __le16 creq_ring_id;
100 __le32 prod_idx;
101 };
102
103 /* cmdq_base (size:128b/16B) */
104 struct cmdq_base {
105 u8 opcode;
106 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL
107 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL
108 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL
109 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL
110 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL
111 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL
112 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL
113 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL
114 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL
115 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL
116 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL
117 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL
118 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL
119 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL
120 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL
121 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL
122 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL
123 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL
124 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL
125 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL
126 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL
127 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL
128 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL
129 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL
130 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL
131 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL
132 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL
133 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL
134 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL
135 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL
136 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL
137 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL
138 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL
139 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL
140 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL
141 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL
142 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL
143 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
144 #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL
145 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL
146 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
147 #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT
148 u8 cmd_size;
149 __le16 flags;
150 __le16 cookie;
151 u8 resp_size;
152 u8 reserved8;
153 __le64 resp_addr;
154 };
155
156 /* creq_base (size:128b/16B) */
157 struct creq_base {
158 u8 type;
159 #define CREQ_BASE_TYPE_MASK 0x3fUL
160 #define CREQ_BASE_TYPE_SFT 0
161 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL
162 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL
163 #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT
164 u8 reserved56[7];
165 u8 v;
166 #define CREQ_BASE_V 0x1UL
167 u8 event;
168 u8 reserved48[6];
169 };
170
171 /* cmdq_query_version (size:128b/16B) */
172 struct cmdq_query_version {
173 u8 opcode;
174 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL
175 #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION
176 u8 cmd_size;
177 __le16 flags;
178 __le16 cookie;
179 u8 resp_size;
180 u8 reserved8;
181 __le64 resp_addr;
182 };
183
184 /* creq_query_version_resp (size:128b/16B) */
185 struct creq_query_version_resp {
186 u8 type;
187 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL
188 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
189 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL
190 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT
191 u8 status;
192 __le16 cookie;
193 u8 fw_maj;
194 u8 fw_minor;
195 u8 fw_bld;
196 u8 fw_rsvd;
197 u8 v;
198 #define CREQ_QUERY_VERSION_RESP_V 0x1UL
199 u8 event;
200 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL
201 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST \
202 CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION
203 __le16 reserved16;
204 u8 intf_maj;
205 u8 intf_minor;
206 u8 intf_bld;
207 u8 intf_rsvd;
208 };
209
210 /* cmdq_initialize_fw (size:896b/112B) */
211 struct cmdq_initialize_fw {
212 u8 opcode;
213 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL
214 #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW
215 u8 cmd_size;
216 __le16 flags;
217 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
218 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL
219 #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED 0x8UL
220 #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT 0x10UL
221 __le16 cookie;
222 u8 resp_size;
223 u8 reserved8;
224 __le64 resp_addr;
225 u8 qpc_pg_size_qpc_lvl;
226 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL
227 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
228 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL
229 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL
230 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL
231 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2
232 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL
233 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4
234 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4)
235 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4)
236 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4)
237 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4)
238 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4)
239 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4)
240 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G
241 u8 mrw_pg_size_mrw_lvl;
242 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL
243 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
244 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL
245 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL
246 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL
247 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2
248 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL
249 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4
250 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4)
251 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4)
252 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4)
253 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4)
254 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4)
255 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4)
256 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G
257 u8 srq_pg_size_srq_lvl;
258 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL
259 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
260 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL
261 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL
262 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL
263 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2
264 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL
265 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4
266 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
267 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
268 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
269 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
270 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
271 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
272 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G
273 u8 cq_pg_size_cq_lvl;
274 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL
275 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
276 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL
277 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL
278 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL
279 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2
280 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL
281 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4
282 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4)
283 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4)
284 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4)
285 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4)
286 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4)
287 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4)
288 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G
289 u8 tqm_pg_size_tqm_lvl;
290 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL
291 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
292 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL
293 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL
294 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL
295 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2
296 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL
297 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4
298 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4)
299 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4)
300 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4)
301 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4)
302 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4)
303 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4)
304 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G
305 u8 tim_pg_size_tim_lvl;
306 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL
307 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
308 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL
309 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL
310 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL
311 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2
312 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL
313 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4
314 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4)
315 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4)
316 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4)
317 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4)
318 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4)
319 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4)
320 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G
321 __le16 log2_dbr_pg_size;
322 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL
323 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0
324 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL
325 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL
326 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL
327 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL
328 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL
329 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL
330 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL
331 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL
332 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL
333 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL
334 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL
335 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL
336 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL
337 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL
338 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL
339 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL
340 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \
341 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
342 #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL
343 #define CMDQ_INITIALIZE_FW_RSVD_SFT 4
344 __le64 qpc_page_dir;
345 __le64 mrw_page_dir;
346 __le64 srq_page_dir;
347 __le64 cq_page_dir;
348 __le64 tqm_page_dir;
349 __le64 tim_page_dir;
350 __le32 number_of_qp;
351 __le32 number_of_mrw;
352 __le32 number_of_srq;
353 __le32 number_of_cq;
354 __le32 max_qp_per_vf;
355 __le32 max_mrw_per_vf;
356 __le32 max_srq_per_vf;
357 __le32 max_cq_per_vf;
358 __le32 max_gid_per_vf;
359 __le32 stat_ctx_id;
360 };
361
362 /* creq_initialize_fw_resp (size:128b/16B) */
363 struct creq_initialize_fw_resp {
364 u8 type;
365 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
366 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
367 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
368 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT
369 u8 status;
370 __le16 cookie;
371 __le32 reserved32;
372 u8 v;
373 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL
374 u8 event;
375 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL
376 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \
377 CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW
378 u8 reserved48[6];
379 };
380
381 /* cmdq_deinitialize_fw (size:128b/16B) */
382 struct cmdq_deinitialize_fw {
383 u8 opcode;
384 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL
385 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \
386 CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW
387 u8 cmd_size;
388 __le16 flags;
389 __le16 cookie;
390 u8 resp_size;
391 u8 reserved8;
392 __le64 resp_addr;
393 };
394
395 /* creq_deinitialize_fw_resp (size:128b/16B) */
396 struct creq_deinitialize_fw_resp {
397 u8 type;
398 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
399 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
400 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
401 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT
402 u8 status;
403 __le16 cookie;
404 __le32 reserved32;
405 u8 v;
406 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL
407 u8 event;
408 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL
409 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \
410 CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW
411 u8 reserved48[6];
412 };
413
414 /* cmdq_create_qp (size:832b/104B) */
415 struct cmdq_create_qp {
416 u8 opcode;
417 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL
418 #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP
419 u8 cmd_size;
420 __le16 flags;
421 __le16 cookie;
422 u8 resp_size;
423 u8 reserved8;
424 __le64 resp_addr;
425 __le64 qp_handle;
426 __le32 qp_flags;
427 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL
428 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL
429 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
430 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL
431 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL
432 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL
433 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL
434 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL
435 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED 0x100UL
436 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID 0x200UL
437 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 0x400UL
438 #define CMDQ_CREATE_QP_QP_FLAGS_LAST \
439 CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED
440 u8 type;
441 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL
442 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL
443 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL
444 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL
445 #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI
446 u8 sq_pg_size_sq_lvl;
447 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL
448 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0
449 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL
450 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL
451 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL
452 #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2
453 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL
454 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4
455 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4)
456 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4)
457 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4)
458 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4)
459 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4)
460 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4)
461 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G
462 u8 rq_pg_size_rq_lvl;
463 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL
464 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0
465 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL
466 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL
467 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL
468 #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2
469 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL
470 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4
471 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4)
472 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4)
473 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4)
474 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4)
475 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4)
476 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4)
477 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G
478 u8 unused_0;
479 __le32 dpi;
480 __le32 sq_size;
481 __le32 rq_size;
482 __le16 sq_fwo_sq_sge;
483 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL
484 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0
485 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL
486 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4
487 __le16 rq_fwo_rq_sge;
488 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL
489 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0
490 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL
491 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4
492 __le32 scq_cid;
493 __le32 rcq_cid;
494 __le32 srq_cid;
495 __le32 pd_id;
496 __le64 sq_pbl;
497 __le64 rq_pbl;
498 __le64 irrq_addr;
499 __le64 orrq_addr;
500 __le32 request_xid;
501 __le16 steering_tag;
502 __le16 reserved16;
503 };
504
505 /* creq_create_qp_resp (size:128b/16B) */
506 struct creq_create_qp_resp {
507 u8 type;
508 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL
509 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0
510 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL
511 #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT
512 u8 status;
513 __le16 cookie;
514 __le32 xid;
515 u8 v;
516 #define CREQ_CREATE_QP_RESP_V 0x1UL
517 u8 event;
518 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL
519 #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP
520 u8 optimized_transmit_enabled;
521 u8 reserved48[5];
522 };
523
524 /* cmdq_destroy_qp (size:192b/24B) */
525 struct cmdq_destroy_qp {
526 u8 opcode;
527 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL
528 #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP
529 u8 cmd_size;
530 __le16 flags;
531 __le16 cookie;
532 u8 resp_size;
533 u8 reserved8;
534 __le64 resp_addr;
535 __le32 qp_cid;
536 __le32 unused_0;
537 };
538
539 /* creq_destroy_qp_resp (size:128b/16B) */
540 struct creq_destroy_qp_resp {
541 u8 type;
542 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL
543 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
544 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL
545 #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT
546 u8 status;
547 __le16 cookie;
548 __le32 xid;
549 u8 v;
550 #define CREQ_DESTROY_QP_RESP_V 0x1UL
551 u8 event;
552 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL
553 #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP
554 u8 reserved48[6];
555 };
556
557 /* cmdq_modify_qp (size:1024b/128B) */
558 struct cmdq_modify_qp {
559 u8 opcode;
560 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL
561 #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP
562 u8 cmd_size;
563 __le16 flags;
564 #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED 0x1UL
565 __le16 cookie;
566 u8 resp_size;
567 u8 qp_type;
568 #define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL
569 #define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL
570 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL
571 #define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL
572 #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI
573 __le64 resp_addr;
574 __le32 modify_mask;
575 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL
576 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL
577 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL
578 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL
579 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL
580 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL
581 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL
582 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL
583 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL
584 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL
585 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL
586 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL
587 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL
588 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL
589 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL
590 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL
591 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL
592 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL
593 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL
594 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL
595 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL
596 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL
597 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL
598 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL
599 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL
600 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL
601 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL
602 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL
603 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL
604 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL
605 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL
606 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL
607 __le32 qp_cid;
608 u8 network_type_en_sqd_async_notify_new_state;
609 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL
610 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
611 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL
612 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL
613 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL
614 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL
615 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL
616 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL
617 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL
618 #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR
619 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL
620 #define CMDQ_MODIFY_QP_UNUSED1 0x20UL
621 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL
622 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6
623 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6)
624 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6)
625 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6)
626 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6
627 u8 access;
628 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL
629 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
630 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL
631 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL
632 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL
633 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL
634 __le16 pkey;
635 __le32 qkey;
636 __le32 dgid[4];
637 __le32 flow_label;
638 __le16 sgid_index;
639 u8 hop_limit;
640 u8 traffic_class;
641 __le16 dest_mac[3];
642 u8 tos_dscp_tos_ecn;
643 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL
644 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
645 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL
646 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
647 u8 path_mtu_pingpong_push_enable;
648 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL
649 #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL
650 #define CMDQ_MODIFY_QP_UNUSED3_SFT 1
651 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL
652 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4
653 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4)
654 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4)
655 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4)
656 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4)
657 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4)
658 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4)
659 #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192
660 u8 timeout;
661 u8 retry_cnt;
662 u8 rnr_retry;
663 u8 min_rnr_timer;
664 __le32 rq_psn;
665 __le32 sq_psn;
666 u8 max_rd_atomic;
667 u8 max_dest_rd_atomic;
668 __le16 enable_cc;
669 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL
670 #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL
671 #define CMDQ_MODIFY_QP_UNUSED15_SFT 1
672 __le32 sq_size;
673 __le32 rq_size;
674 __le16 sq_sge;
675 __le16 rq_sge;
676 __le32 max_inline_data;
677 __le32 dest_qp_id;
678 __le32 pingpong_push_dpi;
679 __le16 src_mac[3];
680 __le16 vlan_pcp_vlan_dei_vlan_id;
681 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL
682 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
683 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL
684 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL
685 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
686 __le64 irrq_addr;
687 __le64 orrq_addr;
688 __le32 ext_modify_mask;
689 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL
690 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL
691 __le32 ext_stats_ctx_id;
692 __le16 schq_id;
693 __le16 unused_0;
694 __le32 reserved32;
695 };
696
697 /* creq_modify_qp_resp (size:128b/16B) */
698 struct creq_modify_qp_resp {
699 u8 type;
700 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL
701 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
702 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL
703 #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT
704 u8 status;
705 __le16 cookie;
706 __le32 xid;
707 u8 v;
708 #define CREQ_MODIFY_QP_RESP_V 0x1UL
709 u8 event;
710 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL
711 #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP
712 u8 pingpong_push_state_index_enabled;
713 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL
714 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL
715 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1
716 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL
717 u8 reserved8;
718 __le32 lag_src_mac;
719 };
720
721 /* cmdq_query_qp (size:192b/24B) */
722 struct cmdq_query_qp {
723 u8 opcode;
724 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL
725 #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP
726 u8 cmd_size;
727 __le16 flags;
728 __le16 cookie;
729 u8 resp_size;
730 u8 reserved8;
731 __le64 resp_addr;
732 __le32 qp_cid;
733 __le32 unused_0;
734 };
735
736 /* creq_query_qp_resp (size:128b/16B) */
737 struct creq_query_qp_resp {
738 u8 type;
739 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL
740 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0
741 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL
742 #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT
743 u8 status;
744 __le16 cookie;
745 __le32 size;
746 u8 v;
747 #define CREQ_QUERY_QP_RESP_V 0x1UL
748 u8 event;
749 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL
750 #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP
751 u8 reserved48[6];
752 };
753
754 /* creq_query_qp_resp_sb (size:832b/104B) */
755 struct creq_query_qp_resp_sb {
756 u8 opcode;
757 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL
758 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP
759 u8 status;
760 __le16 cookie;
761 __le16 flags;
762 u8 resp_size;
763 u8 reserved8;
764 __le32 xid;
765 u8 en_sqd_async_notify_state;
766 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL
767 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
768 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL
769 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL
770 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL
771 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL
772 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL
773 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL
774 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL
775 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR
776 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL
777 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL
778 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5
779 u8 access;
780 #define \
781 CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\
782 0xffUL
783 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\
784 0
785 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL
786 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL
787 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL
788 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL
789 __le16 pkey;
790 __le32 qkey;
791 __le32 reserved32;
792 __le32 dgid[4];
793 __le32 flow_label;
794 __le16 sgid_index;
795 u8 hop_limit;
796 u8 traffic_class;
797 __le16 dest_mac[3];
798 __le16 path_mtu_dest_vlan_id;
799 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL
800 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
801 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL
802 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12
803 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12)
804 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12)
805 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12)
806 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12)
807 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12)
808 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12)
809 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192
810 u8 timeout;
811 u8 retry_cnt;
812 u8 rnr_retry;
813 u8 min_rnr_timer;
814 __le32 rq_psn;
815 __le32 sq_psn;
816 u8 max_rd_atomic;
817 u8 max_dest_rd_atomic;
818 u8 tos_dscp_tos_ecn;
819 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL
820 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
821 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL
822 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
823 u8 enable_cc;
824 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL
825 __le32 sq_size;
826 __le32 rq_size;
827 __le16 sq_sge;
828 __le16 rq_sge;
829 __le32 max_inline_data;
830 __le32 dest_qp_id;
831 __le16 port_id;
832 u8 unused_0;
833 u8 stat_collection_id;
834 __le16 src_mac[3];
835 __le16 vlan_pcp_vlan_dei_vlan_id;
836 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL
837 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
838 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL
839 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL
840 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
841 };
842
843 /* cmdq_query_qp_extend (size:192b/24B) */
844 struct cmdq_query_qp_extend {
845 u8 opcode;
846 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL
847 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND
848 u8 cmd_size;
849 __le16 flags;
850 __le16 cookie;
851 u8 resp_size;
852 u8 num_qps;
853 __le64 resp_addr;
854 __le32 function_id;
855 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL
856 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0
857 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL
858 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8
859 #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL
860 __le32 current_index;
861 };
862
863 /* creq_query_qp_extend_resp (size:128b/16B) */
864 struct creq_query_qp_extend_resp {
865 u8 type;
866 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL
867 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0
868 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL
869 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT
870 u8 status;
871 __le16 cookie;
872 __le32 size;
873 u8 v;
874 #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL
875 u8 event;
876 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL
877 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND
878 __le16 reserved16;
879 __le32 current_index;
880 };
881
882 /* creq_query_qp_extend_resp_sb (size:384b/48B) */
883 struct creq_query_qp_extend_resp_sb {
884 u8 opcode;
885 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL
886 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \
887 CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND
888 u8 status;
889 __le16 cookie;
890 __le16 flags;
891 u8 resp_size;
892 u8 reserved8;
893 __le32 xid;
894 u8 state;
895 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL
896 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0
897 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL
898 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL
899 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL
900 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL
901 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL
902 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL
903 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL
904 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR
905 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL
906 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4
907 u8 reserved_8;
908 __le16 port_id;
909 __le32 qkey;
910 __le16 sgid_index;
911 u8 network_type;
912 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL
913 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
914 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
915 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \
916 CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6
917 u8 unused_0;
918 __le32 dgid[4];
919 __le32 dest_qp_id;
920 u8 stat_collection_id;
921 u8 reservred_8;
922 __le16 reserved_16;
923 };
924
925 /* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */
926 struct creq_query_qp_extend_resp_sb_tlv {
927 __le16 cmd_discr;
928 u8 reserved_8b;
929 u8 tlv_flags;
930 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
931 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
932 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
933 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
934 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
935 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
936 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
937 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
938 __le16 tlv_type;
939 __le16 length;
940 u8 total_size;
941 u8 reserved56[7];
942 u8 opcode;
943 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL
944 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \
945 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND
946 u8 status;
947 __le16 cookie;
948 __le16 flags;
949 u8 resp_size;
950 u8 reserved8;
951 __le32 xid;
952 u8 state;
953 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL
954 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0
955 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL
956 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL
957 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL
958 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL
959 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL
960 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL
961 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL
962 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \
963 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR
964 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL
965 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4
966 u8 reserved_8;
967 __le16 port_id;
968 __le32 qkey;
969 __le16 sgid_index;
970 u8 network_type;
971 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL
972 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
973 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
974 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \
975 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6
976 u8 unused_0;
977 __le32 dgid[4];
978 __le32 dest_qp_id;
979 u8 stat_collection_id;
980 u8 reservred_8;
981 __le16 reserved_16;
982 };
983
984 /* cmdq_create_srq (size:448b/56B) */
985 struct cmdq_create_srq {
986 u8 opcode;
987 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL
988 #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ
989 u8 cmd_size;
990 __le16 flags;
991 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL
992 __le16 cookie;
993 u8 resp_size;
994 u8 reserved8;
995 __le64 resp_addr;
996 __le64 srq_handle;
997 __le16 pg_size_lvl;
998 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL
999 #define CMDQ_CREATE_SRQ_LVL_SFT 0
1000 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL
1001 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL
1002 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL
1003 #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2
1004 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL
1005 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2
1006 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2)
1007 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2)
1008 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2)
1009 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2)
1010 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2)
1011 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2)
1012 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G
1013 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL
1014 #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5
1015 __le16 eventq_id;
1016 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL
1017 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
1018 #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL
1019 #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12
1020 __le16 srq_size;
1021 __le16 srq_fwo;
1022 __le32 dpi;
1023 __le32 pd_id;
1024 __le64 pbl;
1025 __le16 steering_tag;
1026 u8 reserved48[6];
1027 };
1028
1029 /* creq_create_srq_resp (size:128b/16B) */
1030 struct creq_create_srq_resp {
1031 u8 type;
1032 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL
1033 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
1034 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1035 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT
1036 u8 status;
1037 __le16 cookie;
1038 __le32 xid;
1039 u8 v;
1040 #define CREQ_CREATE_SRQ_RESP_V 0x1UL
1041 u8 event;
1042 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL
1043 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ
1044 u8 reserved48[6];
1045 };
1046
1047 /* cmdq_destroy_srq (size:192b/24B) */
1048 struct cmdq_destroy_srq {
1049 u8 opcode;
1050 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL
1051 #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ
1052 u8 cmd_size;
1053 __le16 flags;
1054 __le16 cookie;
1055 u8 resp_size;
1056 u8 reserved8;
1057 __le64 resp_addr;
1058 __le32 srq_cid;
1059 __le32 unused_0;
1060 };
1061
1062 /* creq_destroy_srq_resp (size:128b/16B) */
1063 struct creq_destroy_srq_resp {
1064 u8 type;
1065 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL
1066 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
1067 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1068 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT
1069 u8 status;
1070 __le16 cookie;
1071 __le32 xid;
1072 u8 v;
1073 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL
1074 u8 event;
1075 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL
1076 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ
1077 __le16 enable_for_arm[3];
1078 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL
1079 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0
1080 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL
1081 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
1082 };
1083
1084 /* cmdq_query_srq (size:192b/24B) */
1085 struct cmdq_query_srq {
1086 u8 opcode;
1087 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL
1088 #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ
1089 u8 cmd_size;
1090 __le16 flags;
1091 __le16 cookie;
1092 u8 resp_size;
1093 u8 reserved8;
1094 __le64 resp_addr;
1095 __le32 srq_cid;
1096 __le32 unused_0;
1097 };
1098
1099 /* creq_query_srq_resp (size:128b/16B) */
1100 struct creq_query_srq_resp {
1101 u8 type;
1102 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL
1103 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
1104 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1105 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT
1106 u8 status;
1107 __le16 cookie;
1108 __le32 size;
1109 u8 v;
1110 #define CREQ_QUERY_SRQ_RESP_V 0x1UL
1111 u8 event;
1112 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL
1113 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ
1114 u8 reserved48[6];
1115 };
1116
1117 /* creq_query_srq_resp_sb (size:256b/32B) */
1118 struct creq_query_srq_resp_sb {
1119 u8 opcode;
1120 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL
1121 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ
1122 u8 status;
1123 __le16 cookie;
1124 __le16 flags;
1125 u8 resp_size;
1126 u8 reserved8;
1127 __le32 xid;
1128 __le16 srq_limit;
1129 __le16 reserved16;
1130 __le32 data[4];
1131 };
1132
1133 /* cmdq_create_cq (size:448b/56B) */
1134 struct cmdq_create_cq {
1135 u8 opcode;
1136 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL
1137 #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ
1138 u8 cmd_size;
1139 __le16 flags;
1140 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL
1141 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL
1142 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL
1143 #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID 0x8UL
1144 __le16 cookie;
1145 u8 resp_size;
1146 u8 reserved8;
1147 __le64 resp_addr;
1148 __le64 cq_handle;
1149 __le32 pg_size_lvl;
1150 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL
1151 #define CMDQ_CREATE_CQ_LVL_SFT 0
1152 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL
1153 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL
1154 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL
1155 #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2
1156 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL
1157 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2
1158 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1159 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1160 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1161 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1162 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1163 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1164 #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G
1165 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL
1166 #define CMDQ_CREATE_CQ_UNUSED27_SFT 5
1167 __le32 cq_fco_cnq_id;
1168 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL
1169 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
1170 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL
1171 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
1172 __le32 dpi;
1173 __le32 cq_size;
1174 __le64 pbl;
1175 __le16 steering_tag;
1176 u8 reserved48[2];
1177 __le32 coalescing;
1178 #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK 0x1ffUL
1179 #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0
1180 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK 0x3e00UL
1181 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9
1182 #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK 0x7c000UL
1183 #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14
1184 #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE 0x80000UL
1185 #define CMDQ_CREATE_CQ_UNUSED12_MASK 0xfff00000UL
1186 #define CMDQ_CREATE_CQ_UNUSED12_SFT 20
1187 __le64 reserved64;
1188 };
1189
1190 /* creq_create_cq_resp (size:128b/16B) */
1191 struct creq_create_cq_resp {
1192 u8 type;
1193 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL
1194 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
1195 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1196 #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT
1197 u8 status;
1198 __le16 cookie;
1199 __le32 xid;
1200 u8 v;
1201 #define CREQ_CREATE_CQ_RESP_V 0x1UL
1202 u8 event;
1203 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL
1204 #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ
1205 u8 reserved48[6];
1206 };
1207
1208 /* cmdq_destroy_cq (size:192b/24B) */
1209 struct cmdq_destroy_cq {
1210 u8 opcode;
1211 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL
1212 #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ
1213 u8 cmd_size;
1214 __le16 flags;
1215 __le16 cookie;
1216 u8 resp_size;
1217 u8 reserved8;
1218 __le64 resp_addr;
1219 __le32 cq_cid;
1220 __le32 unused_0;
1221 };
1222
1223 /* creq_destroy_cq_resp (size:128b/16B) */
1224 struct creq_destroy_cq_resp {
1225 u8 type;
1226 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL
1227 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
1228 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL
1229 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT
1230 u8 status;
1231 __le16 cookie;
1232 __le32 xid;
1233 u8 v;
1234 #define CREQ_DESTROY_CQ_RESP_V 0x1UL
1235 u8 event;
1236 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL
1237 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ
1238 __le16 cq_arm_lvl;
1239 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL
1240 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
1241 __le16 total_cnq_events;
1242 __le16 reserved16;
1243 };
1244
1245 /* cmdq_resize_cq (size:320b/40B) */
1246 struct cmdq_resize_cq {
1247 u8 opcode;
1248 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL
1249 #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ
1250 u8 cmd_size;
1251 __le16 flags;
1252 __le16 cookie;
1253 u8 resp_size;
1254 u8 reserved8;
1255 __le64 resp_addr;
1256 __le32 cq_cid;
1257 __le32 new_cq_size_pg_size_lvl;
1258 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL
1259 #define CMDQ_RESIZE_CQ_LVL_SFT 0
1260 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL
1261 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL
1262 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL
1263 #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2
1264 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL
1265 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2
1266 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1267 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1268 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1269 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1270 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1271 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1272 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G
1273 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL
1274 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
1275 __le64 new_pbl;
1276 __le32 new_cq_fco;
1277 __le32 unused_0;
1278 };
1279
1280 /* creq_resize_cq_resp (size:128b/16B) */
1281 struct creq_resize_cq_resp {
1282 u8 type;
1283 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL
1284 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
1285 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1286 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT
1287 u8 status;
1288 __le16 cookie;
1289 __le32 xid;
1290 u8 v;
1291 #define CREQ_RESIZE_CQ_RESP_V 0x1UL
1292 u8 event;
1293 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL
1294 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ
1295 u8 reserved48[6];
1296 };
1297
1298 /* cmdq_allocate_mrw (size:256b/32B) */
1299 struct cmdq_allocate_mrw {
1300 u8 opcode;
1301 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL
1302 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW
1303 u8 cmd_size;
1304 __le16 flags;
1305 __le16 cookie;
1306 u8 resp_size;
1307 u8 reserved8;
1308 __le64 resp_addr;
1309 __le64 mrw_handle;
1310 u8 mrw_flags;
1311 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL
1312 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
1313 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL
1314 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL
1315 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL
1316 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL
1317 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL
1318 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B
1319 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID 0x10UL
1320 #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xe0UL
1321 #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 5
1322 u8 access;
1323 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL
1324 __le16 steering_tag;
1325 __le32 pd_id;
1326 };
1327
1328 /* creq_allocate_mrw_resp (size:128b/16B) */
1329 struct creq_allocate_mrw_resp {
1330 u8 type;
1331 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL
1332 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
1333 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL
1334 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT
1335 u8 status;
1336 __le16 cookie;
1337 __le32 xid;
1338 u8 v;
1339 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL
1340 u8 event;
1341 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL
1342 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW
1343 u8 reserved48[6];
1344 };
1345
1346 /* cmdq_deallocate_key (size:192b/24B) */
1347 struct cmdq_deallocate_key {
1348 u8 opcode;
1349 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL
1350 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY
1351 u8 cmd_size;
1352 __le16 flags;
1353 __le16 cookie;
1354 u8 resp_size;
1355 u8 reserved8;
1356 __le64 resp_addr;
1357 u8 mrw_flags;
1358 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL
1359 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
1360 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL
1361 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL
1362 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL
1363 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL
1364 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL
1365 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B
1366 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL
1367 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4
1368 u8 unused24[3];
1369 __le32 key;
1370 };
1371
1372 /* creq_deallocate_key_resp (size:128b/16B) */
1373 struct creq_deallocate_key_resp {
1374 u8 type;
1375 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL
1376 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
1377 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL
1378 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT
1379 u8 status;
1380 __le16 cookie;
1381 __le32 xid;
1382 u8 v;
1383 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL
1384 u8 event;
1385 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL
1386 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY
1387 __le16 reserved16;
1388 __le32 bound_window_info;
1389 };
1390
1391 /* cmdq_register_mr (size:448b/56B) */
1392 struct cmdq_register_mr {
1393 u8 opcode;
1394 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL
1395 #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR
1396 u8 cmd_size;
1397 __le16 flags;
1398 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL
1399 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL
1400 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO 0x4UL
1401 __le16 cookie;
1402 u8 resp_size;
1403 u8 reserved8;
1404 __le64 resp_addr;
1405 u8 log2_pg_size_lvl;
1406 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL
1407 #define CMDQ_REGISTER_MR_LVL_SFT 0
1408 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL
1409 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL
1410 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL
1411 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2
1412 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL
1413 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2
1414 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2)
1415 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2)
1416 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2)
1417 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2)
1418 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2)
1419 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2)
1420 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2)
1421 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2)
1422 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
1423 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL
1424 u8 access;
1425 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL
1426 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL
1427 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL
1428 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL
1429 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL
1430 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL
1431 __le16 log2_pbl_pg_size;
1432 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL
1433 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
1434 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL
1435 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL
1436 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL
1437 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL
1438 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL
1439 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL
1440 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL
1441 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL
1442 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
1443 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL
1444 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5
1445 __le32 key;
1446 __le64 pbl;
1447 __le64 va;
1448 __le64 mr_size;
1449 __le16 steering_tag;
1450 u8 reserved48[6];
1451 };
1452
1453 /* creq_register_mr_resp (size:128b/16B) */
1454 struct creq_register_mr_resp {
1455 u8 type;
1456 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL
1457 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
1458 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1459 #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT
1460 u8 status;
1461 __le16 cookie;
1462 __le32 xid;
1463 u8 v;
1464 #define CREQ_REGISTER_MR_RESP_V 0x1UL
1465 u8 event;
1466 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL
1467 #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR
1468 u8 reserved48[6];
1469 };
1470
1471 /* cmdq_deregister_mr (size:192b/24B) */
1472 struct cmdq_deregister_mr {
1473 u8 opcode;
1474 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL
1475 #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR
1476 u8 cmd_size;
1477 __le16 flags;
1478 __le16 cookie;
1479 u8 resp_size;
1480 u8 reserved8;
1481 __le64 resp_addr;
1482 __le32 lkey;
1483 __le32 unused_0;
1484 };
1485
1486 /* creq_deregister_mr_resp (size:128b/16B) */
1487 struct creq_deregister_mr_resp {
1488 u8 type;
1489 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL
1490 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
1491 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1492 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT
1493 u8 status;
1494 __le16 cookie;
1495 __le32 xid;
1496 u8 v;
1497 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL
1498 u8 event;
1499 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL
1500 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR
1501 __le16 reserved16;
1502 __le32 bound_windows;
1503 };
1504
1505 /* cmdq_add_gid (size:384b/48B) */
1506 struct cmdq_add_gid {
1507 u8 opcode;
1508 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL
1509 #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID
1510 u8 cmd_size;
1511 __le16 flags;
1512 __le16 cookie;
1513 u8 resp_size;
1514 u8 reserved8;
1515 __le64 resp_addr;
1516 __be32 gid[4];
1517 __be16 src_mac[3];
1518 __le16 vlan;
1519 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1520 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1521 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL
1522 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
1523 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL
1524 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12
1525 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1526 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1527 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1528 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1529 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1530 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1531 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1532 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1533 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1534 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL
1535 __le16 ipid;
1536 __le16 stats_ctx;
1537 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL
1538 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0
1539 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1540 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1541 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1542 __le32 unused_0;
1543 };
1544
1545 /* creq_add_gid_resp (size:128b/16B) */
1546 struct creq_add_gid_resp {
1547 u8 type;
1548 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL
1549 #define CREQ_ADD_GID_RESP_TYPE_SFT 0
1550 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL
1551 #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT
1552 u8 status;
1553 __le16 cookie;
1554 __le32 xid;
1555 u8 v;
1556 #define CREQ_ADD_GID_RESP_V 0x1UL
1557 u8 event;
1558 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL
1559 #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID
1560 u8 reserved48[6];
1561 };
1562
1563 /* cmdq_delete_gid (size:192b/24B) */
1564 struct cmdq_delete_gid {
1565 u8 opcode;
1566 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL
1567 #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID
1568 u8 cmd_size;
1569 __le16 flags;
1570 __le16 cookie;
1571 u8 resp_size;
1572 u8 reserved8;
1573 __le64 resp_addr;
1574 __le16 gid_index;
1575 u8 unused_0[6];
1576 };
1577
1578 /* creq_delete_gid_resp (size:128b/16B) */
1579 struct creq_delete_gid_resp {
1580 u8 type;
1581 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL
1582 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0
1583 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL
1584 #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT
1585 u8 status;
1586 __le16 cookie;
1587 __le32 xid;
1588 u8 v;
1589 #define CREQ_DELETE_GID_RESP_V 0x1UL
1590 u8 event;
1591 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL
1592 #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID
1593 u8 reserved48[6];
1594 };
1595
1596 /* cmdq_modify_gid (size:384b/48B) */
1597 struct cmdq_modify_gid {
1598 u8 opcode;
1599 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL
1600 #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID
1601 u8 cmd_size;
1602 __le16 flags;
1603 __le16 cookie;
1604 u8 resp_size;
1605 u8 reserved8;
1606 __le64 resp_addr;
1607 __be32 gid[4];
1608 __be16 src_mac[3];
1609 __le16 vlan;
1610 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL
1611 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
1612 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL
1613 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12
1614 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1615 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1616 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1617 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1618 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1619 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1620 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1621 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1622 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1623 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL
1624 __le16 ipid;
1625 __le16 gid_index;
1626 __le16 stats_ctx;
1627 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1628 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1629 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1630 __le16 unused_0;
1631 };
1632
1633 /* creq_modify_gid_resp (size:128b/16B) */
1634 struct creq_modify_gid_resp {
1635 u8 type;
1636 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL
1637 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
1638 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL
1639 #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT
1640 u8 status;
1641 __le16 cookie;
1642 __le32 xid;
1643 u8 v;
1644 #define CREQ_MODIFY_GID_RESP_V 0x1UL
1645 u8 event;
1646 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL
1647 #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID
1648 u8 reserved48[6];
1649 };
1650
1651 /* cmdq_query_gid (size:192b/24B) */
1652 struct cmdq_query_gid {
1653 u8 opcode;
1654 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL
1655 #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID
1656 u8 cmd_size;
1657 __le16 flags;
1658 __le16 cookie;
1659 u8 resp_size;
1660 u8 reserved8;
1661 __le64 resp_addr;
1662 __le16 gid_index;
1663 u8 unused16[6];
1664 };
1665
1666 /* creq_query_gid_resp (size:128b/16B) */
1667 struct creq_query_gid_resp {
1668 u8 type;
1669 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL
1670 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0
1671 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL
1672 #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT
1673 u8 status;
1674 __le16 cookie;
1675 __le32 size;
1676 u8 v;
1677 #define CREQ_QUERY_GID_RESP_V 0x1UL
1678 u8 event;
1679 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL
1680 #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID
1681 u8 reserved48[6];
1682 };
1683
1684 /* creq_query_gid_resp_sb (size:320b/40B) */
1685 struct creq_query_gid_resp_sb {
1686 u8 opcode;
1687 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL
1688 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID
1689 u8 status;
1690 __le16 cookie;
1691 __le16 flags;
1692 u8 resp_size;
1693 u8 reserved8;
1694 __le32 gid[4];
1695 __le16 src_mac[3];
1696 __le16 vlan;
1697 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1698 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1699 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL
1700 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
1701 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL
1702 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12
1703 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1704 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12)
1705 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12)
1706 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12)
1707 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12)
1708 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1709 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1710 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1711 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
1712 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL
1713 __le16 ipid;
1714 __le16 gid_index;
1715 __le32 unused_0;
1716 };
1717
1718 /* cmdq_create_qp1 (size:640b/80B) */
1719 struct cmdq_create_qp1 {
1720 u8 opcode;
1721 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL
1722 #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1
1723 u8 cmd_size;
1724 __le16 flags;
1725 __le16 cookie;
1726 u8 resp_size;
1727 u8 reserved8;
1728 __le64 resp_addr;
1729 __le64 qp_handle;
1730 __le32 qp_flags;
1731 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL
1732 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL
1733 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
1734 #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE
1735 u8 type;
1736 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL
1737 #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI
1738 u8 sq_pg_size_sq_lvl;
1739 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL
1740 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
1741 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL
1742 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL
1743 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL
1744 #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2
1745 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL
1746 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4
1747 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4)
1748 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4)
1749 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4)
1750 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4)
1751 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4)
1752 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4)
1753 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G
1754 u8 rq_pg_size_rq_lvl;
1755 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL
1756 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
1757 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL
1758 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL
1759 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL
1760 #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2
1761 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL
1762 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4
1763 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4)
1764 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4)
1765 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4)
1766 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4)
1767 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4)
1768 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4)
1769 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G
1770 u8 unused_0;
1771 __le32 dpi;
1772 __le32 sq_size;
1773 __le32 rq_size;
1774 __le16 sq_fwo_sq_sge;
1775 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL
1776 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
1777 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL
1778 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4
1779 __le16 rq_fwo_rq_sge;
1780 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL
1781 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
1782 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL
1783 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4
1784 __le32 scq_cid;
1785 __le32 rcq_cid;
1786 __le32 srq_cid;
1787 __le32 pd_id;
1788 __le64 sq_pbl;
1789 __le64 rq_pbl;
1790 };
1791
1792 /* creq_create_qp1_resp (size:128b/16B) */
1793 struct creq_create_qp1_resp {
1794 u8 type;
1795 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL
1796 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
1797 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL
1798 #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT
1799 u8 status;
1800 __le16 cookie;
1801 __le32 xid;
1802 u8 v;
1803 #define CREQ_CREATE_QP1_RESP_V 0x1UL
1804 u8 event;
1805 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL
1806 #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1
1807 u8 reserved48[6];
1808 };
1809
1810 /* cmdq_destroy_qp1 (size:192b/24B) */
1811 struct cmdq_destroy_qp1 {
1812 u8 opcode;
1813 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL
1814 #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1
1815 u8 cmd_size;
1816 __le16 flags;
1817 __le16 cookie;
1818 u8 resp_size;
1819 u8 reserved8;
1820 __le64 resp_addr;
1821 __le32 qp1_cid;
1822 __le32 unused_0;
1823 };
1824
1825 /* creq_destroy_qp1_resp (size:128b/16B) */
1826 struct creq_destroy_qp1_resp {
1827 u8 type;
1828 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL
1829 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
1830 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL
1831 #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT
1832 u8 status;
1833 __le16 cookie;
1834 __le32 xid;
1835 u8 v;
1836 #define CREQ_DESTROY_QP1_RESP_V 0x1UL
1837 u8 event;
1838 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL
1839 #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1
1840 u8 reserved48[6];
1841 };
1842
1843 /* cmdq_create_ah (size:512b/64B) */
1844 struct cmdq_create_ah {
1845 u8 opcode;
1846 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL
1847 #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH
1848 u8 cmd_size;
1849 __le16 flags;
1850 __le16 cookie;
1851 u8 resp_size;
1852 u8 reserved8;
1853 __le64 resp_addr;
1854 __le64 ah_handle;
1855 __le32 dgid[4];
1856 u8 type;
1857 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL
1858 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL
1859 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL
1860 #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6
1861 u8 hop_limit;
1862 __le16 sgid_index;
1863 __le32 dest_vlan_id_flow_label;
1864 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL
1865 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
1866 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL
1867 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20
1868 __le32 pd_id;
1869 __le32 unused_0;
1870 __le16 dest_mac[3];
1871 u8 traffic_class;
1872 u8 enable_cc;
1873 #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL
1874 };
1875
1876 /* creq_create_ah_resp (size:128b/16B) */
1877 struct creq_create_ah_resp {
1878 u8 type;
1879 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL
1880 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0
1881 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL
1882 #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT
1883 u8 status;
1884 __le16 cookie;
1885 __le32 xid;
1886 u8 v;
1887 #define CREQ_CREATE_AH_RESP_V 0x1UL
1888 u8 event;
1889 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL
1890 #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH
1891 u8 reserved48[6];
1892 };
1893
1894 /* cmdq_destroy_ah (size:192b/24B) */
1895 struct cmdq_destroy_ah {
1896 u8 opcode;
1897 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL
1898 #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH
1899 u8 cmd_size;
1900 __le16 flags;
1901 __le16 cookie;
1902 u8 resp_size;
1903 u8 reserved8;
1904 __le64 resp_addr;
1905 __le32 ah_cid;
1906 __le32 unused_0;
1907 };
1908
1909 /* creq_destroy_ah_resp (size:128b/16B) */
1910 struct creq_destroy_ah_resp {
1911 u8 type;
1912 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL
1913 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
1914 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL
1915 #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT
1916 u8 status;
1917 __le16 cookie;
1918 __le32 xid;
1919 u8 v;
1920 #define CREQ_DESTROY_AH_RESP_V 0x1UL
1921 u8 event;
1922 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL
1923 #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH
1924 u8 reserved48[6];
1925 };
1926
1927 /* cmdq_query_roce_stats (size:192b/24B) */
1928 struct cmdq_query_roce_stats {
1929 u8 opcode;
1930 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL
1931 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS
1932 u8 cmd_size;
1933 __le16 flags;
1934 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL
1935 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL
1936 __le16 cookie;
1937 u8 resp_size;
1938 u8 collection_id;
1939 __le64 resp_addr;
1940 __le32 function_id;
1941 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL
1942 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0
1943 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL
1944 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8
1945 #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL
1946 __le32 reserved32;
1947 };
1948
1949 /* creq_query_roce_stats_resp (size:128b/16B) */
1950 struct creq_query_roce_stats_resp {
1951 u8 type;
1952 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL
1953 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0
1954 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL
1955 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT
1956 u8 status;
1957 __le16 cookie;
1958 __le32 size;
1959 u8 v;
1960 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL
1961 u8 event;
1962 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL
1963 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \
1964 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS
1965 u8 reserved48[6];
1966 };
1967
1968 /* creq_query_roce_stats_resp_sb (size:2944b/368B) */
1969 struct creq_query_roce_stats_resp_sb {
1970 u8 opcode;
1971 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL
1972 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \
1973 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS
1974 u8 status;
1975 __le16 cookie;
1976 __le16 flags;
1977 u8 resp_size;
1978 u8 rsvd;
1979 __le32 num_counters;
1980 __le32 rsvd1;
1981 __le64 to_retransmits;
1982 __le64 seq_err_naks_rcvd;
1983 __le64 max_retry_exceeded;
1984 __le64 rnr_naks_rcvd;
1985 __le64 missing_resp;
1986 __le64 unrecoverable_err;
1987 __le64 bad_resp_err;
1988 __le64 local_qp_op_err;
1989 __le64 local_protection_err;
1990 __le64 mem_mgmt_op_err;
1991 __le64 remote_invalid_req_err;
1992 __le64 remote_access_err;
1993 __le64 remote_op_err;
1994 __le64 dup_req;
1995 __le64 res_exceed_max;
1996 __le64 res_length_mismatch;
1997 __le64 res_exceeds_wqe;
1998 __le64 res_opcode_err;
1999 __le64 res_rx_invalid_rkey;
2000 __le64 res_rx_domain_err;
2001 __le64 res_rx_no_perm;
2002 __le64 res_rx_range_err;
2003 __le64 res_tx_invalid_rkey;
2004 __le64 res_tx_domain_err;
2005 __le64 res_tx_no_perm;
2006 __le64 res_tx_range_err;
2007 __le64 res_irrq_oflow;
2008 __le64 res_unsup_opcode;
2009 __le64 res_unaligned_atomic;
2010 __le64 res_rem_inv_err;
2011 __le64 res_mem_error;
2012 __le64 res_srq_err;
2013 __le64 res_cmp_err;
2014 __le64 res_invalid_dup_rkey;
2015 __le64 res_wqe_format_err;
2016 __le64 res_cq_load_err;
2017 __le64 res_srq_load_err;
2018 __le64 res_tx_pci_err;
2019 __le64 res_rx_pci_err;
2020 __le64 res_oos_drop_count;
2021 __le64 active_qp_count_p0;
2022 __le64 active_qp_count_p1;
2023 __le64 active_qp_count_p2;
2024 __le64 active_qp_count_p3;
2025 };
2026
2027 /* cmdq_query_roce_stats_ext (size:192b/24B) */
2028 struct cmdq_query_roce_stats_ext {
2029 u8 opcode;
2030 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL
2031 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \
2032 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS
2033 u8 cmd_size;
2034 __le16 flags;
2035 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL
2036 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL
2037 __le16 cookie;
2038 u8 resp_size;
2039 u8 collection_id;
2040 __le64 resp_addr;
2041 __le32 function_id;
2042 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL
2043 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0
2044 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL
2045 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8
2046 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL
2047 __le32 reserved32;
2048 };
2049
2050 /* creq_query_roce_stats_ext_resp (size:128b/16B) */
2051 struct creq_query_roce_stats_ext_resp {
2052 u8 type;
2053 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL
2054 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0
2055 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL
2056 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \
2057 CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT
2058 u8 status;
2059 __le16 cookie;
2060 __le32 size;
2061 u8 v;
2062 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL
2063 u8 event;
2064 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL
2065 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \
2066 CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT
2067 u8 reserved48[6];
2068 };
2069
2070 /* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */
2071 struct creq_query_roce_stats_ext_resp_sb {
2072 u8 opcode;
2073 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
2074 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \
2075 CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT
2076 u8 status;
2077 __le16 cookie;
2078 __le16 flags;
2079 u8 resp_size;
2080 u8 rsvd;
2081 __le64 tx_atomic_req_pkts;
2082 __le64 tx_read_req_pkts;
2083 __le64 tx_read_res_pkts;
2084 __le64 tx_write_req_pkts;
2085 __le64 tx_send_req_pkts;
2086 __le64 tx_roce_pkts;
2087 __le64 tx_roce_bytes;
2088 __le64 rx_atomic_req_pkts;
2089 __le64 rx_read_req_pkts;
2090 __le64 rx_read_res_pkts;
2091 __le64 rx_write_req_pkts;
2092 __le64 rx_send_req_pkts;
2093 __le64 rx_roce_pkts;
2094 __le64 rx_roce_bytes;
2095 __le64 rx_roce_good_pkts;
2096 __le64 rx_roce_good_bytes;
2097 __le64 rx_out_of_buffer_pkts;
2098 __le64 rx_out_of_sequence_pkts;
2099 __le64 tx_cnp_pkts;
2100 __le64 rx_cnp_pkts;
2101 __le64 rx_ecn_marked_pkts;
2102 __le64 tx_cnp_bytes;
2103 __le64 rx_cnp_bytes;
2104 __le64 seq_err_naks_rcvd;
2105 __le64 rnr_naks_rcvd;
2106 __le64 missing_resp;
2107 __le64 to_retransmit;
2108 __le64 dup_req;
2109 };
2110
2111 /* cmdq_query_func (size:128b/16B) */
2112 struct cmdq_query_func {
2113 u8 opcode;
2114 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL
2115 #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC
2116 u8 cmd_size;
2117 __le16 flags;
2118 __le16 cookie;
2119 u8 resp_size;
2120 u8 reserved8;
2121 __le64 resp_addr;
2122 };
2123
2124 /* creq_query_func_resp (size:128b/16B) */
2125 struct creq_query_func_resp {
2126 u8 type;
2127 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL
2128 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
2129 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL
2130 #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT
2131 u8 status;
2132 __le16 cookie;
2133 __le32 size;
2134 u8 v;
2135 #define CREQ_QUERY_FUNC_RESP_V 0x1UL
2136 u8 event;
2137 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL
2138 #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC
2139 u8 reserved48[6];
2140 };
2141
2142 /* creq_query_func_resp_sb (size:1088b/136B) */
2143 struct creq_query_func_resp_sb {
2144 u8 opcode;
2145 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL
2146 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC
2147 u8 status;
2148 __le16 cookie;
2149 __le16 flags;
2150 u8 resp_size;
2151 u8 reserved8;
2152 __le64 max_mr_size;
2153 __le32 max_qp;
2154 __le16 max_qp_wr;
2155 __le16 dev_cap_flags;
2156 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL
2157 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL
2158 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1
2159 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1)
2160 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1)
2161 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1)
2162 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \
2163 CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT
2164 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL
2165 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL
2166 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL
2167 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL
2168 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL
2169 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL
2170 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL
2171 __le32 max_cq;
2172 __le32 max_cqe;
2173 __le32 max_pd;
2174 u8 max_sge;
2175 u8 max_srq_sge;
2176 u8 max_qp_rd_atom;
2177 u8 max_qp_init_rd_atom;
2178 __le32 max_mr;
2179 __le32 max_mw;
2180 __le32 max_raw_eth_qp;
2181 __le32 max_ah;
2182 __le32 max_fmr;
2183 __le32 max_srq_wr;
2184 __le32 max_pkeys;
2185 __le32 max_inline_data;
2186 u8 max_map_per_fmr;
2187 u8 l2_db_space_size;
2188 __le16 max_srq;
2189 __le32 max_gid;
2190 __le32 tqm_alloc_reqs[12];
2191 __le32 max_dpi;
2192 u8 max_sge_var_wqe;
2193 u8 dev_cap_ext_flags;
2194 #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL
2195 #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL
2196 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL
2197 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL
2198 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL
2199 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL
2200 #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL
2201 #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL
2202 __le16 max_inline_data_var_wqe;
2203 __le32 start_qid;
2204 u8 max_msn_table_size;
2205 u8 reserved8_1;
2206 __le16 dev_cap_ext_flags_2;
2207 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL
2208 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL
2209 #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL
2210 #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL
2211 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL
2212 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4
2213 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4)
2214 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4)
2215 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4)
2216 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \
2217 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE
2218 __le16 max_xp_qp_size;
2219 __le16 create_qp_batch_size;
2220 __le16 destroy_qp_batch_size;
2221 __le16 reserved16;
2222 __le64 reserved64;
2223 };
2224
2225 /* cmdq_set_func_resources (size:448b/56B) */
2226 struct cmdq_set_func_resources {
2227 u8 opcode;
2228 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
2229 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\
2230 CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES
2231 u8 cmd_size;
2232 __le16 flags;
2233 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
2234 __le16 cookie;
2235 u8 resp_size;
2236 u8 reserved8;
2237 __le64 resp_addr;
2238 __le32 number_of_qp;
2239 __le32 number_of_mrw;
2240 __le32 number_of_srq;
2241 __le32 number_of_cq;
2242 __le32 max_qp_per_vf;
2243 __le32 max_mrw_per_vf;
2244 __le32 max_srq_per_vf;
2245 __le32 max_cq_per_vf;
2246 __le32 max_gid_per_vf;
2247 __le32 stat_ctx_id;
2248 };
2249
2250 /* creq_set_func_resources_resp (size:128b/16B) */
2251 struct creq_set_func_resources_resp {
2252 u8 type;
2253 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL
2254 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
2255 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL
2256 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT
2257 u8 status;
2258 __le16 cookie;
2259 __le32 reserved32;
2260 u8 v;
2261 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL
2262 u8 event;
2263 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2264 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \
2265 CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES
2266 u8 reserved48[6];
2267 };
2268
2269 /* cmdq_read_context (size:192b/24B) */
2270 struct cmdq_read_context {
2271 u8 opcode;
2272 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL
2273 #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT
2274 u8 cmd_size;
2275 __le16 flags;
2276 __le16 cookie;
2277 u8 resp_size;
2278 u8 reserved8;
2279 __le64 resp_addr;
2280 __le32 xid;
2281 u8 type;
2282 #define CMDQ_READ_CONTEXT_TYPE_QPC 0x0UL
2283 #define CMDQ_READ_CONTEXT_TYPE_CQ 0x1UL
2284 #define CMDQ_READ_CONTEXT_TYPE_MRW 0x2UL
2285 #define CMDQ_READ_CONTEXT_TYPE_SRQ 0x3UL
2286 #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ
2287 u8 unused_0[3];
2288 };
2289
2290 /* creq_read_context (size:128b/16B) */
2291 struct creq_read_context {
2292 u8 type;
2293 #define CREQ_READ_CONTEXT_TYPE_MASK 0x3fUL
2294 #define CREQ_READ_CONTEXT_TYPE_SFT 0
2295 #define CREQ_READ_CONTEXT_TYPE_QP_EVENT 0x38UL
2296 #define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT
2297 u8 status;
2298 __le16 cookie;
2299 __le32 reserved32;
2300 u8 v;
2301 #define CREQ_READ_CONTEXT_V 0x1UL
2302 u8 event;
2303 #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 0x85UL
2304 #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT
2305 __le16 reserved16;
2306 __le32 reserved_32;
2307 };
2308
2309 /* cmdq_map_tc_to_cos (size:192b/24B) */
2310 struct cmdq_map_tc_to_cos {
2311 u8 opcode;
2312 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL
2313 #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS
2314 u8 cmd_size;
2315 __le16 flags;
2316 __le16 cookie;
2317 u8 resp_size;
2318 u8 reserved8;
2319 __le64 resp_addr;
2320 __le16 cos0;
2321 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL
2322 #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE
2323 __le16 cos1;
2324 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL
2325 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL
2326 #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE
2327 __le32 unused_0;
2328 };
2329
2330 /* creq_map_tc_to_cos_resp (size:128b/16B) */
2331 struct creq_map_tc_to_cos_resp {
2332 u8 type;
2333 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL
2334 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
2335 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL
2336 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT
2337 u8 status;
2338 __le16 cookie;
2339 __le32 reserved32;
2340 u8 v;
2341 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL
2342 u8 event;
2343 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL
2344 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS
2345 u8 reserved48[6];
2346 };
2347
2348 /* cmdq_query_roce_cc (size:128b/16B) */
2349 struct cmdq_query_roce_cc {
2350 u8 opcode;
2351 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL
2352 #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC
2353 u8 cmd_size;
2354 __le16 flags;
2355 __le16 cookie;
2356 u8 resp_size;
2357 u8 reserved8;
2358 __le64 resp_addr;
2359 };
2360
2361 /* creq_query_roce_cc_resp (size:128b/16B) */
2362 struct creq_query_roce_cc_resp {
2363 u8 type;
2364 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2365 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
2366 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2367 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT
2368 u8 status;
2369 __le16 cookie;
2370 __le32 size;
2371 u8 v;
2372 #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL
2373 u8 event;
2374 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL
2375 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC
2376 u8 reserved48[6];
2377 };
2378
2379 /* creq_query_roce_cc_resp_sb (size:256b/32B) */
2380 struct creq_query_roce_cc_resp_sb {
2381 u8 opcode;
2382 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL
2383 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \
2384 CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC
2385 u8 status;
2386 __le16 cookie;
2387 __le16 flags;
2388 u8 resp_size;
2389 u8 reserved8;
2390 u8 enable_cc;
2391 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL
2392 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL
2393 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1
2394 u8 tos_dscp_tos_ecn;
2395 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL
2396 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
2397 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL
2398 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2
2399 u8 g;
2400 u8 num_phases_per_state;
2401 __le16 init_cr;
2402 __le16 init_tr;
2403 u8 alt_vlan_pcp;
2404 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL
2405 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
2406 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL
2407 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3
2408 u8 alt_tos_dscp;
2409 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL
2410 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
2411 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL
2412 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6
2413 u8 cc_mode;
2414 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL
2415 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL
2416 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \
2417 CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC
2418 u8 tx_queue;
2419 __le16 rtt;
2420 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL
2421 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
2422 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL
2423 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14
2424 __le16 tcp_cp;
2425 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL
2426 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
2427 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL
2428 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10
2429 __le16 inactivity_th;
2430 u8 pkts_per_phase;
2431 u8 time_per_phase;
2432 __le32 reserved32;
2433 };
2434
2435 /* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */
2436 struct creq_query_roce_cc_resp_sb_tlv {
2437 __le16 cmd_discr;
2438 u8 reserved_8b;
2439 u8 tlv_flags;
2440 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2441 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2442 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2443 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2444 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2445 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2446 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
2447 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2448 __le16 tlv_type;
2449 __le16 length;
2450 u8 total_size;
2451 u8 reserved56[7];
2452 u8 opcode;
2453 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL
2454 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \
2455 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC
2456 u8 status;
2457 __le16 cookie;
2458 __le16 flags;
2459 u8 resp_size;
2460 u8 reserved8;
2461 u8 enable_cc;
2462 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL
2463 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL
2464 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1
2465 u8 tos_dscp_tos_ecn;
2466 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL
2467 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0
2468 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL
2469 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2
2470 u8 g;
2471 u8 num_phases_per_state;
2472 __le16 init_cr;
2473 __le16 init_tr;
2474 u8 alt_vlan_pcp;
2475 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL
2476 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0
2477 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL
2478 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3
2479 u8 alt_tos_dscp;
2480 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2481 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0
2482 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL
2483 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6
2484 u8 cc_mode;
2485 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL
2486 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL
2487 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\
2488 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC
2489 u8 tx_queue;
2490 __le16 rtt;
2491 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL
2492 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0
2493 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL
2494 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14
2495 __le16 tcp_cp;
2496 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL
2497 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0
2498 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL
2499 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10
2500 __le16 inactivity_th;
2501 u8 pkts_per_phase;
2502 u8 time_per_phase;
2503 __le32 reserved32;
2504 };
2505
2506 /* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */
2507 struct creq_query_roce_cc_gen1_resp_sb_tlv {
2508 __le16 cmd_discr;
2509 u8 reserved_8b;
2510 u8 tlv_flags;
2511 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2512 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2513 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2514 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2515 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2516 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2517 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
2518 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2519 __le16 tlv_type;
2520 __le16 length;
2521 __le64 reserved64;
2522 __le16 inactivity_th_hi;
2523 __le16 min_time_between_cnps;
2524 __le16 init_cp;
2525 u8 tr_update_mode;
2526 u8 tr_update_cycles;
2527 u8 fr_num_rtts;
2528 u8 ai_rate_increase;
2529 __le16 reduction_relax_rtts_th;
2530 __le16 additional_relax_cr_th;
2531 __le16 cr_min_th;
2532 u8 bw_avg_weight;
2533 u8 actual_cr_factor;
2534 __le16 max_cp_cr_th;
2535 u8 cp_bias_en;
2536 u8 cp_bias;
2537 u8 cnp_ecn;
2538 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL
2539 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL
2540 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL
2541 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \
2542 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0
2543 u8 rtt_jitter_en;
2544 __le16 link_bytes_per_usec;
2545 __le16 reset_cc_cr_th;
2546 u8 cr_width;
2547 u8 quota_period_min;
2548 u8 quota_period_max;
2549 u8 quota_period_abs_max;
2550 __le16 tr_lower_bound;
2551 u8 cr_prob_factor;
2552 u8 tr_prob_factor;
2553 __le16 fairness_cr_th;
2554 u8 red_div;
2555 u8 cnp_ratio_th;
2556 __le16 exp_ai_rtts;
2557 u8 exp_ai_cr_cp_ratio;
2558 u8 use_rate_table;
2559 __le16 cp_exp_update_th;
2560 __le16 high_exp_ai_rtts_th1;
2561 __le16 high_exp_ai_rtts_th2;
2562 __le16 actual_cr_cong_free_rtts_th;
2563 __le16 severe_cong_cr_th1;
2564 __le16 severe_cong_cr_th2;
2565 __le32 link64B_per_rtt;
2566 u8 cc_ack_bytes;
2567 u8 reduce_init_en;
2568 __le16 reduce_init_cong_free_rtts_th;
2569 u8 random_no_red_en;
2570 u8 actual_cr_shift_correction_en;
2571 u8 quota_period_adjust_en;
2572 u8 reserved[5];
2573 };
2574
2575 /* cmdq_modify_roce_cc (size:448b/56B) */
2576 struct cmdq_modify_roce_cc {
2577 u8 opcode;
2578 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL
2579 #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC
2580 u8 cmd_size;
2581 __le16 flags;
2582 __le16 cookie;
2583 u8 resp_size;
2584 u8 reserved8;
2585 __le64 resp_addr;
2586 __le32 modify_mask;
2587 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL
2588 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL
2589 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2590 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL
2591 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL
2592 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL
2593 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL
2594 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2595 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2596 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL
2597 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL
2598 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL
2599 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL
2600 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2601 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2602 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2603 u8 enable_cc;
2604 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL
2605 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL
2606 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1
2607 u8 g;
2608 u8 num_phases_per_state;
2609 u8 pkts_per_phase;
2610 __le16 init_cr;
2611 __le16 init_tr;
2612 u8 tos_dscp_tos_ecn;
2613 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL
2614 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
2615 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL
2616 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2
2617 u8 alt_vlan_pcp;
2618 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL
2619 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
2620 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL
2621 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3
2622 __le16 alt_tos_dscp;
2623 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL
2624 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
2625 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL
2626 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6
2627 __le16 rtt;
2628 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL
2629 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
2630 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL
2631 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14
2632 __le16 tcp_cp;
2633 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL
2634 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
2635 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL
2636 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10
2637 u8 cc_mode;
2638 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL
2639 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2640 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE
2641 u8 tx_queue;
2642 __le16 inactivity_th;
2643 u8 time_per_phase;
2644 u8 reserved8_1;
2645 __le16 reserved16;
2646 __le32 reserved32;
2647 __le64 reserved64;
2648 };
2649
2650 /* cmdq_modify_roce_cc_tlv (size:640b/80B) */
2651 struct cmdq_modify_roce_cc_tlv {
2652 __le16 cmd_discr;
2653 u8 reserved_8b;
2654 u8 tlv_flags;
2655 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL
2656 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2657 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2658 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL
2659 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2660 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2661 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \
2662 CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES
2663 __le16 tlv_type;
2664 __le16 length;
2665 u8 total_size;
2666 u8 reserved56[7];
2667 u8 opcode;
2668 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL
2669 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC
2670 u8 cmd_size;
2671 __le16 flags;
2672 __le16 cookie;
2673 u8 resp_size;
2674 u8 reserved8;
2675 __le64 resp_addr;
2676 __le32 modify_mask;
2677 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL
2678 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL
2679 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2680 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL
2681 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL
2682 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL
2683 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL
2684 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2685 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2686 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL
2687 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL
2688 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL
2689 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL
2690 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2691 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2692 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2693 u8 enable_cc;
2694 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL
2695 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL
2696 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1
2697 u8 g;
2698 u8 num_phases_per_state;
2699 u8 pkts_per_phase;
2700 __le16 init_cr;
2701 __le16 init_tr;
2702 u8 tos_dscp_tos_ecn;
2703 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL
2704 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0
2705 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL
2706 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2
2707 u8 alt_vlan_pcp;
2708 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL
2709 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0
2710 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL
2711 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3
2712 __le16 alt_tos_dscp;
2713 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2714 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0
2715 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL
2716 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6
2717 __le16 rtt;
2718 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL
2719 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0
2720 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL
2721 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14
2722 __le16 tcp_cp;
2723 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL
2724 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0
2725 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL
2726 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10
2727 u8 cc_mode;
2728 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL
2729 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2730 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\
2731 CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE
2732 u8 tx_queue;
2733 __le16 inactivity_th;
2734 u8 time_per_phase;
2735 u8 reserved8_1;
2736 __le16 reserved16;
2737 __le32 reserved32;
2738 __le64 reserved64;
2739 __le64 reservedtlvpad;
2740 };
2741
2742 /* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */
2743 struct cmdq_modify_roce_cc_gen1_tlv {
2744 __le16 cmd_discr;
2745 u8 reserved_8b;
2746 u8 tlv_flags;
2747 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL
2748 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2749 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2750 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL
2751 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2752 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2753 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\
2754 CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES
2755 __le16 tlv_type;
2756 __le16 length;
2757 __le64 reserved64;
2758 __le64 modify_mask;
2759 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL
2760 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL
2761 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL
2762 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL
2763 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL
2764 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL
2765 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL
2766 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL
2767 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL
2768 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL
2769 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL
2770 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL
2771 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL
2772 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL
2773 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL
2774 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL
2775 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL
2776 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL
2777 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL
2778 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL
2779 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL
2780 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL
2781 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL
2782 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL
2783 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL
2784 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL
2785 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL
2786 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL
2787 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL
2788 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL
2789 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL
2790 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL
2791 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL
2792 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL
2793 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL
2794 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL
2795 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL
2796 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL
2797 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL
2798 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL
2799 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \
2800 0x10000000000ULL
2801 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL
2802 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \
2803 0x40000000000ULL
2804 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL
2805 __le16 inactivity_th_hi;
2806 __le16 min_time_between_cnps;
2807 __le16 init_cp;
2808 u8 tr_update_mode;
2809 u8 tr_update_cycles;
2810 u8 fr_num_rtts;
2811 u8 ai_rate_increase;
2812 __le16 reduction_relax_rtts_th;
2813 __le16 additional_relax_cr_th;
2814 __le16 cr_min_th;
2815 u8 bw_avg_weight;
2816 u8 actual_cr_factor;
2817 __le16 max_cp_cr_th;
2818 u8 cp_bias_en;
2819 u8 cp_bias;
2820 u8 cnp_ecn;
2821 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL
2822 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL
2823 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL
2824 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0
2825 u8 rtt_jitter_en;
2826 __le16 link_bytes_per_usec;
2827 __le16 reset_cc_cr_th;
2828 u8 cr_width;
2829 u8 quota_period_min;
2830 u8 quota_period_max;
2831 u8 quota_period_abs_max;
2832 __le16 tr_lower_bound;
2833 u8 cr_prob_factor;
2834 u8 tr_prob_factor;
2835 __le16 fairness_cr_th;
2836 u8 red_div;
2837 u8 cnp_ratio_th;
2838 __le16 exp_ai_rtts;
2839 u8 exp_ai_cr_cp_ratio;
2840 u8 use_rate_table;
2841 __le16 cp_exp_update_th;
2842 __le16 high_exp_ai_rtts_th1;
2843 __le16 high_exp_ai_rtts_th2;
2844 __le16 actual_cr_cong_free_rtts_th;
2845 __le16 severe_cong_cr_th1;
2846 __le16 severe_cong_cr_th2;
2847 __le32 link64B_per_rtt;
2848 u8 cc_ack_bytes;
2849 u8 reduce_init_en;
2850 __le16 reduce_init_cong_free_rtts_th;
2851 u8 random_no_red_en;
2852 u8 actual_cr_shift_correction_en;
2853 u8 quota_period_adjust_en;
2854 u8 reserved[5];
2855 };
2856
2857 /* creq_modify_roce_cc_resp (size:128b/16B) */
2858 struct creq_modify_roce_cc_resp {
2859 u8 type;
2860 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2861 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
2862 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2863 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT
2864 u8 status;
2865 __le16 cookie;
2866 __le32 reserved32;
2867 u8 v;
2868 #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL
2869 u8 event;
2870 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL
2871 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC
2872 u8 reserved48[6];
2873 };
2874
2875 /* cmdq_set_link_aggr_mode_cc (size:320b/40B) */
2876 struct cmdq_set_link_aggr_mode_cc {
2877 u8 opcode;
2878 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
2879 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \
2880 CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE
2881 u8 cmd_size;
2882 __le16 flags;
2883 __le16 cookie;
2884 u8 resp_size;
2885 u8 reserved8;
2886 __le64 resp_addr;
2887 __le32 modify_mask;
2888 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL
2889 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL
2890 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL
2891 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL
2892 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL
2893 u8 aggr_enable;
2894 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL
2895 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL
2896 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1
2897 u8 active_port_map;
2898 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL
2899 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0
2900 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL
2901 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4
2902 u8 member_port_map;
2903 u8 link_aggr_mode;
2904 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL
2905 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL
2906 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL
2907 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL
2908 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD
2909 __le16 stat_ctx_id[4];
2910 __le64 rsvd1;
2911 };
2912
2913 /* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */
2914 struct creq_set_link_aggr_mode_resources_resp {
2915 u8 type;
2916 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL
2917 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0
2918 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL
2919 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT
2920 u8 status;
2921 __le16 cookie;
2922 __le32 reserved32;
2923 u8 v;
2924 #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL
2925 u8 event;
2926 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL
2927 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\
2928 CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE
2929 u8 reserved48[6];
2930 };
2931
2932 /* creq_func_event (size:128b/16B) */
2933 struct creq_func_event {
2934 u8 type;
2935 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL
2936 #define CREQ_FUNC_EVENT_TYPE_SFT 0
2937 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL
2938 #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT
2939 u8 reserved56[7];
2940 u8 v;
2941 #define CREQ_FUNC_EVENT_V 0x1UL
2942 u8 event;
2943 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL
2944 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL
2945 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL
2946 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL
2947 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL
2948 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL
2949 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL
2950 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL
2951 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL
2952 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL
2953 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL
2954 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL
2955 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL
2956 #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED
2957 u8 reserved48[6];
2958 };
2959
2960 /* creq_qp_event (size:128b/16B) */
2961 struct creq_qp_event {
2962 u8 type;
2963 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL
2964 #define CREQ_QP_EVENT_TYPE_SFT 0
2965 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL
2966 #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT
2967 u8 status;
2968 #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL
2969 #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL
2970 #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL
2971 #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL
2972 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL
2973 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL
2974 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL
2975 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL
2976 #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR
2977 __le16 cookie;
2978 __le32 reserved32;
2979 u8 v;
2980 #define CREQ_QP_EVENT_V 0x1UL
2981 u8 event;
2982 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL
2983 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL
2984 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL
2985 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL
2986 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL
2987 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL
2988 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL
2989 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL
2990 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL
2991 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL
2992 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL
2993 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL
2994 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL
2995 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL
2996 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL
2997 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL
2998 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL
2999 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL
3000 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL
3001 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL
3002 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL
3003 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL
3004 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL
3005 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL
3006 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL
3007 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL
3008 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL
3009 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL
3010 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL
3011 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL
3012 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL
3013 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL
3014 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL
3015 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL
3016 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL
3017 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3018 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3019 #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION
3020 u8 reserved48[6];
3021 };
3022
3023 /* creq_qp_error_notification (size:128b/16B) */
3024 struct creq_qp_error_notification {
3025 u8 type;
3026 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3027 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
3028 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL
3029 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT
3030 u8 status;
3031 u8 req_slow_path_state;
3032 u8 req_err_state_reason;
3033 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0X0UL
3034 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0X1UL
3035 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0X2UL
3036 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0X3UL
3037 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0X4UL
3038 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0X5UL
3039 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0X6UL
3040 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0X7UL
3041 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0X8UL
3042 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0X9UL
3043 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0XAUL
3044 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0XBUL
3045 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0XCUL
3046 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0XDUL
3047 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0XEUL
3048 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0XFUL
3049 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0X10UL
3050 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0X11UL
3051 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0X12UL
3052 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0X13UL
3053 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0X14UL
3054 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0X15UL
3055 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0X16UL
3056 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0X17UL
3057 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0X18UL
3058 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0X19UL
3059 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0X1AUL
3060 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0X1BUL
3061 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0X1CUL
3062 __le32 xid;
3063 u8 v;
3064 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL
3065 u8 event;
3066 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3067 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \
3068 CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION
3069 u8 res_slow_path_state;
3070 u8 res_err_state_reason;
3071 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL
3072 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL
3073 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL
3074 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL
3075 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL
3076 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL
3077 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL
3078 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL
3079 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL
3080 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL
3081 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL
3082 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL
3083 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL
3084 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL
3085 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL
3086 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL
3087 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL
3088 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL
3089 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL
3090 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL
3091 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL
3092 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL
3093 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL
3094 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL
3095 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL
3096 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL
3097 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL
3098 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL
3099 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL
3100 __le16 sq_cons_idx;
3101 __le16 rq_cons_idx;
3102 };
3103
3104 /* creq_cq_error_notification (size:128b/16B) */
3105 struct creq_cq_error_notification {
3106 u8 type;
3107 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3108 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0
3109 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL
3110 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT
3111 u8 status;
3112 u8 cq_err_reason;
3113 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL
3114 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL
3115 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL
3116 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL
3117 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL
3118 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL
3119 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \
3120 CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR
3121 u8 reserved8;
3122 __le32 xid;
3123 u8 v;
3124 #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL
3125 u8 event;
3126 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3127 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \
3128 CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION
3129 u8 reserved48[6];
3130 };
3131
3132 /* sq_base (size:64b/8B) */
3133 struct sq_base {
3134 u8 wqe_type;
3135 #define SQ_BASE_WQE_TYPE_SEND 0x0UL
3136 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3137 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL
3138 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL
3139 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3140 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL
3141 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL
3142 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL
3143 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL
3144 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL
3145 #define SQ_BASE_WQE_TYPE_BIND 0xeUL
3146 #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL
3147 #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR
3148 u8 unused_0[7];
3149 };
3150
3151 /* sq_sge (size:128b/16B) */
3152 struct sq_sge {
3153 __le64 va_or_pa;
3154 __le32 l_key;
3155 __le32 size;
3156 };
3157
3158 /* sq_psn_search (size:64b/8B) */
3159 struct sq_psn_search {
3160 __le32 opcode_start_psn;
3161 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL
3162 #define SQ_PSN_SEARCH_START_PSN_SFT 0
3163 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL
3164 #define SQ_PSN_SEARCH_OPCODE_SFT 24
3165 __le32 flags_next_psn;
3166 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL
3167 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
3168 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL
3169 #define SQ_PSN_SEARCH_FLAGS_SFT 24
3170 };
3171
3172 /* sq_psn_search_ext (size:128b/16B) */
3173 struct sq_psn_search_ext {
3174 __le32 opcode_start_psn;
3175 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL
3176 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
3177 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL
3178 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24
3179 __le32 flags_next_psn;
3180 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL
3181 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
3182 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL
3183 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24
3184 __le16 start_slot_idx;
3185 __le16 reserved16;
3186 __le32 reserved32;
3187 };
3188
3189 /* sq_msn_search (size:64b/8B) */
3190 struct sq_msn_search {
3191 __le64 start_idx_next_psn_start_psn;
3192 #define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL
3193 #define SQ_MSN_SEARCH_START_PSN_SFT 0
3194 #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL
3195 #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24
3196 #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL
3197 #define SQ_MSN_SEARCH_START_IDX_SFT 48
3198 };
3199
3200 /* sq_send (size:1024b/128B) */
3201 struct sq_send {
3202 u8 wqe_type;
3203 #define SQ_SEND_WQE_TYPE_SEND 0x0UL
3204 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3205 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL
3206 #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID
3207 u8 flags;
3208 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3209 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3210 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL
3211 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3212 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL
3213 #define SQ_SEND_FLAGS_SE 0x8UL
3214 #define SQ_SEND_FLAGS_INLINE 0x10UL
3215 #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL
3216 #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL
3217 u8 wqe_size;
3218 u8 reserved8_1;
3219 __le32 inv_key_or_imm_data;
3220 __le32 length;
3221 __le32 q_key;
3222 __le32 dst_qp;
3223 #define SQ_SEND_DST_QP_MASK 0xffffffUL
3224 #define SQ_SEND_DST_QP_SFT 0
3225 __le32 avid;
3226 #define SQ_SEND_AVID_MASK 0xfffffUL
3227 #define SQ_SEND_AVID_SFT 0
3228 __le32 reserved32;
3229 __le32 timestamp;
3230 #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL
3231 #define SQ_SEND_TIMESTAMP_SFT 0
3232 __le32 data[24];
3233 };
3234
3235 /* sq_send_hdr (size:256b/32B) */
3236 struct sq_send_hdr {
3237 u8 wqe_type;
3238 #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL
3239 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3240 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL
3241 #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID
3242 u8 flags;
3243 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3244 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3245 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3246 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3247 #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL
3248 #define SQ_SEND_HDR_FLAGS_SE 0x8UL
3249 #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL
3250 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL
3251 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3252 u8 wqe_size;
3253 u8 reserved8_1;
3254 __le32 inv_key_or_imm_data;
3255 __le32 length;
3256 __le32 q_key;
3257 __le32 dst_qp;
3258 #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL
3259 #define SQ_SEND_HDR_DST_QP_SFT 0
3260 __le32 avid;
3261 #define SQ_SEND_HDR_AVID_MASK 0xfffffUL
3262 #define SQ_SEND_HDR_AVID_SFT 0
3263 __le32 reserved32;
3264 __le32 timestamp;
3265 #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL
3266 #define SQ_SEND_HDR_TIMESTAMP_SFT 0
3267 };
3268
3269 /* sq_send_raweth_qp1 (size:1024b/128B) */
3270 struct sq_send_raweth_qp1 {
3271 u8 wqe_type;
3272 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL
3273 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND
3274 u8 flags;
3275 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \
3276 0xffUL
3277 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \
3278 0
3279 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL
3280 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3281 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL
3282 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL
3283 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL
3284 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL
3285 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL
3286 u8 wqe_size;
3287 u8 reserved8;
3288 __le16 lflags;
3289 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3290 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL
3291 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL
3292 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL
3293 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL
3294 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL
3295 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL
3296 __le16 cfa_action;
3297 __le32 length;
3298 __le32 reserved32_1;
3299 __le32 cfa_meta;
3300 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL
3301 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
3302 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL
3303 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL
3304 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13
3305 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL
3306 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16
3307 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
3308 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
3309 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
3310 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
3311 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
3312 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
3313 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\
3314 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
3315 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
3316 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19
3317 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL
3318 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28
3319 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28)
3320 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
3321 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
3322 __le32 reserved32_2;
3323 __le32 reserved32_3;
3324 __le32 timestamp;
3325 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL
3326 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0
3327 __le32 data[24];
3328 };
3329
3330 /* sq_send_raweth_qp1_hdr (size:256b/32B) */
3331 struct sq_send_raweth_qp1_hdr {
3332 u8 wqe_type;
3333 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL
3334 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND
3335 u8 flags;
3336 #define \
3337 SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3338 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3339 0
3340 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL
3341 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3342 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL
3343 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL
3344 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL
3345 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL
3346 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL
3347 u8 wqe_size;
3348 u8 reserved8;
3349 __le16 lflags;
3350 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3351 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL
3352 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL
3353 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL
3354 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL
3355 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL
3356 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL
3357 __le16 cfa_action;
3358 __le32 length;
3359 __le32 reserved32_1;
3360 __le32 cfa_meta;
3361 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL
3362 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0
3363 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL
3364 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL
3365 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13
3366 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL
3367 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16
3368 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
3369 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
3370 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
3371 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
3372 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
3373 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
3374 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\
3375 SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG
3376 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
3377 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19
3378 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL
3379 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28
3380 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28)
3381 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
3382 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\
3383 SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG
3384 __le32 reserved32_2;
3385 __le32 reserved32_3;
3386 __le32 timestamp;
3387 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL
3388 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0
3389 };
3390
3391 /* sq_rdma (size:1024b/128B) */
3392 struct sq_rdma {
3393 u8 wqe_type;
3394 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL
3395 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3396 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL
3397 #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE
3398 u8 flags;
3399 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3400 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3401 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL
3402 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3403 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL
3404 #define SQ_RDMA_FLAGS_SE 0x8UL
3405 #define SQ_RDMA_FLAGS_INLINE 0x10UL
3406 #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL
3407 #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL
3408 u8 wqe_size;
3409 u8 reserved8;
3410 __le32 imm_data;
3411 __le32 length;
3412 __le32 reserved32_1;
3413 __le64 remote_va;
3414 __le32 remote_key;
3415 __le32 timestamp;
3416 #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL
3417 #define SQ_RDMA_TIMESTAMP_SFT 0
3418 __le32 data[24];
3419 };
3420
3421 /* sq_rdma_hdr (size:256b/32B) */
3422 struct sq_rdma_hdr {
3423 u8 wqe_type;
3424 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL
3425 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3426 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL
3427 #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE
3428 u8 flags;
3429 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3430 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3431 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL
3432 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3433 #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL
3434 #define SQ_RDMA_HDR_FLAGS_SE 0x8UL
3435 #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL
3436 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL
3437 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL
3438 u8 wqe_size;
3439 u8 reserved8;
3440 __le32 imm_data;
3441 __le32 length;
3442 __le32 reserved32_1;
3443 __le64 remote_va;
3444 __le32 remote_key;
3445 __le32 timestamp;
3446 #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL
3447 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0
3448 };
3449
3450 /* sq_atomic (size:1024b/128B) */
3451 struct sq_atomic {
3452 u8 wqe_type;
3453 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL
3454 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL
3455 #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA
3456 u8 flags;
3457 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3458 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3459 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL
3460 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3461 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL
3462 #define SQ_ATOMIC_FLAGS_SE 0x8UL
3463 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL
3464 #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL
3465 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL
3466 __le16 reserved16;
3467 __le32 remote_key;
3468 __le64 remote_va;
3469 __le64 swap_data;
3470 __le64 cmp_data;
3471 __le32 data[24];
3472 };
3473
3474 /* sq_atomic_hdr (size:256b/32B) */
3475 struct sq_atomic_hdr {
3476 u8 wqe_type;
3477 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL
3478 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL
3479 #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA
3480 u8 flags;
3481 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3482 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3483 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL
3484 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3485 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL
3486 #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL
3487 #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL
3488 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL
3489 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL
3490 __le16 reserved16;
3491 __le32 remote_key;
3492 __le64 remote_va;
3493 __le64 swap_data;
3494 __le64 cmp_data;
3495 };
3496
3497 /* sq_localinvalidate (size:1024b/128B) */
3498 struct sq_localinvalidate {
3499 u8 wqe_type;
3500 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL
3501 #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID
3502 u8 flags;
3503 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\
3504 0xffUL
3505 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3506 0
3507 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL
3508 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3509 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL
3510 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL
3511 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL
3512 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL
3513 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL
3514 __le16 reserved16;
3515 __le32 inv_l_key;
3516 __le64 reserved64;
3517 u8 reserved128[16];
3518 __le32 data[24];
3519 };
3520
3521 /* sq_localinvalidate_hdr (size:256b/32B) */
3522 struct sq_localinvalidate_hdr {
3523 u8 wqe_type;
3524 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL
3525 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID
3526 u8 flags;
3527 #define \
3528 SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3529 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3530 0
3531 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL
3532 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3533 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL
3534 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL
3535 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL
3536 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL
3537 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL
3538 __le16 reserved16;
3539 __le32 inv_l_key;
3540 __le64 reserved64;
3541 u8 reserved128[16];
3542 };
3543
3544 /* sq_fr_pmr (size:1024b/128B) */
3545 struct sq_fr_pmr {
3546 u8 wqe_type;
3547 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL
3548 #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR
3549 u8 flags;
3550 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL
3551 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3552 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL
3553 #define SQ_FR_PMR_FLAGS_SE 0x8UL
3554 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL
3555 #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL
3556 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL
3557 u8 access_cntl;
3558 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3559 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL
3560 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3561 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3562 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3563 u8 zero_based_page_size_log;
3564 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL
3565 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
3566 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3567 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3568 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3569 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3570 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3571 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3572 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3573 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3574 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3575 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3576 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3577 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3578 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3579 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3580 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3581 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3582 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3583 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3584 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3585 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3586 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3587 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3588 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3589 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3590 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3591 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3592 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3593 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3594 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3595 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3596 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3597 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3598 #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T
3599 #define SQ_FR_PMR_ZERO_BASED 0x20UL
3600 __le32 l_key;
3601 u8 length[5];
3602 u8 reserved8_1;
3603 u8 reserved8_2;
3604 u8 numlevels_pbl_page_size_log;
3605 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
3606 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
3607 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3608 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3609 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3610 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3611 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3612 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3613 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3614 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3615 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3616 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3617 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3618 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3619 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3620 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3621 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3622 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3623 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3624 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3625 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3626 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3627 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3628 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3629 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3630 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3631 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3632 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3633 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3634 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3635 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3636 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3637 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3638 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3639 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T
3640 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL
3641 #define SQ_FR_PMR_NUMLEVELS_SFT 6
3642 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6)
3643 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6)
3644 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6)
3645 #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2
3646 __le64 pblptr;
3647 __le64 va;
3648 __le32 data[24];
3649 };
3650
3651 /* sq_fr_pmr_hdr (size:256b/32B) */
3652 struct sq_fr_pmr_hdr {
3653 u8 wqe_type;
3654 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL
3655 #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR
3656 u8 flags;
3657 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL
3658 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3659 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL
3660 #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL
3661 #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL
3662 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL
3663 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL
3664 u8 access_cntl;
3665 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3666 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
3667 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3668 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3669 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3670 u8 zero_based_page_size_log;
3671 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL
3672 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0
3673 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3674 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3675 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3676 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3677 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3678 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3679 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3680 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3681 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3682 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3683 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3684 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3685 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3686 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3687 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3688 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3689 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3690 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3691 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3692 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3693 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3694 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3695 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3696 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3697 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3698 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3699 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3700 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3701 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3702 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3703 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3704 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3705 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T
3706 #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL
3707 __le32 l_key;
3708 u8 length[5];
3709 u8 reserved8_1;
3710 u8 reserved8_2;
3711 u8 numlevels_pbl_page_size_log;
3712 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
3713 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0
3714 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3715 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3716 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3717 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3718 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3719 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3720 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3721 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3722 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3723 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3724 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3725 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3726 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3727 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3728 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3729 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3730 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3731 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3732 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3733 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3734 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3735 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3736 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3737 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3738 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3739 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3740 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3741 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3742 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3743 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3744 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3745 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3746 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T
3747 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL
3748 #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6
3749 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6)
3750 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6)
3751 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6)
3752 #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2
3753 __le64 pblptr;
3754 __le64 va;
3755 };
3756
3757 /* sq_bind (size:1024b/128B) */
3758 struct sq_bind {
3759 u8 wqe_type;
3760 #define SQ_BIND_WQE_TYPE_BIND 0xeUL
3761 #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND
3762 u8 flags;
3763 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3764 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3765 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL
3766 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3767 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL
3768 #define SQ_BIND_FLAGS_SE 0x8UL
3769 #define SQ_BIND_FLAGS_INLINE 0x10UL
3770 #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL
3771 #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL
3772 u8 access_cntl;
3773 #define \
3774 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\
3775 0xffUL
3776 #define \
3777 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
3778 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3779 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL
3780 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3781 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3782 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL
3783 u8 reserved8_1;
3784 u8 mw_type_zero_based;
3785 #define SQ_BIND_ZERO_BASED 0x1UL
3786 #define SQ_BIND_MW_TYPE 0x2UL
3787 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1)
3788 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1)
3789 #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2
3790 u8 reserved8_2;
3791 __le16 reserved16;
3792 __le32 parent_l_key;
3793 __le32 l_key;
3794 __le64 va;
3795 u8 length[5];
3796 u8 reserved24[3];
3797 __le32 data[24];
3798 };
3799
3800 /* sq_bind_hdr (size:256b/32B) */
3801 struct sq_bind_hdr {
3802 u8 wqe_type;
3803 #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL
3804 #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND
3805 u8 flags;
3806 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3807 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3808 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3809 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3810 #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL
3811 #define SQ_BIND_HDR_FLAGS_SE 0x8UL
3812 #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL
3813 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL
3814 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3815 u8 access_cntl;
3816 #define \
3817 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\
3818 0xffUL
3819 #define \
3820 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \
3821 0
3822 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3823 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
3824 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3825 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3826 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3827 u8 reserved8_1;
3828 u8 mw_type_zero_based;
3829 #define SQ_BIND_HDR_ZERO_BASED 0x1UL
3830 #define SQ_BIND_HDR_MW_TYPE 0x2UL
3831 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1)
3832 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1)
3833 #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2
3834 u8 reserved8_2;
3835 __le16 reserved16;
3836 __le32 parent_l_key;
3837 __le32 l_key;
3838 __le64 va;
3839 u8 length[5];
3840 u8 reserved24[3];
3841 };
3842
3843 /* rq_wqe (size:1024b/128B) */
3844 struct rq_wqe {
3845 u8 wqe_type;
3846 #define RQ_WQE_WQE_TYPE_RCV 0x80UL
3847 #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV
3848 u8 flags;
3849 u8 wqe_size;
3850 u8 reserved8;
3851 __le32 reserved32;
3852 __le32 wr_id[2];
3853 #define RQ_WQE_WR_ID_MASK 0xfffffUL
3854 #define RQ_WQE_WR_ID_SFT 0
3855 u8 reserved128[16];
3856 __le32 data[24];
3857 };
3858
3859 /* rq_wqe_hdr (size:256b/32B) */
3860 struct rq_wqe_hdr {
3861 u8 wqe_type;
3862 #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL
3863 #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV
3864 u8 flags;
3865 u8 wqe_size;
3866 u8 reserved8;
3867 __le32 reserved32;
3868 __le32 wr_id[2];
3869 #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL
3870 #define RQ_WQE_HDR_WR_ID_SFT 0
3871 u8 reserved128[16];
3872 };
3873
3874 /* cq_base (size:256b/32B) */
3875 struct cq_base {
3876 __le64 reserved64_1;
3877 __le64 reserved64_2;
3878 __le64 reserved64_3;
3879 u8 cqe_type_toggle;
3880 #define CQ_BASE_TOGGLE 0x1UL
3881 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL
3882 #define CQ_BASE_CQE_TYPE_SFT 1
3883 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1)
3884 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1)
3885 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1)
3886 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
3887 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
3888 #define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1)
3889 #define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1)
3890 #define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1)
3891 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1)
3892 #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1)
3893 #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1)
3894 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1)
3895 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1)
3896 #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF
3897 u8 status;
3898 #define CQ_BASE_STATUS_OK 0x0UL
3899 #define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL
3900 #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL
3901 #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
3902 #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3903 #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL
3904 #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL
3905 #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL
3906 #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL
3907 #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL
3908 #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL
3909 #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL
3910 #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL
3911 #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
3912 #define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL
3913 #define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL
3914 #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR
3915 __le16 reserved16;
3916 __le32 opaque;
3917 };
3918
3919 /* cq_req (size:256b/32B) */
3920 struct cq_req {
3921 __le64 qp_handle;
3922 __le16 sq_cons_idx;
3923 __le16 reserved16_1;
3924 __le32 reserved32_2;
3925 __le64 reserved64;
3926 u8 cqe_type_toggle;
3927 #define CQ_REQ_TOGGLE 0x1UL
3928 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL
3929 #define CQ_REQ_CQE_TYPE_SFT 1
3930 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1)
3931 #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ
3932 #define CQ_REQ_PUSH 0x20UL
3933 u8 status;
3934 #define CQ_REQ_STATUS_OK 0x0UL
3935 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL
3936 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL
3937 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL
3938 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL
3939 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3940 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
3941 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL
3942 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL
3943 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL
3944 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL
3945 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL
3946 #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR
3947 __le16 reserved16_2;
3948 __le32 reserved32_1;
3949 };
3950
3951 /* cq_res_rc (size:256b/32B) */
3952 struct cq_res_rc {
3953 __le32 length;
3954 __le32 imm_data_or_inv_r_key;
3955 __le64 qp_handle;
3956 __le64 mr_handle;
3957 u8 cqe_type_toggle;
3958 #define CQ_RES_RC_TOGGLE 0x1UL
3959 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL
3960 #define CQ_RES_RC_CQE_TYPE_SFT 1
3961 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1)
3962 #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC
3963 u8 status;
3964 #define CQ_RES_RC_STATUS_OK 0x0UL
3965 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL
3966 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL
3967 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL
3968 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3969 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3970 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
3971 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
3972 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL
3973 #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR
3974 __le16 flags;
3975 #define CQ_RES_RC_FLAGS_SRQ 0x1UL
3976 #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL
3977 #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL
3978 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ
3979 #define CQ_RES_RC_FLAGS_IMM 0x2UL
3980 #define CQ_RES_RC_FLAGS_INV 0x4UL
3981 #define CQ_RES_RC_FLAGS_RDMA 0x8UL
3982 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3)
3983 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3)
3984 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
3985 __le32 srq_or_rq_wr_id;
3986 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
3987 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
3988 };
3989
3990 /* cq_res_ud (size:256b/32B) */
3991 struct cq_res_ud {
3992 __le16 length;
3993 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL
3994 #define CQ_RES_UD_LENGTH_SFT 0
3995 __le16 cfa_metadata;
3996 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL
3997 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0
3998 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL
3999 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL
4000 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13
4001 __le32 imm_data;
4002 __le64 qp_handle;
4003 __le16 src_mac[3];
4004 __le16 src_qp_low;
4005 u8 cqe_type_toggle;
4006 #define CQ_RES_UD_TOGGLE 0x1UL
4007 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL
4008 #define CQ_RES_UD_CQE_TYPE_SFT 1
4009 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1)
4010 #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD
4011 u8 status;
4012 #define CQ_RES_UD_STATUS_OK 0x0UL
4013 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4014 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4015 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4016 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4017 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4018 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4019 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL
4020 #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR
4021 __le16 flags;
4022 #define CQ_RES_UD_FLAGS_SRQ 0x1UL
4023 #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL
4024 #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL
4025 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
4026 #define CQ_RES_UD_FLAGS_IMM 0x2UL
4027 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL
4028 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2
4029 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL
4030 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4
4031 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4032 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4033 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4034 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
4035 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL
4036 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6
4037 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4038 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
4039 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4040 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4041 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4042 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET
4043 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
4044 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10
4045 __le32 src_qp_high_srq_or_rq_wr_id;
4046 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4047 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
4048 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL
4049 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24
4050 };
4051
4052 /* cq_res_ud_v2 (size:256b/32B) */
4053 struct cq_res_ud_v2 {
4054 __le16 length;
4055 #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL
4056 #define CQ_RES_UD_V2_LENGTH_SFT 0
4057 __le16 cfa_metadata0;
4058 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL
4059 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0
4060 #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL
4061 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4062 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13
4063 __le32 imm_data;
4064 __le64 qp_handle;
4065 __le16 src_mac[3];
4066 __le16 src_qp_low;
4067 u8 cqe_type_toggle;
4068 #define CQ_RES_UD_V2_TOGGLE 0x1UL
4069 #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL
4070 #define CQ_RES_UD_V2_CQE_TYPE_SFT 1
4071 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1)
4072 #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD
4073 u8 status;
4074 #define CQ_RES_UD_V2_STATUS_OK 0x0UL
4075 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4076 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4077 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4078 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4079 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4080 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4081 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL
4082 #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR
4083 __le16 flags;
4084 #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL
4085 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL
4086 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL
4087 #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ
4088 #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL
4089 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL
4090 #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2
4091 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
4092 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4
4093 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4094 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4095 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4096 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6
4097 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
4098 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6
4099 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4100 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
4101 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4102 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4103 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4104 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET
4105 __le32 src_qp_high_srq_or_rq_wr_id;
4106 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4107 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0
4108 #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL
4109 #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20
4110 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4111 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20
4112 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4113 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4114 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4115 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4116 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4117 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4118 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4119 #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL
4120 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL
4121 #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24
4122 };
4123
4124 /* cq_res_ud_cfa (size:256b/32B) */
4125 struct cq_res_ud_cfa {
4126 __le16 length;
4127 #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL
4128 #define CQ_RES_UD_CFA_LENGTH_SFT 0
4129 __le16 cfa_code;
4130 __le32 imm_data;
4131 __le32 qid;
4132 #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL
4133 #define CQ_RES_UD_CFA_QID_SFT 0
4134 __le32 cfa_metadata;
4135 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL
4136 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0
4137 #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL
4138 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL
4139 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13
4140 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL
4141 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16
4142 __le16 src_mac[3];
4143 __le16 src_qp_low;
4144 u8 cqe_type_toggle;
4145 #define CQ_RES_UD_CFA_TOGGLE 0x1UL
4146 #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL
4147 #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1
4148 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
4149 #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA
4150 u8 status;
4151 #define CQ_RES_UD_CFA_STATUS_OK 0x0UL
4152 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4153 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4154 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4155 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4156 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4157 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4158 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL
4159 #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR
4160 __le16 flags;
4161 #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL
4162 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL
4163 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL
4164 #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ
4165 #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL
4166 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL
4167 #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2
4168 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL
4169 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4
4170 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4171 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4172 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4173 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6
4174 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL
4175 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6
4176 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4177 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
4178 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4179 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4180 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4181 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET
4182 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
4183 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10
4184 __le32 src_qp_high_srq_or_rq_wr_id;
4185 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4186 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0
4187 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL
4188 #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24
4189 };
4190
4191 /* cq_res_ud_cfa_v2 (size:256b/32B) */
4192 struct cq_res_ud_cfa_v2 {
4193 __le16 length;
4194 #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL
4195 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0
4196 __le16 cfa_metadata0;
4197 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL
4198 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0
4199 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL
4200 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4201 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13
4202 __le32 imm_data;
4203 __le32 qid;
4204 #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL
4205 #define CQ_RES_UD_CFA_V2_QID_SFT 0
4206 __le32 cfa_metadata2;
4207 __le16 src_mac[3];
4208 __le16 src_qp_low;
4209 u8 cqe_type_toggle;
4210 #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL
4211 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL
4212 #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1
4213 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
4214 #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA
4215 u8 status;
4216 #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL
4217 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4218 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4219 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4220 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4221 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4222 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4223 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL
4224 #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR
4225 __le16 flags;
4226 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL
4227 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL
4228 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL
4229 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ
4230 #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL
4231 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL
4232 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2
4233 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
4234 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4
4235 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4236 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4237 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4238 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6
4239 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
4240 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6
4241 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4242 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
4243 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4244 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4245 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4246 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \
4247 CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET
4248 __le32 src_qp_high_srq_or_rq_wr_id;
4249 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4250 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0
4251 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL
4252 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20
4253 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4254 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20
4255 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4256 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4257 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4258 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4259 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4260 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4261 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \
4262 CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4263 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL
4264 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL
4265 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24
4266 };
4267
4268 /* cq_res_raweth_qp1 (size:256b/32B) */
4269 struct cq_res_raweth_qp1 {
4270 __le16 length;
4271 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL
4272 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
4273 __le16 raweth_qp1_flags;
4274 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL
4275 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
4276 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL
4277 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
4278 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4279 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
4280 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
4281 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
4282 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
4283 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
4284 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
4285 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
4286 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
4287 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
4288 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \
4289 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4290 __le16 raweth_qp1_errors;
4291 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
4292 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
4293 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
4294 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
4295 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
4296 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
4297 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4298 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
4299 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
4300 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
4301 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
4302 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
4303 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
4304 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
4305 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
4306 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4307 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
4308 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4309 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
4310 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
4311 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
4312 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
4313 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
4314 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
4315 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
4316 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
4317 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
4318 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
4319 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4320 __le16 raweth_qp1_cfa_code;
4321 __le64 qp_handle;
4322 __le32 raweth_qp1_flags2;
4323 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL
4324 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL
4325 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL
4326 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL
4327 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
4328 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4329 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
4330 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4)
4331 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
4332 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
4333 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
4334 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \
4335 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
4336 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
4337 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
4338 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL
4339 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10
4340 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
4341 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4342 __le32 raweth_qp1_metadata;
4343 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL
4344 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0
4345 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL
4346 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
4347 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL
4348 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL
4349 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13
4350 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL
4351 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16
4352 u8 cqe_type_toggle;
4353 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL
4354 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL
4355 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1
4356 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
4357 #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1
4358 u8 status;
4359 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL
4360 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4361 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4362 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4363 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4364 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4365 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4366 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL
4367 #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR
4368 __le16 flags;
4369 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL
4370 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL
4371 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL
4372 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
4373 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
4374 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4375 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
4376 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
4377 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4378 };
4379
4380 /* cq_res_raweth_qp1_v2 (size:256b/32B) */
4381 struct cq_res_raweth_qp1_v2 {
4382 __le16 length;
4383 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL
4384 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0
4385 __le16 raweth_qp1_flags;
4386 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL
4387 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0
4388 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL
4389 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
4390 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4391 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
4392 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
4393 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
4394 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
4395 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
4396 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
4397 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
4398 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
4399 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
4400 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \
4401 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4402 __le16 raweth_qp1_errors;
4403 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
4404 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
4405 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
4406 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
4407 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
4408 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
4409 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4410 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
4411 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
4412 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
4413 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
4414 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
4415 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
4416 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
4417 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
4418 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4419 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
4420 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4421 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
4422 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
4423 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
4424 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
4425 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
4426 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
4427 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
4428 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4429 (0x7UL << 12)
4430 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4431 (0x8UL << 12)
4432 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
4433 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4434 __le16 cfa_metadata0;
4435 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL
4436 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0
4437 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL
4438 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4439 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13
4440 __le64 qp_handle;
4441 __le32 raweth_qp1_flags2;
4442 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL
4443 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
4444 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4445 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
4446 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
4447 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
4448 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
4449 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
4450 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \
4451 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
4452 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
4453 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
4454 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL
4455 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10
4456 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
4457 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4458 __le32 cfa_metadata2;
4459 u8 cqe_type_toggle;
4460 #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL
4461 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL
4462 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1
4463 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
4464 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1
4465 u8 status;
4466 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL
4467 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4468 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4469 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4470 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4471 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4472 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4473 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL
4474 #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR
4475 __le16 flags;
4476 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL
4477 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL
4478 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL
4479 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ
4480 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
4481 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4482 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0
4483 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL
4484 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20
4485 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4486 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20
4487 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4488 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4489 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4490 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4491 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4492 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4493 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \
4494 CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4495 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL
4496 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
4497 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4498 };
4499
4500 /* cq_terminal (size:256b/32B) */
4501 struct cq_terminal {
4502 __le64 qp_handle;
4503 __le16 sq_cons_idx;
4504 __le16 rq_cons_idx;
4505 __le32 reserved32_1;
4506 __le64 reserved64_3;
4507 u8 cqe_type_toggle;
4508 #define CQ_TERMINAL_TOGGLE 0x1UL
4509 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL
4510 #define CQ_TERMINAL_CQE_TYPE_SFT 1
4511 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1)
4512 #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL
4513 u8 status;
4514 #define CQ_TERMINAL_STATUS_OK 0x0UL
4515 #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK
4516 __le16 reserved16;
4517 __le32 reserved32_2;
4518 };
4519
4520 /* cq_cutoff (size:256b/32B) */
4521 struct cq_cutoff {
4522 __le64 reserved64_1;
4523 __le64 reserved64_2;
4524 __le64 reserved64_3;
4525 u8 cqe_type_toggle;
4526 #define CQ_CUTOFF_TOGGLE 0x1UL
4527 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL
4528 #define CQ_CUTOFF_CQE_TYPE_SFT 1
4529 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1)
4530 #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF
4531 #define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL
4532 #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5
4533 u8 status;
4534 #define CQ_CUTOFF_STATUS_OK 0x0UL
4535 #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK
4536 __le16 reserved16;
4537 __le32 reserved32;
4538 };
4539
4540 /* nq_base (size:128b/16B) */
4541 struct nq_base {
4542 __le16 info10_type;
4543 #define NQ_BASE_TYPE_MASK 0x3fUL
4544 #define NQ_BASE_TYPE_SFT 0
4545 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL
4546 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL
4547 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL
4548 #define NQ_BASE_TYPE_QP_EVENT 0x38UL
4549 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL
4550 #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT
4551 #define NQ_BASE_INFO10_MASK 0xffc0UL
4552 #define NQ_BASE_INFO10_SFT 6
4553 __le16 info16;
4554 __le32 info32;
4555 __le32 info63_v[2];
4556 #define NQ_BASE_V 0x1UL
4557 #define NQ_BASE_INFO63_MASK 0xfffffffeUL
4558 #define NQ_BASE_INFO63_SFT 1
4559 };
4560
4561 /* nq_cn (size:128b/16B) */
4562 struct nq_cn {
4563 __le16 type;
4564 #define NQ_CN_TYPE_MASK 0x3fUL
4565 #define NQ_CN_TYPE_SFT 0
4566 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
4567 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
4568 #define NQ_CN_TOGGLE_MASK 0xc0UL
4569 #define NQ_CN_TOGGLE_SFT 6
4570 __le16 reserved16;
4571 __le32 cq_handle_low;
4572 __le32 v;
4573 #define NQ_CN_V 0x1UL
4574 __le32 cq_handle_high;
4575 };
4576
4577 /* nq_srq_event (size:128b/16B) */
4578 struct nq_srq_event {
4579 u8 type;
4580 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL
4581 #define NQ_SRQ_EVENT_TYPE_SFT 0
4582 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL
4583 #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT
4584 #define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL
4585 #define NQ_SRQ_EVENT_TOGGLE_SFT 6
4586 u8 event;
4587 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL
4588 #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT
4589 __le16 reserved16;
4590 __le32 srq_handle_low;
4591 __le32 v;
4592 #define NQ_SRQ_EVENT_V 0x1UL
4593 __le32 srq_handle_high;
4594 };
4595
4596 /* nq_dbq_event (size:128b/16B) */
4597 struct nq_dbq_event {
4598 u8 type;
4599 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL
4600 #define NQ_DBQ_EVENT_TYPE_SFT 0
4601 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL
4602 #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT
4603 u8 event;
4604 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL
4605 #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT
4606 __le16 db_pfid;
4607 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL
4608 #define NQ_DBQ_EVENT_DB_PFID_SFT 0
4609 __le32 db_dpi;
4610 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL
4611 #define NQ_DBQ_EVENT_DB_DPI_SFT 0
4612 __le32 v;
4613 #define NQ_DBQ_EVENT_V 0x1UL
4614 __le32 db_type_db_xid;
4615 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL
4616 #define NQ_DBQ_EVENT_DB_XID_SFT 0
4617 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL
4618 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28
4619 };
4620
4621 /* xrrq_irrq (size:256b/32B) */
4622 struct xrrq_irrq {
4623 __le16 credits_type;
4624 #define XRRQ_IRRQ_TYPE 0x1UL
4625 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL
4626 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL
4627 #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ
4628 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL
4629 #define XRRQ_IRRQ_CREDITS_SFT 11
4630 __le16 reserved16;
4631 __le32 reserved32;
4632 __le32 psn;
4633 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL
4634 #define XRRQ_IRRQ_PSN_SFT 0
4635 __le32 msn;
4636 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL
4637 #define XRRQ_IRRQ_MSN_SFT 0
4638 __le64 va_or_atomic_result;
4639 __le32 rdma_r_key;
4640 __le32 length;
4641 };
4642
4643 /* xrrq_orrq (size:256b/32B) */
4644 struct xrrq_orrq {
4645 __le16 num_sges_type;
4646 #define XRRQ_ORRQ_TYPE 0x1UL
4647 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL
4648 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL
4649 #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ
4650 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL
4651 #define XRRQ_ORRQ_NUM_SGES_SFT 11
4652 __le16 reserved16;
4653 __le32 length;
4654 __le32 psn;
4655 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL
4656 #define XRRQ_ORRQ_PSN_SFT 0
4657 __le32 end_psn;
4658 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL
4659 #define XRRQ_ORRQ_END_PSN_SFT 0
4660 __le64 first_sge_phy_or_sing_sge_va;
4661 __le32 single_sge_l_key;
4662 __le32 single_sge_size;
4663 };
4664
4665 /* ptu_pte (size:64b/8B) */
4666 struct ptu_pte {
4667 __le32 page_next_to_last_last_valid[2];
4668 #define PTU_PTE_VALID 0x1UL
4669 #define PTU_PTE_LAST 0x2UL
4670 #define PTU_PTE_NEXT_TO_LAST 0x4UL
4671 #define PTU_PTE_UNUSED_MASK 0xff8UL
4672 #define PTU_PTE_UNUSED_SFT 3
4673 #define PTU_PTE_PAGE_MASK 0xfffff000UL
4674 #define PTU_PTE_PAGE_SFT 12
4675 };
4676
4677 /* ptu_pde (size:64b/8B) */
4678 struct ptu_pde {
4679 __le32 page_valid[2];
4680 #define PTU_PDE_VALID 0x1UL
4681 #define PTU_PDE_UNUSED_MASK 0xffeUL
4682 #define PTU_PDE_UNUSED_SFT 1
4683 #define PTU_PDE_PAGE_MASK 0xfffff000UL
4684 #define PTU_PDE_PAGE_SFT 12
4685 };
4686
4687 #endif /* ___BNXT_RE_HSI_H__ */
Kernel DRM miscellaneous fixes and cross-tree changes