drm/imagination: Use the drm_sched_job_has_dependency helper
[drm/drm-misc.git] / drivers / input / serio / i8042.c
blob509330a27880275e440fbf57c732907c4340a8c6
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i8042 keyboard and mouse controller driver for Linux
5 * Copyright (c) 1999-2004 Vojtech Pavlik
6 */
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/types.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/init.h>
17 #include <linux/serio.h>
18 #include <linux/err.h>
19 #include <linux/rcupdate.h>
20 #include <linux/platform_device.h>
21 #include <linux/i8042.h>
22 #include <linux/slab.h>
23 #include <linux/suspend.h>
24 #include <linux/property.h>
26 #include <asm/io.h>
28 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
29 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
30 MODULE_LICENSE("GPL");
32 static bool i8042_nokbd;
33 module_param_named(nokbd, i8042_nokbd, bool, 0);
34 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
36 static bool i8042_noaux;
37 module_param_named(noaux, i8042_noaux, bool, 0);
38 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
40 static bool i8042_nomux;
41 module_param_named(nomux, i8042_nomux, bool, 0);
42 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
44 static bool i8042_unlock;
45 module_param_named(unlock, i8042_unlock, bool, 0);
46 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
48 static bool i8042_probe_defer;
49 module_param_named(probe_defer, i8042_probe_defer, bool, 0);
50 MODULE_PARM_DESC(probe_defer, "Allow deferred probing.");
52 enum i8042_controller_reset_mode {
53 I8042_RESET_NEVER,
54 I8042_RESET_ALWAYS,
55 I8042_RESET_ON_S2RAM,
56 #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM
58 static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT;
59 static int i8042_set_reset(const char *val, const struct kernel_param *kp)
61 enum i8042_controller_reset_mode *arg = kp->arg;
62 int error;
63 bool reset;
65 if (val) {
66 error = kstrtobool(val, &reset);
67 if (error)
68 return error;
69 } else {
70 reset = true;
73 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER;
74 return 0;
77 static const struct kernel_param_ops param_ops_reset_param = {
78 .flags = KERNEL_PARAM_OPS_FL_NOARG,
79 .set = i8042_set_reset,
81 #define param_check_reset_param(name, p) \
82 __param_check(name, p, enum i8042_controller_reset_mode)
83 module_param_named(reset, i8042_reset, reset_param, 0);
84 MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both");
86 static bool i8042_direct;
87 module_param_named(direct, i8042_direct, bool, 0);
88 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
90 static bool i8042_dumbkbd;
91 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
92 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
94 static bool i8042_noloop;
95 module_param_named(noloop, i8042_noloop, bool, 0);
96 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
98 static bool i8042_notimeout;
99 module_param_named(notimeout, i8042_notimeout, bool, 0);
100 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
102 static bool i8042_kbdreset;
103 module_param_named(kbdreset, i8042_kbdreset, bool, 0);
104 MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
106 #ifdef CONFIG_X86
107 static bool i8042_dritek;
108 module_param_named(dritek, i8042_dritek, bool, 0);
109 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
110 #endif
112 #ifdef CONFIG_PNP
113 static bool i8042_nopnp;
114 module_param_named(nopnp, i8042_nopnp, bool, 0);
115 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
116 #endif
118 static bool i8042_forcenorestore;
119 module_param_named(forcenorestore, i8042_forcenorestore, bool, 0);
120 MODULE_PARM_DESC(forcenorestore, "Force no restore on s3 resume, copying s2idle behaviour");
122 #define DEBUG
123 #ifdef DEBUG
124 static bool i8042_debug;
125 module_param_named(debug, i8042_debug, bool, 0600);
126 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
128 static bool i8042_unmask_kbd_data;
129 module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600);
130 MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]");
131 #endif
133 static bool i8042_present;
134 static bool i8042_bypass_aux_irq_test;
135 static char i8042_kbd_firmware_id[128];
136 static char i8042_aux_firmware_id[128];
137 static struct fwnode_handle *i8042_kbd_fwnode;
139 #include "i8042.h"
142 * i8042_lock protects serialization between i8042_command and
143 * the interrupt handler.
145 static DEFINE_SPINLOCK(i8042_lock);
148 * Writers to AUX and KBD ports as well as users issuing i8042_command
149 * directly should acquire i8042_mutex (by means of calling
150 * i8042_lock_chip() and i8042_unlock_chip() helpers) to ensure that
151 * they do not disturb each other (unfortunately in many i8042
152 * implementations write to one of the ports will immediately abort
153 * command that is being processed by another port).
155 static DEFINE_MUTEX(i8042_mutex);
157 struct i8042_port {
158 struct serio *serio;
159 int irq;
160 bool exists;
161 bool driver_bound;
162 signed char mux;
165 #define I8042_KBD_PORT_NO 0
166 #define I8042_AUX_PORT_NO 1
167 #define I8042_MUX_PORT_NO 2
168 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
170 static struct i8042_port i8042_ports[I8042_NUM_PORTS];
172 static unsigned char i8042_initial_ctr;
173 static unsigned char i8042_ctr;
174 static bool i8042_mux_present;
175 static bool i8042_kbd_irq_registered;
176 static bool i8042_aux_irq_registered;
177 static unsigned char i8042_suppress_kbd_ack;
178 static struct platform_device *i8042_platform_device;
179 static struct notifier_block i8042_kbd_bind_notifier_block;
181 static bool i8042_handle_data(int irq);
182 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
183 struct serio *serio);
185 void i8042_lock_chip(void)
187 mutex_lock(&i8042_mutex);
189 EXPORT_SYMBOL(i8042_lock_chip);
191 void i8042_unlock_chip(void)
193 mutex_unlock(&i8042_mutex);
195 EXPORT_SYMBOL(i8042_unlock_chip);
197 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
198 struct serio *serio))
200 guard(spinlock_irqsave)(&i8042_lock);
202 if (i8042_platform_filter)
203 return -EBUSY;
205 i8042_platform_filter = filter;
206 return 0;
208 EXPORT_SYMBOL(i8042_install_filter);
210 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
211 struct serio *port))
213 guard(spinlock_irqsave)(&i8042_lock);
215 if (i8042_platform_filter != filter)
216 return -EINVAL;
218 i8042_platform_filter = NULL;
219 return 0;
221 EXPORT_SYMBOL(i8042_remove_filter);
224 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
225 * be ready for reading values from it / writing values to it.
226 * Called always with i8042_lock held.
229 static int i8042_wait_read(void)
231 int i = 0;
233 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
234 udelay(50);
235 i++;
237 return -(i == I8042_CTL_TIMEOUT);
240 static int i8042_wait_write(void)
242 int i = 0;
244 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
245 udelay(50);
246 i++;
248 return -(i == I8042_CTL_TIMEOUT);
252 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
253 * of the i8042 down the toilet.
256 static int i8042_flush(void)
258 unsigned char data, str;
259 int count = 0;
261 guard(spinlock_irqsave)(&i8042_lock);
263 while ((str = i8042_read_status()) & I8042_STR_OBF) {
264 if (count++ >= I8042_BUFFER_SIZE)
265 return -EIO;
267 udelay(50);
268 data = i8042_read_data();
269 dbg("%02x <- i8042 (flush, %s)\n",
270 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
273 return 0;
277 * i8042_command() executes a command on the i8042. It also sends the input
278 * parameter(s) of the commands to it, and receives the output value(s). The
279 * parameters are to be stored in the param array, and the output is placed
280 * into the same array. The number of the parameters and output values is
281 * encoded in bits 8-11 of the command number.
284 static int __i8042_command(unsigned char *param, int command)
286 int i, error;
288 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
289 return -1;
291 error = i8042_wait_write();
292 if (error)
293 return error;
295 dbg("%02x -> i8042 (command)\n", command & 0xff);
296 i8042_write_command(command & 0xff);
298 for (i = 0; i < ((command >> 12) & 0xf); i++) {
299 error = i8042_wait_write();
300 if (error) {
301 dbg(" -- i8042 (wait write timeout)\n");
302 return error;
304 dbg("%02x -> i8042 (parameter)\n", param[i]);
305 i8042_write_data(param[i]);
308 for (i = 0; i < ((command >> 8) & 0xf); i++) {
309 error = i8042_wait_read();
310 if (error) {
311 dbg(" -- i8042 (wait read timeout)\n");
312 return error;
315 if (command == I8042_CMD_AUX_LOOP &&
316 !(i8042_read_status() & I8042_STR_AUXDATA)) {
317 dbg(" -- i8042 (auxerr)\n");
318 return -1;
321 param[i] = i8042_read_data();
322 dbg("%02x <- i8042 (return)\n", param[i]);
325 return 0;
328 int i8042_command(unsigned char *param, int command)
330 if (!i8042_present)
331 return -1;
333 guard(spinlock_irqsave)(&i8042_lock);
335 return __i8042_command(param, command);
337 EXPORT_SYMBOL(i8042_command);
340 * i8042_kbd_write() sends a byte out through the keyboard interface.
343 static int i8042_kbd_write(struct serio *port, unsigned char c)
345 int error;
347 guard(spinlock_irqsave)(&i8042_lock);
349 error = i8042_wait_write();
350 if (error)
351 return error;
353 dbg("%02x -> i8042 (kbd-data)\n", c);
354 i8042_write_data(c);
356 return 0;
360 * i8042_aux_write() sends a byte out through the aux interface.
363 static int i8042_aux_write(struct serio *serio, unsigned char c)
365 struct i8042_port *port = serio->port_data;
367 return i8042_command(&c, port->mux == -1 ?
368 I8042_CMD_AUX_SEND :
369 I8042_CMD_MUX_SEND + port->mux);
374 * i8042_port_close attempts to clear AUX or KBD port state by disabling
375 * and then re-enabling it.
378 static void i8042_port_close(struct serio *serio)
380 int irq_bit;
381 int disable_bit;
382 const char *port_name;
384 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
385 irq_bit = I8042_CTR_AUXINT;
386 disable_bit = I8042_CTR_AUXDIS;
387 port_name = "AUX";
388 } else {
389 irq_bit = I8042_CTR_KBDINT;
390 disable_bit = I8042_CTR_KBDDIS;
391 port_name = "KBD";
394 i8042_ctr &= ~irq_bit;
395 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
396 pr_warn("Can't write CTR while closing %s port\n", port_name);
398 udelay(50);
400 i8042_ctr &= ~disable_bit;
401 i8042_ctr |= irq_bit;
402 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
403 pr_err("Can't reactivate %s port\n", port_name);
406 * See if there is any data appeared while we were messing with
407 * port state.
409 i8042_handle_data(0);
413 * i8042_start() is called by serio core when port is about to finish
414 * registering. It will mark port as existing so i8042_interrupt can
415 * start sending data through it.
417 static int i8042_start(struct serio *serio)
419 struct i8042_port *port = serio->port_data;
421 device_set_wakeup_capable(&serio->dev, true);
424 * On platforms using suspend-to-idle, allow the keyboard to
425 * wake up the system from sleep by enabling keyboard wakeups
426 * by default. This is consistent with keyboard wakeup
427 * behavior on many platforms using suspend-to-RAM (ACPI S3)
428 * by default.
430 if (pm_suspend_default_s2idle() &&
431 serio == i8042_ports[I8042_KBD_PORT_NO].serio) {
432 device_set_wakeup_enable(&serio->dev, true);
435 guard(spinlock_irq)(&i8042_lock);
436 port->exists = true;
438 return 0;
442 * i8042_stop() marks serio port as non-existing so i8042_interrupt
443 * will not try to send data to the port that is about to go away.
444 * The function is called by serio core as part of unregister procedure.
446 static void i8042_stop(struct serio *serio)
448 struct i8042_port *port = serio->port_data;
450 scoped_guard(spinlock_irq, &i8042_lock) {
451 port->exists = false;
452 port->serio = NULL;
456 * We need to make sure that interrupt handler finishes using
457 * our serio port before we return from this function.
458 * We synchronize with both AUX and KBD IRQs because there is
459 * a (very unlikely) chance that AUX IRQ is raised for KBD port
460 * and vice versa.
462 synchronize_irq(I8042_AUX_IRQ);
463 synchronize_irq(I8042_KBD_IRQ);
467 * i8042_filter() filters out unwanted bytes from the input data stream.
468 * It is called from i8042_interrupt and thus is running with interrupts
469 * off and i8042_lock held.
471 static bool i8042_filter(unsigned char data, unsigned char str,
472 struct serio *serio)
474 if (unlikely(i8042_suppress_kbd_ack)) {
475 if ((~str & I8042_STR_AUXDATA) &&
476 (data == 0xfa || data == 0xfe)) {
477 i8042_suppress_kbd_ack--;
478 dbg("Extra keyboard ACK - filtered out\n");
479 return true;
483 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
484 dbg("Filtered out by platform filter\n");
485 return true;
488 return false;
492 * i8042_handle_mux() handles case when data is coming from one of
493 * the multiplexed ports. It would be simple if not for quirks with
494 * handling errors:
496 * When MUXERR condition is signalled the data register can only contain
497 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
498 * it is not always the case. Some KBCs also report 0xfc when there is
499 * nothing connected to the port while others sometimes get confused which
500 * port the data came from and signal error leaving the data intact. They
501 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
502 * to legacy mode yet, when we see one we'll add proper handling).
503 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
504 * rest assume that the data came from the same serio last byte
505 * was transmitted (if transmission happened not too long ago).
507 static int i8042_handle_mux(u8 str, u8 *data, unsigned int *dfl)
509 static unsigned long last_transmit;
510 static unsigned long last_port;
511 unsigned int mux_port;
513 mux_port = (str >> 6) & 3;
514 *dfl = 0;
516 if (str & I8042_STR_MUXERR) {
517 dbg("MUX error, status is %02x, data is %02x\n",
518 str, *data);
520 switch (*data) {
521 default:
522 if (time_before(jiffies, last_transmit + HZ/10)) {
523 mux_port = last_port;
524 break;
526 fallthrough; /* report timeout */
527 case 0xfc:
528 case 0xfd:
529 case 0xfe:
530 *dfl = SERIO_TIMEOUT;
531 *data = 0xfe;
532 break;
533 case 0xff:
534 *dfl = SERIO_PARITY;
535 *data = 0xfe;
536 break;
540 last_port = mux_port;
541 last_transmit = jiffies;
543 return I8042_MUX_PORT_NO + mux_port;
547 * i8042_handle_data() is the most important function in this driver -
548 * it reads the data from the i8042, determines its destination serio
549 * port, and sends received byte to the upper layers.
551 * Returns true if there was data waiting, false otherwise.
553 static bool i8042_handle_data(int irq)
555 struct i8042_port *port;
556 struct serio *serio;
557 unsigned char str, data;
558 unsigned int dfl;
559 unsigned int port_no;
560 bool filtered;
562 scoped_guard(spinlock_irqsave, &i8042_lock) {
563 str = i8042_read_status();
564 if (unlikely(~str & I8042_STR_OBF))
565 return false;
567 data = i8042_read_data();
569 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
570 port_no = i8042_handle_mux(str, &data, &dfl);
571 } else {
573 dfl = (str & I8042_STR_PARITY) ? SERIO_PARITY : 0;
574 if ((str & I8042_STR_TIMEOUT) && !i8042_notimeout)
575 dfl |= SERIO_TIMEOUT;
577 port_no = (str & I8042_STR_AUXDATA) ?
578 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
581 port = &i8042_ports[port_no];
582 serio = port->exists ? port->serio : NULL;
584 filter_dbg(port->driver_bound,
585 data, "<- i8042 (interrupt, %d, %d%s%s)\n",
586 port_no, irq,
587 dfl & SERIO_PARITY ? ", bad parity" : "",
588 dfl & SERIO_TIMEOUT ? ", timeout" : "");
590 filtered = i8042_filter(data, str, serio);
593 if (likely(serio && !filtered))
594 serio_interrupt(serio, data, dfl);
596 return true;
599 static irqreturn_t i8042_interrupt(int irq, void *dev_id)
601 if (unlikely(!i8042_handle_data(irq))) {
602 dbg("Interrupt %d, without any data\n", irq);
603 return IRQ_NONE;
606 return IRQ_HANDLED;
610 * i8042_enable_kbd_port enables keyboard port on chip
613 static int i8042_enable_kbd_port(void)
615 i8042_ctr &= ~I8042_CTR_KBDDIS;
616 i8042_ctr |= I8042_CTR_KBDINT;
618 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
619 i8042_ctr &= ~I8042_CTR_KBDINT;
620 i8042_ctr |= I8042_CTR_KBDDIS;
621 pr_err("Failed to enable KBD port\n");
622 return -EIO;
625 return 0;
629 * i8042_enable_aux_port enables AUX (mouse) port on chip
632 static int i8042_enable_aux_port(void)
634 i8042_ctr &= ~I8042_CTR_AUXDIS;
635 i8042_ctr |= I8042_CTR_AUXINT;
637 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
638 i8042_ctr &= ~I8042_CTR_AUXINT;
639 i8042_ctr |= I8042_CTR_AUXDIS;
640 pr_err("Failed to enable AUX port\n");
641 return -EIO;
644 return 0;
648 * i8042_enable_mux_ports enables 4 individual AUX ports after
649 * the controller has been switched into Multiplexed mode
652 static int i8042_enable_mux_ports(void)
654 unsigned char param;
655 int i;
657 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
658 i8042_command(&param, I8042_CMD_MUX_PFX + i);
659 i8042_command(&param, I8042_CMD_AUX_ENABLE);
662 return i8042_enable_aux_port();
666 * i8042_set_mux_mode checks whether the controller has an
667 * active multiplexor and puts the chip into Multiplexed (true)
668 * or Legacy (false) mode.
671 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
674 unsigned char param, val;
676 * Get rid of bytes in the queue.
679 i8042_flush();
682 * Internal loopback test - send three bytes, they should come back from the
683 * mouse interface, the last should be version.
686 param = val = 0xf0;
687 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != val)
688 return -1;
689 param = val = multiplex ? 0x56 : 0xf6;
690 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != val)
691 return -1;
692 param = val = multiplex ? 0xa4 : 0xa5;
693 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == val)
694 return -1;
697 * Workaround for interference with USB Legacy emulation
698 * that causes a v10.12 MUX to be found.
700 if (param == 0xac)
701 return -1;
703 if (mux_version)
704 *mux_version = param;
706 return 0;
710 * i8042_check_mux() checks whether the controller supports the PS/2 Active
711 * Multiplexing specification by Synaptics, Phoenix, Insyde and
712 * LCS/Telegraphics.
715 static int i8042_check_mux(void)
717 unsigned char mux_version;
719 if (i8042_set_mux_mode(true, &mux_version))
720 return -1;
722 pr_info("Detected active multiplexing controller, rev %d.%d\n",
723 (mux_version >> 4) & 0xf, mux_version & 0xf);
726 * Disable all muxed ports by disabling AUX.
728 i8042_ctr |= I8042_CTR_AUXDIS;
729 i8042_ctr &= ~I8042_CTR_AUXINT;
731 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
732 pr_err("Failed to disable AUX port, can't use MUX\n");
733 return -EIO;
736 i8042_mux_present = true;
738 return 0;
742 * The following is used to test AUX IRQ delivery.
744 static struct completion i8042_aux_irq_delivered;
745 static bool i8042_irq_being_tested;
747 static irqreturn_t i8042_aux_test_irq(int irq, void *dev_id)
749 unsigned char str, data;
751 guard(spinlock_irqsave)(&i8042_lock);
753 str = i8042_read_status();
754 if (!(str & I8042_STR_OBF))
755 return IRQ_NONE;
757 data = i8042_read_data();
758 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
759 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
761 if (i8042_irq_being_tested && data == 0xa5 && (str & I8042_STR_AUXDATA))
762 complete(&i8042_aux_irq_delivered);
764 return IRQ_HANDLED;
768 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
769 * verifies success by readinng CTR. Used when testing for presence of AUX
770 * port.
772 static int i8042_toggle_aux(bool on)
774 unsigned char param;
775 int i;
777 if (i8042_command(&param,
778 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
779 return -1;
781 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
782 for (i = 0; i < 100; i++) {
783 udelay(50);
785 if (i8042_command(&param, I8042_CMD_CTL_RCTR))
786 return -1;
788 if (!(param & I8042_CTR_AUXDIS) == on)
789 return 0;
792 return -1;
796 * i8042_check_aux() applies as much paranoia as it can at detecting
797 * the presence of an AUX interface.
800 static int i8042_check_aux(void)
802 int retval = -1;
803 bool irq_registered = false;
804 bool aux_loop_broken = false;
805 unsigned char param;
808 * Get rid of bytes in the queue.
811 i8042_flush();
814 * Internal loopback test - filters out AT-type i8042's. Unfortunately
815 * SiS screwed up and their 5597 doesn't support the LOOP command even
816 * though it has an AUX port.
819 param = 0x5a;
820 retval = i8042_command(&param, I8042_CMD_AUX_LOOP);
821 if (retval || param != 0x5a) {
824 * External connection test - filters out AT-soldered PS/2 i8042's
825 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
826 * 0xfa - no error on some notebooks which ignore the spec
827 * Because it's common for chipsets to return error on perfectly functioning
828 * AUX ports, we test for this only when the LOOP command failed.
831 if (i8042_command(&param, I8042_CMD_AUX_TEST) ||
832 (param && param != 0xfa && param != 0xff))
833 return -1;
836 * If AUX_LOOP completed without error but returned unexpected data
837 * mark it as broken
839 if (!retval)
840 aux_loop_broken = true;
844 * Bit assignment test - filters out PS/2 i8042's in AT mode
847 if (i8042_toggle_aux(false)) {
848 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
849 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
852 if (i8042_toggle_aux(true))
853 return -1;
856 * Reset keyboard (needed on some laptops to successfully detect
857 * touchpad, e.g., some Gigabyte laptop models with Elantech
858 * touchpads).
860 if (i8042_kbdreset) {
861 pr_warn("Attempting to reset device connected to KBD port\n");
862 i8042_kbd_write(NULL, (unsigned char) 0xff);
866 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
867 * used it for a PCI card or somethig else.
870 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
872 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
873 * is working and hope we are right.
875 retval = 0;
876 goto out;
879 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
880 "i8042", i8042_platform_device))
881 goto out;
883 irq_registered = true;
885 if (i8042_enable_aux_port())
886 goto out;
888 scoped_guard(spinlock_irqsave, &i8042_lock) {
889 init_completion(&i8042_aux_irq_delivered);
890 i8042_irq_being_tested = true;
892 param = 0xa5;
893 retval = __i8042_command(&param, I8042_CMD_AUX_LOOP & 0xf0ff);
894 if (retval)
895 goto out;
898 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
899 msecs_to_jiffies(250)) == 0) {
901 * AUX IRQ was never delivered so we need to flush the controller to
902 * get rid of the byte we put there; otherwise keyboard may not work.
904 dbg(" -- i8042 (aux irq test timeout)\n");
905 i8042_flush();
906 retval = -1;
909 out:
912 * Disable the interface.
915 i8042_ctr |= I8042_CTR_AUXDIS;
916 i8042_ctr &= ~I8042_CTR_AUXINT;
918 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
919 retval = -1;
921 if (irq_registered)
922 free_irq(I8042_AUX_IRQ, i8042_platform_device);
924 return retval;
927 static int i8042_controller_check(void)
929 if (i8042_flush()) {
930 pr_info("No controller found\n");
931 return -ENODEV;
934 return 0;
937 static int i8042_controller_selftest(void)
939 unsigned char param;
940 int i = 0;
943 * We try this 5 times; on some really fragile systems this does not
944 * take the first time...
946 do {
948 if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
949 pr_err("i8042 controller selftest timeout\n");
950 return -ENODEV;
953 if (param == I8042_RET_CTL_TEST)
954 return 0;
956 dbg("i8042 controller selftest: %#x != %#x\n",
957 param, I8042_RET_CTL_TEST);
958 msleep(50);
959 } while (i++ < 5);
961 #ifdef CONFIG_X86
963 * On x86, we don't fail entire i8042 initialization if controller
964 * reset fails in hopes that keyboard port will still be functional
965 * and user will still get a working keyboard. This is especially
966 * important on netbooks. On other arches we trust hardware more.
968 pr_info("giving up on controller selftest, continuing anyway...\n");
969 return 0;
970 #else
971 pr_err("i8042 controller selftest failed\n");
972 return -EIO;
973 #endif
977 * i8042_controller_init initializes the i8042 controller, and,
978 * most importantly, sets it into non-xlated mode if that's
979 * desired.
982 static int i8042_controller_init(void)
984 int n = 0;
985 unsigned char ctr[2];
988 * Save the CTR for restore on unload / reboot.
991 do {
992 if (n >= 10) {
993 pr_err("Unable to get stable CTR read\n");
994 return -EIO;
997 if (n != 0)
998 udelay(50);
1000 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
1001 pr_err("Can't read CTR while initializing i8042\n");
1002 return i8042_probe_defer ? -EPROBE_DEFER : -EIO;
1005 } while (n < 2 || ctr[0] != ctr[1]);
1007 i8042_initial_ctr = i8042_ctr = ctr[0];
1010 * Disable the keyboard interface and interrupt.
1013 i8042_ctr |= I8042_CTR_KBDDIS;
1014 i8042_ctr &= ~I8042_CTR_KBDINT;
1017 * Handle keylock.
1020 scoped_guard(spinlock_irqsave, &i8042_lock) {
1021 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
1022 if (i8042_unlock)
1023 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
1024 else
1025 pr_warn("Warning: Keylock active\n");
1030 * If the chip is configured into nontranslated mode by the BIOS, don't
1031 * bother enabling translating and be happy.
1034 if (~i8042_ctr & I8042_CTR_XLATE)
1035 i8042_direct = true;
1038 * Set nontranslated mode for the kbd interface if requested by an option.
1039 * After this the kbd interface becomes a simple serial in/out, like the aux
1040 * interface is. We don't do this by default, since it can confuse notebook
1041 * BIOSes.
1044 if (i8042_direct)
1045 i8042_ctr &= ~I8042_CTR_XLATE;
1048 * Write CTR back.
1051 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1052 pr_err("Can't write CTR while initializing i8042\n");
1053 return -EIO;
1057 * Flush whatever accumulated while we were disabling keyboard port.
1060 i8042_flush();
1062 return 0;
1067 * Reset the controller and reset CRT to the original value set by BIOS.
1070 static void i8042_controller_reset(bool s2r_wants_reset)
1072 i8042_flush();
1075 * Disable both KBD and AUX interfaces so they don't get in the way
1078 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1079 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1081 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1082 pr_warn("Can't write CTR while resetting\n");
1085 * Disable MUX mode if present.
1088 if (i8042_mux_present)
1089 i8042_set_mux_mode(false, NULL);
1092 * Reset the controller if requested.
1095 if (i8042_reset == I8042_RESET_ALWAYS ||
1096 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
1097 i8042_controller_selftest();
1101 * Restore the original control register setting.
1104 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1105 pr_warn("Can't restore CTR\n");
1110 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
1111 * when kernel panics. Flashing LEDs is useful for users running X who may
1112 * not see the console and will help distinguishing panics from "real"
1113 * lockups.
1115 * Note that DELAY has a limit of 10ms so we will not get stuck here
1116 * waiting for KBC to free up even if KBD interrupt is off
1119 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1121 static long i8042_panic_blink(int state)
1123 long delay = 0;
1124 char led;
1126 led = (state) ? 0x01 | 0x04 : 0;
1127 while (i8042_read_status() & I8042_STR_IBF)
1128 DELAY;
1129 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1130 i8042_suppress_kbd_ack = 2;
1131 i8042_write_data(0xed); /* set leds */
1132 DELAY;
1133 while (i8042_read_status() & I8042_STR_IBF)
1134 DELAY;
1135 DELAY;
1136 dbg("%02x -> i8042 (panic blink)\n", led);
1137 i8042_write_data(led);
1138 DELAY;
1139 return delay;
1142 #undef DELAY
1144 #ifdef CONFIG_X86
1145 static void i8042_dritek_enable(void)
1147 unsigned char param = 0x90;
1148 int error;
1150 error = i8042_command(&param, 0x1059);
1151 if (error)
1152 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1154 #endif
1156 #ifdef CONFIG_PM
1159 * Here we try to reset everything back to a state we had
1160 * before suspending.
1163 static int i8042_controller_resume(bool s2r_wants_reset)
1165 int error;
1167 error = i8042_controller_check();
1168 if (error)
1169 return error;
1171 if (i8042_reset == I8042_RESET_ALWAYS ||
1172 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
1173 error = i8042_controller_selftest();
1174 if (error)
1175 return error;
1179 * Restore original CTR value and disable all ports
1182 i8042_ctr = i8042_initial_ctr;
1183 if (i8042_direct)
1184 i8042_ctr &= ~I8042_CTR_XLATE;
1185 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1186 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1187 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1188 pr_warn("Can't write CTR to resume, retrying...\n");
1189 msleep(50);
1190 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1191 pr_err("CTR write retry failed\n");
1192 return -EIO;
1197 #ifdef CONFIG_X86
1198 if (i8042_dritek)
1199 i8042_dritek_enable();
1200 #endif
1202 if (i8042_mux_present) {
1203 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1204 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1205 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) {
1206 i8042_enable_aux_port();
1209 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1210 i8042_enable_kbd_port();
1212 i8042_handle_data(0);
1214 return 0;
1218 * Here we try to restore the original BIOS settings to avoid
1219 * upsetting it.
1222 static int i8042_pm_suspend(struct device *dev)
1224 int i;
1226 if (!i8042_forcenorestore && pm_suspend_via_firmware())
1227 i8042_controller_reset(true);
1229 /* Set up serio interrupts for system wakeup. */
1230 for (i = 0; i < I8042_NUM_PORTS; i++) {
1231 struct serio *serio = i8042_ports[i].serio;
1233 if (serio && device_may_wakeup(&serio->dev))
1234 enable_irq_wake(i8042_ports[i].irq);
1237 return 0;
1240 static int i8042_pm_resume_noirq(struct device *dev)
1242 if (i8042_forcenorestore || !pm_resume_via_firmware())
1243 i8042_handle_data(0);
1245 return 0;
1248 static int i8042_pm_resume(struct device *dev)
1250 bool want_reset;
1251 int i;
1253 for (i = 0; i < I8042_NUM_PORTS; i++) {
1254 struct serio *serio = i8042_ports[i].serio;
1256 if (serio && device_may_wakeup(&serio->dev))
1257 disable_irq_wake(i8042_ports[i].irq);
1261 * If platform firmware was not going to be involved in suspend, we did
1262 * not restore the controller state to whatever it had been at boot
1263 * time, so we do not need to do anything.
1265 if (i8042_forcenorestore || !pm_suspend_via_firmware())
1266 return 0;
1269 * We only need to reset the controller if we are resuming after handing
1270 * off control to the platform firmware, otherwise we can simply restore
1271 * the mode.
1273 want_reset = pm_resume_via_firmware();
1275 return i8042_controller_resume(want_reset);
1278 static int i8042_pm_thaw(struct device *dev)
1280 i8042_handle_data(0);
1282 return 0;
1285 static int i8042_pm_reset(struct device *dev)
1287 i8042_controller_reset(false);
1289 return 0;
1292 static int i8042_pm_restore(struct device *dev)
1294 return i8042_controller_resume(false);
1297 static const struct dev_pm_ops i8042_pm_ops = {
1298 .suspend = i8042_pm_suspend,
1299 .resume_noirq = i8042_pm_resume_noirq,
1300 .resume = i8042_pm_resume,
1301 .thaw = i8042_pm_thaw,
1302 .poweroff = i8042_pm_reset,
1303 .restore = i8042_pm_restore,
1306 #endif /* CONFIG_PM */
1309 * We need to reset the 8042 back to original mode on system shutdown,
1310 * because otherwise BIOSes will be confused.
1313 static void i8042_shutdown(struct platform_device *dev)
1315 i8042_controller_reset(false);
1318 static int i8042_create_kbd_port(void)
1320 struct serio *serio;
1321 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1323 serio = kzalloc(sizeof(*serio), GFP_KERNEL);
1324 if (!serio)
1325 return -ENOMEM;
1327 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1328 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1329 serio->start = i8042_start;
1330 serio->stop = i8042_stop;
1331 serio->close = i8042_port_close;
1332 serio->ps2_cmd_mutex = &i8042_mutex;
1333 serio->port_data = port;
1334 serio->dev.parent = &i8042_platform_device->dev;
1335 strscpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1336 strscpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1337 strscpy(serio->firmware_id, i8042_kbd_firmware_id,
1338 sizeof(serio->firmware_id));
1339 set_primary_fwnode(&serio->dev, i8042_kbd_fwnode);
1341 port->serio = serio;
1342 port->irq = I8042_KBD_IRQ;
1344 return 0;
1347 static int i8042_create_aux_port(int idx)
1349 struct serio *serio;
1350 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1351 struct i8042_port *port = &i8042_ports[port_no];
1353 serio = kzalloc(sizeof(*serio), GFP_KERNEL);
1354 if (!serio)
1355 return -ENOMEM;
1357 serio->id.type = SERIO_8042;
1358 serio->write = i8042_aux_write;
1359 serio->start = i8042_start;
1360 serio->stop = i8042_stop;
1361 serio->ps2_cmd_mutex = &i8042_mutex;
1362 serio->port_data = port;
1363 serio->dev.parent = &i8042_platform_device->dev;
1364 if (idx < 0) {
1365 strscpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1366 strscpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1367 strscpy(serio->firmware_id, i8042_aux_firmware_id,
1368 sizeof(serio->firmware_id));
1369 serio->close = i8042_port_close;
1370 } else {
1371 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1372 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1373 strscpy(serio->firmware_id, i8042_aux_firmware_id,
1374 sizeof(serio->firmware_id));
1377 port->serio = serio;
1378 port->mux = idx;
1379 port->irq = I8042_AUX_IRQ;
1381 return 0;
1384 static void i8042_free_kbd_port(void)
1386 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1387 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1390 static void i8042_free_aux_ports(void)
1392 int i;
1394 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1395 kfree(i8042_ports[i].serio);
1396 i8042_ports[i].serio = NULL;
1400 static void i8042_register_ports(void)
1402 int i;
1404 for (i = 0; i < I8042_NUM_PORTS; i++) {
1405 struct serio *serio = i8042_ports[i].serio;
1407 if (!serio)
1408 continue;
1410 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1411 serio->name,
1412 (unsigned long) I8042_DATA_REG,
1413 (unsigned long) I8042_COMMAND_REG,
1414 i8042_ports[i].irq);
1415 serio_register_port(serio);
1419 static void i8042_unregister_ports(void)
1421 int i;
1423 for (i = 0; i < I8042_NUM_PORTS; i++) {
1424 if (i8042_ports[i].serio) {
1425 serio_unregister_port(i8042_ports[i].serio);
1426 i8042_ports[i].serio = NULL;
1431 static void i8042_free_irqs(void)
1433 if (i8042_aux_irq_registered)
1434 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1435 if (i8042_kbd_irq_registered)
1436 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1438 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1441 static int i8042_setup_aux(void)
1443 int (*aux_enable)(void);
1444 int error;
1445 int i;
1447 if (i8042_check_aux())
1448 return -ENODEV;
1450 if (i8042_nomux || i8042_check_mux()) {
1451 error = i8042_create_aux_port(-1);
1452 if (error)
1453 goto err_free_ports;
1454 aux_enable = i8042_enable_aux_port;
1455 } else {
1456 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1457 error = i8042_create_aux_port(i);
1458 if (error)
1459 goto err_free_ports;
1461 aux_enable = i8042_enable_mux_ports;
1464 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1465 "i8042", i8042_platform_device);
1466 if (error)
1467 goto err_free_ports;
1469 error = aux_enable();
1470 if (error)
1471 goto err_free_irq;
1473 i8042_aux_irq_registered = true;
1474 return 0;
1476 err_free_irq:
1477 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1478 err_free_ports:
1479 i8042_free_aux_ports();
1480 return error;
1483 static int i8042_setup_kbd(void)
1485 int error;
1487 error = i8042_create_kbd_port();
1488 if (error)
1489 return error;
1491 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1492 "i8042", i8042_platform_device);
1493 if (error)
1494 goto err_free_port;
1496 error = i8042_enable_kbd_port();
1497 if (error)
1498 goto err_free_irq;
1500 i8042_kbd_irq_registered = true;
1501 return 0;
1503 err_free_irq:
1504 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1505 err_free_port:
1506 i8042_free_kbd_port();
1507 return error;
1510 static int i8042_kbd_bind_notifier(struct notifier_block *nb,
1511 unsigned long action, void *data)
1513 struct device *dev = data;
1514 struct serio *serio = to_serio_port(dev);
1515 struct i8042_port *port = serio->port_data;
1517 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio)
1518 return 0;
1520 switch (action) {
1521 case BUS_NOTIFY_BOUND_DRIVER:
1522 port->driver_bound = true;
1523 break;
1525 case BUS_NOTIFY_UNBIND_DRIVER:
1526 port->driver_bound = false;
1527 break;
1530 return 0;
1533 static int i8042_probe(struct platform_device *dev)
1535 int error;
1537 if (i8042_reset == I8042_RESET_ALWAYS) {
1538 error = i8042_controller_selftest();
1539 if (error)
1540 return error;
1543 error = i8042_controller_init();
1544 if (error)
1545 return error;
1547 #ifdef CONFIG_X86
1548 if (i8042_dritek)
1549 i8042_dritek_enable();
1550 #endif
1552 if (!i8042_noaux) {
1553 error = i8042_setup_aux();
1554 if (error && error != -ENODEV && error != -EBUSY)
1555 goto out_fail;
1558 if (!i8042_nokbd) {
1559 error = i8042_setup_kbd();
1560 if (error)
1561 goto out_fail;
1564 * Ok, everything is ready, let's register all serio ports
1566 i8042_register_ports();
1568 return 0;
1570 out_fail:
1571 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1572 i8042_free_irqs();
1573 i8042_controller_reset(false);
1575 return error;
1578 static void i8042_remove(struct platform_device *dev)
1580 i8042_unregister_ports();
1581 i8042_free_irqs();
1582 i8042_controller_reset(false);
1585 static struct platform_driver i8042_driver = {
1586 .driver = {
1587 .name = "i8042",
1588 #ifdef CONFIG_PM
1589 .pm = &i8042_pm_ops,
1590 #endif
1592 .probe = i8042_probe,
1593 .remove = i8042_remove,
1594 .shutdown = i8042_shutdown,
1597 static struct notifier_block i8042_kbd_bind_notifier_block = {
1598 .notifier_call = i8042_kbd_bind_notifier,
1601 static int __init i8042_init(void)
1603 int err;
1605 dbg_init();
1607 err = i8042_platform_init();
1608 if (err)
1609 return (err == -ENODEV) ? 0 : err;
1611 err = i8042_controller_check();
1612 if (err)
1613 goto err_platform_exit;
1615 /* Set this before creating the dev to allow i8042_command to work right away */
1616 i8042_present = true;
1618 err = platform_driver_register(&i8042_driver);
1619 if (err)
1620 goto err_platform_exit;
1622 i8042_platform_device = platform_device_alloc("i8042", -1);
1623 if (!i8042_platform_device) {
1624 err = -ENOMEM;
1625 goto err_unregister_driver;
1628 err = platform_device_add(i8042_platform_device);
1629 if (err)
1630 goto err_free_device;
1632 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
1633 panic_blink = i8042_panic_blink;
1635 return 0;
1637 err_free_device:
1638 platform_device_put(i8042_platform_device);
1639 err_unregister_driver:
1640 platform_driver_unregister(&i8042_driver);
1641 err_platform_exit:
1642 i8042_platform_exit();
1643 return err;
1646 static void __exit i8042_exit(void)
1648 if (!i8042_present)
1649 return;
1651 platform_device_unregister(i8042_platform_device);
1652 platform_driver_unregister(&i8042_driver);
1653 i8042_platform_exit();
1655 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
1656 panic_blink = NULL;
1659 module_init(i8042_init);
1660 module_exit(i8042_exit);