drivers/input/serio/sun4i-ps2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *      Driver for Allwinner A10 PS2 host controller
   4  *
   5  *      Author: Vishnu Patekar <vishnupatekar0510@gmail.com>
   6  *              Aaron.maoye <leafy.myeh@newbietech.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/serio.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/errno.h>
  13 #include <linux/slab.h>
  14 #include <linux/io.h>
  15 #include <linux/clk.h>
  16 #include <linux/mod_devicetable.h>
  17 #include <linux/platform_device.h>
  18
  19 #define DRIVER_NAME             "sun4i-ps2"
  20
  21 /* register offset definitions */
  22 #define PS2_REG_GCTL            0x00    /* PS2 Module Global Control Reg */
  23 #define PS2_REG_DATA            0x04    /* PS2 Module Data Reg          */
  24 #define PS2_REG_LCTL            0x08    /* PS2 Module Line Control Reg */
  25 #define PS2_REG_LSTS            0x0C    /* PS2 Module Line Status Reg   */
  26 #define PS2_REG_FCTL            0x10    /* PS2 Module FIFO Control Reg */
  27 #define PS2_REG_FSTS            0x14    /* PS2 Module FIFO Status Reg   */
  28 #define PS2_REG_CLKDR           0x18    /* PS2 Module Clock Divider Reg*/
  29
  30 /*  PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
  31 #define PS2_GCTL_INTFLAG        BIT(4)
  32 #define PS2_GCTL_INTEN          BIT(3)
  33 #define PS2_GCTL_RESET          BIT(2)
  34 #define PS2_GCTL_MASTER         BIT(1)
  35 #define PS2_GCTL_BUSEN          BIT(0)
  36
  37 /* PS2 LINE CONTROL REGISTER */
  38 #define PS2_LCTL_NOACK          BIT(18)
  39 #define PS2_LCTL_TXDTOEN        BIT(8)
  40 #define PS2_LCTL_STOPERREN      BIT(3)
  41 #define PS2_LCTL_ACKERREN       BIT(2)
  42 #define PS2_LCTL_PARERREN       BIT(1)
  43 #define PS2_LCTL_RXDTOEN        BIT(0)
  44
  45 /* PS2 LINE STATUS REGISTER */
  46 #define PS2_LSTS_TXTDO          BIT(8)
  47 #define PS2_LSTS_STOPERR        BIT(3)
  48 #define PS2_LSTS_ACKERR         BIT(2)
  49 #define PS2_LSTS_PARERR         BIT(1)
  50 #define PS2_LSTS_RXTDO          BIT(0)
  51
  52 #define PS2_LINE_ERROR_BIT \
  53         (PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
  54         PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
  55
  56 /* PS2 FIFO CONTROL REGISTER */
  57 #define PS2_FCTL_TXRST          BIT(17)
  58 #define PS2_FCTL_RXRST          BIT(16)
  59 #define PS2_FCTL_TXUFIEN        BIT(10)
  60 #define PS2_FCTL_TXOFIEN        BIT(9)
  61 #define PS2_FCTL_TXRDYIEN       BIT(8)
  62 #define PS2_FCTL_RXUFIEN        BIT(2)
  63 #define PS2_FCTL_RXOFIEN        BIT(1)
  64 #define PS2_FCTL_RXRDYIEN       BIT(0)
  65
  66 /* PS2 FIFO STATUS REGISTER */
  67 #define PS2_FSTS_TXUF           BIT(10)
  68 #define PS2_FSTS_TXOF           BIT(9)
  69 #define PS2_FSTS_TXRDY          BIT(8)
  70 #define PS2_FSTS_RXUF           BIT(2)
  71 #define PS2_FSTS_RXOF           BIT(1)
  72 #define PS2_FSTS_RXRDY          BIT(0)
  73
  74 #define PS2_FIFO_ERROR_BIT \
  75         (PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
  76
  77 #define PS2_SAMPLE_CLK          1000000
  78 #define PS2_SCLK                125000
  79
  80 struct sun4i_ps2data {
  81         struct serio *serio;
  82         struct device *dev;
  83
  84         /* IO mapping base */
  85         void __iomem    *reg_base;
  86
  87         /* clock management */
  88         struct clk      *clk;
  89
  90         /* irq */
  91         spinlock_t      lock;
  92         int             irq;
  93 };
  94
  95 static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id)
  96 {
  97         struct sun4i_ps2data *drvdata = dev_id;
  98         u32 intr_status;
  99         u32 fifo_status;
 100         unsigned char byte;
 101         unsigned int rxflags = 0;
 102         u32 rval;
 103
 104         guard(spinlock)(&drvdata->lock);
 105
 106         /* Get the PS/2 interrupts and clear them */
 107         intr_status  = readl(drvdata->reg_base + PS2_REG_LSTS);
 108         fifo_status  = readl(drvdata->reg_base + PS2_REG_FSTS);
 109
 110         /* Check line status register */
 111         if (intr_status & PS2_LINE_ERROR_BIT) {
 112                 rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0;
 113                 rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0;
 114                 rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0;
 115
 116                 rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR |
 117                         PS2_LSTS_PARERR | PS2_LSTS_RXTDO;
 118                 writel(rval, drvdata->reg_base + PS2_REG_LSTS);
 119         }
 120
 121         /* Check FIFO status register */
 122         if (fifo_status & PS2_FIFO_ERROR_BIT) {
 123                 rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY |
 124                         PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY;
 125                 writel(rval, drvdata->reg_base + PS2_REG_FSTS);
 126         }
 127
 128         rval = (fifo_status >> 16) & 0x3;
 129         while (rval--) {
 130                 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
 131                 serio_interrupt(drvdata->serio, byte, rxflags);
 132         }
 133
 134         writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
 135         writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
 136
 137         return IRQ_HANDLED;
 138 }
 139
 140 static int sun4i_ps2_open(struct serio *serio)
 141 {
 142         struct sun4i_ps2data *drvdata = serio->port_data;
 143         u32 src_clk = 0;
 144         u32 clk_scdf;
 145         u32 clk_pcdf;
 146         u32 rval;
 147
 148         /* Set line control and enable interrupt */
 149         rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN
 150                 | PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN;
 151         writel(rval, drvdata->reg_base + PS2_REG_LCTL);
 152
 153         /* Reset FIFO */
 154         rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN
 155                 | PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN
 156                 | PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN;
 157
 158         writel(rval, drvdata->reg_base + PS2_REG_FCTL);
 159
 160         src_clk = clk_get_rate(drvdata->clk);
 161         /* Set clock divider register */
 162         clk_scdf = src_clk / PS2_SAMPLE_CLK - 1;
 163         clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1;
 164         rval = (clk_scdf << 8) | clk_pcdf;
 165         writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
 166
 167         /* Set global control register */
 168         rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER
 169                 | PS2_GCTL_BUSEN;
 170
 171         guard(spinlock_irqsave)(&drvdata->lock);
 172         writel(rval, drvdata->reg_base + PS2_REG_GCTL);
 173
 174         return 0;
 175 }
 176
 177 static void sun4i_ps2_close(struct serio *serio)
 178 {
 179         struct sun4i_ps2data *drvdata = serio->port_data;
 180         u32 rval;
 181
 182         /* Shut off the interrupt */
 183         rval = readl(drvdata->reg_base + PS2_REG_GCTL);
 184         writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
 185
 186         synchronize_irq(drvdata->irq);
 187 }
 188
 189 static int sun4i_ps2_write(struct serio *serio, unsigned char val)
 190 {
 191         unsigned long expire = jiffies + msecs_to_jiffies(10000);
 192         struct sun4i_ps2data *drvdata = serio->port_data;
 193
 194         do {
 195                 if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) {
 196                         writel(val, drvdata->reg_base + PS2_REG_DATA);
 197                         return 0;
 198                 }
 199         } while (time_before(jiffies, expire));
 200
 201         return SERIO_TIMEOUT;
 202 }
 203
 204 static int sun4i_ps2_probe(struct platform_device *pdev)
 205 {
 206         struct resource *res; /* IO mem resources */
 207         struct sun4i_ps2data *drvdata;
 208         struct serio *serio;
 209         struct device *dev = &pdev->dev;
 210         int error;
 211
 212         drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
 213         serio = kzalloc(sizeof(*serio), GFP_KERNEL);
 214         if (!drvdata || !serio) {
 215                 error = -ENOMEM;
 216                 goto err_free_mem;
 217         }
 218
 219         spin_lock_init(&drvdata->lock);
 220
 221         /* IO */
 222         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 223         if (!res) {
 224                 dev_err(dev, "failed to locate registers\n");
 225                 error = -ENXIO;
 226                 goto err_free_mem;
 227         }
 228
 229         drvdata->reg_base = ioremap(res->start, resource_size(res));
 230         if (!drvdata->reg_base) {
 231                 dev_err(dev, "failed to map registers\n");
 232                 error = -ENOMEM;
 233                 goto err_free_mem;
 234         }
 235
 236         drvdata->clk = clk_get(dev, NULL);
 237         if (IS_ERR(drvdata->clk)) {
 238                 error = PTR_ERR(drvdata->clk);
 239                 dev_err(dev, "couldn't get clock %d\n", error);
 240                 goto err_ioremap;
 241         }
 242
 243         error = clk_prepare_enable(drvdata->clk);
 244         if (error) {
 245                 dev_err(dev, "failed to enable clock %d\n", error);
 246                 goto err_clk;
 247         }
 248
 249         serio->id.type = SERIO_8042;
 250         serio->write = sun4i_ps2_write;
 251         serio->open = sun4i_ps2_open;
 252         serio->close = sun4i_ps2_close;
 253         serio->port_data = drvdata;
 254         serio->dev.parent = dev;
 255         strscpy(serio->name, dev_name(dev), sizeof(serio->name));
 256         strscpy(serio->phys, dev_name(dev), sizeof(serio->phys));
 257
 258         /* shutoff interrupt */
 259         writel(0, drvdata->reg_base + PS2_REG_GCTL);
 260
 261         /* Get IRQ for the device */
 262         drvdata->irq = platform_get_irq(pdev, 0);
 263         if (drvdata->irq < 0) {
 264                 error = drvdata->irq;
 265                 goto err_disable_clk;
 266         }
 267
 268         drvdata->serio = serio;
 269         drvdata->dev = dev;
 270
 271         error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0,
 272                             DRIVER_NAME, drvdata);
 273         if (error) {
 274                 dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n",
 275                         drvdata->irq, error);
 276                 goto err_disable_clk;
 277         }
 278
 279         serio_register_port(serio);
 280         platform_set_drvdata(pdev, drvdata);
 281
 282         return 0;       /* success */
 283
 284 err_disable_clk:
 285         clk_disable_unprepare(drvdata->clk);
 286 err_clk:
 287         clk_put(drvdata->clk);
 288 err_ioremap:
 289         iounmap(drvdata->reg_base);
 290 err_free_mem:
 291         kfree(serio);
 292         kfree(drvdata);
 293         return error;
 294 }
 295
 296 static void sun4i_ps2_remove(struct platform_device *pdev)
 297 {
 298         struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev);
 299
 300         serio_unregister_port(drvdata->serio);
 301
 302         free_irq(drvdata->irq, drvdata);
 303
 304         clk_disable_unprepare(drvdata->clk);
 305         clk_put(drvdata->clk);
 306
 307         iounmap(drvdata->reg_base);
 308
 309         kfree(drvdata);
 310 }
 311
 312 static const struct of_device_id sun4i_ps2_match[] = {
 313         { .compatible = "allwinner,sun4i-a10-ps2", },
 314         { },
 315 };
 316
 317 MODULE_DEVICE_TABLE(of, sun4i_ps2_match);
 318
 319 static struct platform_driver sun4i_ps2_driver = {
 320         .probe          = sun4i_ps2_probe,
 321         .remove         = sun4i_ps2_remove,
 322         .driver = {
 323                 .name = DRIVER_NAME,
 324                 .of_match_table = sun4i_ps2_match,
 325         },
 326 };
 327 module_platform_driver(sun4i_ps2_driver);
 328
 329 MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
 330 MODULE_AUTHOR("Aaron.maoye <leafy.myeh@newbietech.com>");
 331 MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver");
 332 MODULE_LICENSE("GPL v2");