drivers/irqchip/irq-bcm2836.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
   4  *
   5  * Copyright 2015 Broadcom
   6  */
   7
   8 #include <linux/cpu.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_irq.h>
  11 #include <linux/irqchip.h>
  12 #include <linux/irqdomain.h>
  13 #include <linux/irqchip/chained_irq.h>
  14 #include <linux/irqchip/irq-bcm2836.h>
  15
  16 #include <asm/exception.h>
  17
  18 struct bcm2836_arm_irqchip_intc {
  19         struct irq_domain *domain;
  20         void __iomem *base;
  21 };
  22
  23 static struct bcm2836_arm_irqchip_intc intc  __read_mostly;
  24
  25 static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
  26                                                  unsigned int bit,
  27                                                  int cpu)
  28 {
  29         void __iomem *reg = intc.base + reg_offset + 4 * cpu;
  30
  31         writel(readl(reg) & ~BIT(bit), reg);
  32 }
  33
  34 static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
  35                                                    unsigned int bit,
  36                                                  int cpu)
  37 {
  38         void __iomem *reg = intc.base + reg_offset + 4 * cpu;
  39
  40         writel(readl(reg) | BIT(bit), reg);
  41 }
  42
  43 static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
  44 {
  45         bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
  46                                              d->hwirq - LOCAL_IRQ_CNTPSIRQ,
  47                                              smp_processor_id());
  48 }
  49
  50 static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
  51 {
  52         bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
  53                                                d->hwirq - LOCAL_IRQ_CNTPSIRQ,
  54                                                smp_processor_id());
  55 }
  56
  57 static struct irq_chip bcm2836_arm_irqchip_timer = {
  58         .name           = "bcm2836-timer",
  59         .irq_mask       = bcm2836_arm_irqchip_mask_timer_irq,
  60         .irq_unmask     = bcm2836_arm_irqchip_unmask_timer_irq,
  61         .flags          = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
  62 };
  63
  64 static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
  65 {
  66         writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
  67 }
  68
  69 static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
  70 {
  71         writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
  72 }
  73
  74 static struct irq_chip bcm2836_arm_irqchip_pmu = {
  75         .name           = "bcm2836-pmu",
  76         .irq_mask       = bcm2836_arm_irqchip_mask_pmu_irq,
  77         .irq_unmask     = bcm2836_arm_irqchip_unmask_pmu_irq,
  78         .flags          = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
  79 };
  80
  81 static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
  82 {
  83 }
  84
  85 static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
  86 {
  87 }
  88
  89 static struct irq_chip bcm2836_arm_irqchip_gpu = {
  90         .name           = "bcm2836-gpu",
  91         .irq_mask       = bcm2836_arm_irqchip_mask_gpu_irq,
  92         .irq_unmask     = bcm2836_arm_irqchip_unmask_gpu_irq,
  93         .flags          = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
  94 };
  95
  96 static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
  97 {
  98 }
  99
 100 static struct irq_chip bcm2836_arm_irqchip_dummy = {
 101         .name           = "bcm2836-dummy",
 102         .irq_eoi        = bcm2836_arm_irqchip_dummy_op,
 103 };
 104
 105 static int bcm2836_map(struct irq_domain *d, unsigned int irq,
 106                        irq_hw_number_t hw)
 107 {
 108         struct irq_chip *chip;
 109
 110         switch (hw) {
 111         case LOCAL_IRQ_MAILBOX0:
 112                 chip = &bcm2836_arm_irqchip_dummy;
 113                 break;
 114         case LOCAL_IRQ_CNTPSIRQ:
 115         case LOCAL_IRQ_CNTPNSIRQ:
 116         case LOCAL_IRQ_CNTHPIRQ:
 117         case LOCAL_IRQ_CNTVIRQ:
 118                 chip = &bcm2836_arm_irqchip_timer;
 119                 break;
 120         case LOCAL_IRQ_GPU_FAST:
 121                 chip = &bcm2836_arm_irqchip_gpu;
 122                 break;
 123         case LOCAL_IRQ_PMU_FAST:
 124                 chip = &bcm2836_arm_irqchip_pmu;
 125                 break;
 126         default:
 127                 pr_warn_once("Unexpected hw irq: %lu\n", hw);
 128                 return -EINVAL;
 129         }
 130
 131         irq_set_percpu_devid(irq);
 132         irq_domain_set_info(d, irq, hw, chip, d->host_data,
 133                             handle_percpu_devid_irq, NULL, NULL);
 134         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 135
 136         return 0;
 137 }
 138
 139 static void
 140 __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
 141 {
 142         int cpu = smp_processor_id();
 143         u32 stat;
 144
 145         stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
 146         if (stat) {
 147                 u32 hwirq = ffs(stat) - 1;
 148
 149                 generic_handle_domain_irq(intc.domain, hwirq);
 150         }
 151 }
 152
 153 #ifdef CONFIG_SMP
 154 static struct irq_domain *ipi_domain;
 155
 156 static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
 157 {
 158         struct irq_chip *chip = irq_desc_get_chip(desc);
 159         int cpu = smp_processor_id();
 160         u32 mbox_val;
 161
 162         chained_irq_enter(chip, desc);
 163
 164         mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
 165         if (mbox_val) {
 166                 int hwirq = ffs(mbox_val) - 1;
 167                 generic_handle_domain_irq(ipi_domain, hwirq);
 168         }
 169
 170         chained_irq_exit(chip, desc);
 171 }
 172
 173 static void bcm2836_arm_irqchip_ipi_ack(struct irq_data *d)
 174 {
 175         int cpu = smp_processor_id();
 176
 177         writel_relaxed(BIT(d->hwirq),
 178                        intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
 179 }
 180
 181 static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
 182                                               const struct cpumask *mask)
 183 {
 184         int cpu;
 185         void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
 186
 187         /*
 188          * Ensure that stores to normal memory are visible to the
 189          * other CPUs before issuing the IPI.
 190          */
 191         smp_wmb();
 192
 193         for_each_cpu(cpu, mask)
 194                 writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
 195 }
 196
 197 static struct irq_chip bcm2836_arm_irqchip_ipi = {
 198         .name           = "IPI",
 199         .irq_mask       = bcm2836_arm_irqchip_dummy_op,
 200         .irq_unmask     = bcm2836_arm_irqchip_dummy_op,
 201         .irq_ack        = bcm2836_arm_irqchip_ipi_ack,
 202         .ipi_send_mask  = bcm2836_arm_irqchip_ipi_send_mask,
 203 };
 204
 205 static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
 206                                          unsigned int virq,
 207                                          unsigned int nr_irqs, void *args)
 208 {
 209         int i;
 210
 211         for (i = 0; i < nr_irqs; i++) {
 212                 irq_set_percpu_devid(virq + i);
 213                 irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
 214                                     d->host_data,
 215                                     handle_percpu_devid_irq,
 216                                     NULL, NULL);
 217         }
 218
 219         return 0;
 220 }
 221
 222 static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
 223                                          unsigned int virq,
 224                                          unsigned int nr_irqs)
 225 {
 226         /* Not freeing IPIs */
 227 }
 228
 229 static const struct irq_domain_ops ipi_domain_ops = {
 230         .alloc  = bcm2836_arm_irqchip_ipi_alloc,
 231         .free   = bcm2836_arm_irqchip_ipi_free,
 232 };
 233
 234 static int bcm2836_cpu_starting(unsigned int cpu)
 235 {
 236         bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
 237                                                cpu);
 238         return 0;
 239 }
 240
 241 static int bcm2836_cpu_dying(unsigned int cpu)
 242 {
 243         bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
 244                                              cpu);
 245         return 0;
 246 }
 247
 248 #define BITS_PER_MBOX   32
 249
 250 static void __init bcm2836_arm_irqchip_smp_init(void)
 251 {
 252         struct irq_fwspec ipi_fwspec = {
 253                 .fwnode         = intc.domain->fwnode,
 254                 .param_count    = 1,
 255                 .param          = {
 256                         [0]     = LOCAL_IRQ_MAILBOX0,
 257                 },
 258         };
 259         int base_ipi, mux_irq;
 260
 261         mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
 262         if (WARN_ON(mux_irq <= 0))
 263                 return;
 264
 265         ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
 266                                               BITS_PER_MBOX, &ipi_domain_ops,
 267                                               NULL);
 268         if (WARN_ON(!ipi_domain))
 269                 return;
 270
 271         ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
 272         irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
 273
 274         base_ipi = irq_domain_alloc_irqs(ipi_domain, BITS_PER_MBOX, NUMA_NO_NODE, NULL);
 275         if (WARN_ON(!base_ipi))
 276                 return;
 277
 278         set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
 279
 280         irq_set_chained_handler_and_data(mux_irq,
 281                                          bcm2836_arm_irqchip_handle_ipi, NULL);
 282
 283         /* Unmask IPIs to the boot CPU. */
 284         cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
 285                           "irqchip/bcm2836:starting", bcm2836_cpu_starting,
 286                           bcm2836_cpu_dying);
 287 }
 288 #else
 289 #define bcm2836_arm_irqchip_smp_init()  do { } while(0)
 290 #endif
 291
 292 static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
 293         .xlate = irq_domain_xlate_onetwocell,
 294         .map = bcm2836_map,
 295 };
 296
 297 /*
 298  * The LOCAL_IRQ_CNT* timer firings are based off of the external
 299  * oscillator with some scaling.  The firmware sets up CNTFRQ to
 300  * report 19.2Mhz, but doesn't set up the scaling registers.
 301  */
 302 static void bcm2835_init_local_timer_frequency(void)
 303 {
 304         /*
 305          * Set the timer to source from the 19.2Mhz crystal clock (bit
 306          * 8 unset), and only increment by 1 instead of 2 (bit 9
 307          * unset).
 308          */
 309         writel(0, intc.base + LOCAL_CONTROL);
 310
 311         /*
 312          * Set the timer prescaler to 1:1 (timer freq = input freq *
 313          * 2**31 / prescaler)
 314          */
 315         writel(0x80000000, intc.base + LOCAL_PRESCALER);
 316 }
 317
 318 static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
 319                                                       struct device_node *parent)
 320 {
 321         intc.base = of_iomap(node, 0);
 322         if (!intc.base) {
 323                 panic("%pOF: unable to map local interrupt registers\n", node);
 324         }
 325
 326         bcm2835_init_local_timer_frequency();
 327
 328         intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
 329                                             &bcm2836_arm_irqchip_intc_ops,
 330                                             NULL);
 331         if (!intc.domain)
 332                 panic("%pOF: unable to create IRQ domain\n", node);
 333
 334         irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
 335
 336         bcm2836_arm_irqchip_smp_init();
 337
 338         set_handle_irq(bcm2836_arm_irqchip_handle_irq);
 339         return 0;
 340 }
 341
 342 IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
 343                 bcm2836_arm_irqchip_l1_intc_of_init);