drivers/irqchip/irq-gic-v3-mbi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #define pr_fmt(fmt) "GICv3: " fmt
   8
   9 #include <linux/iommu.h>
  10 #include <linux/irq.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/kernel.h>
  13 #include <linux/msi.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_pci.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <linux/irqchip/arm-gic-v3.h>
  20
  21 #include "irq-msi-lib.h"
  22
  23 struct mbi_range {
  24         u32                     spi_start;
  25         u32                     nr_spis;
  26         unsigned long           *bm;
  27 };
  28
  29 static DEFINE_MUTEX(mbi_lock);
  30 static phys_addr_t              mbi_phys_base;
  31 static struct mbi_range         *mbi_ranges;
  32 static unsigned int             mbi_range_nr;
  33
  34 static struct irq_chip mbi_irq_chip = {
  35         .name                   = "MBI",
  36         .irq_mask               = irq_chip_mask_parent,
  37         .irq_unmask             = irq_chip_unmask_parent,
  38         .irq_eoi                = irq_chip_eoi_parent,
  39         .irq_set_type           = irq_chip_set_type_parent,
  40         .irq_set_affinity       = irq_chip_set_affinity_parent,
  41 };
  42
  43 static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
  44                                        unsigned int virq,
  45                                        irq_hw_number_t hwirq)
  46 {
  47         struct irq_fwspec fwspec;
  48         struct irq_data *d;
  49         int err;
  50
  51         /*
  52          * Using ACPI? There is no MBI support in the spec, you
  53          * shouldn't even be here.
  54          */
  55         if (!is_of_node(domain->parent->fwnode))
  56                 return -EINVAL;
  57
  58         /*
  59          * Let's default to edge. This is consistent with traditional
  60          * MSIs, and systems requiring level signaling will just
  61          * enforce the trigger on their own.
  62          */
  63         fwspec.fwnode = domain->parent->fwnode;
  64         fwspec.param_count = 3;
  65         fwspec.param[0] = 0;
  66         fwspec.param[1] = hwirq - 32;
  67         fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
  68
  69         err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
  70         if (err)
  71                 return err;
  72
  73         d = irq_domain_get_irq_data(domain->parent, virq);
  74         return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
  75 }
  76
  77 static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq,
  78                          int nr_irqs)
  79 {
  80         mutex_lock(&mbi_lock);
  81         bitmap_release_region(mbi->bm, hwirq - mbi->spi_start,
  82                               get_count_order(nr_irqs));
  83         mutex_unlock(&mbi_lock);
  84 }
  85
  86 static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  87                                    unsigned int nr_irqs, void *args)
  88 {
  89         msi_alloc_info_t *info = args;
  90         struct mbi_range *mbi = NULL;
  91         int hwirq, offset, i, err = 0;
  92
  93         mutex_lock(&mbi_lock);
  94         for (i = 0; i < mbi_range_nr; i++) {
  95                 offset = bitmap_find_free_region(mbi_ranges[i].bm,
  96                                                  mbi_ranges[i].nr_spis,
  97                                                  get_count_order(nr_irqs));
  98                 if (offset >= 0) {
  99                         mbi = &mbi_ranges[i];
 100                         break;
 101                 }
 102         }
 103         mutex_unlock(&mbi_lock);
 104
 105         if (!mbi)
 106                 return -ENOSPC;
 107
 108         hwirq = mbi->spi_start + offset;
 109
 110         err = iommu_dma_prepare_msi(info->desc,
 111                                     mbi_phys_base + GICD_SETSPI_NSR);
 112         if (err)
 113                 return err;
 114
 115         for (i = 0; i < nr_irqs; i++) {
 116                 err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
 117                 if (err)
 118                         goto fail;
 119
 120                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 121                                               &mbi_irq_chip, mbi);
 122         }
 123
 124         return 0;
 125
 126 fail:
 127         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 128         mbi_free_msi(mbi, hwirq, nr_irqs);
 129         return err;
 130 }
 131
 132 static void mbi_irq_domain_free(struct irq_domain *domain,
 133                                 unsigned int virq, unsigned int nr_irqs)
 134 {
 135         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 136         struct mbi_range *mbi = irq_data_get_irq_chip_data(d);
 137
 138         mbi_free_msi(mbi, d->hwirq, nr_irqs);
 139         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 140 }
 141
 142 static const struct irq_domain_ops mbi_domain_ops = {
 143         .select                 = msi_lib_irq_domain_select,
 144         .alloc                  = mbi_irq_domain_alloc,
 145         .free                   = mbi_irq_domain_free,
 146 };
 147
 148 static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 149 {
 150         msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
 151         msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
 152         msg[0].data = data->parent_data->hwirq;
 153
 154         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
 155 }
 156
 157 static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg)
 158 {
 159         mbi_compose_msi_msg(data, msg);
 160
 161         msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
 162         msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
 163         msg[1].data = data->parent_data->hwirq;
 164
 165         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]);
 166 }
 167
 168 static bool mbi_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
 169                                   struct irq_domain *real_parent, struct msi_domain_info *info)
 170 {
 171         if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
 172                 return false;
 173
 174         switch (info->bus_token) {
 175         case DOMAIN_BUS_PCI_DEVICE_MSI:
 176         case DOMAIN_BUS_PCI_DEVICE_MSIX:
 177                 info->chip->irq_compose_msi_msg = mbi_compose_msi_msg;
 178                 return true;
 179
 180         case DOMAIN_BUS_DEVICE_MSI:
 181                 info->chip->irq_compose_msi_msg = mbi_compose_mbi_msg;
 182                 info->chip->irq_set_type = irq_chip_set_type_parent;
 183                 info->chip->flags |= IRQCHIP_SUPPORTS_LEVEL_MSI;
 184                 info->flags |= MSI_FLAG_LEVEL_CAPABLE;
 185                 return true;
 186
 187         default:
 188                 WARN_ON_ONCE(1);
 189                 return false;
 190         }
 191 }
 192
 193 #define MBI_MSI_FLAGS_REQUIRED  (MSI_FLAG_USE_DEF_DOM_OPS |     \
 194                                  MSI_FLAG_USE_DEF_CHIP_OPS |    \
 195                                  MSI_FLAG_PCI_MSI_MASK_PARENT)
 196
 197 #define MBI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK |       \
 198                                  MSI_FLAG_PCI_MSIX      |       \
 199                                  MSI_FLAG_MULTI_PCI_MSI)
 200
 201 static const struct msi_parent_ops gic_v3_mbi_msi_parent_ops = {
 202         .supported_flags        = MBI_MSI_FLAGS_SUPPORTED,
 203         .required_flags         = MBI_MSI_FLAGS_REQUIRED,
 204         .bus_select_token       = DOMAIN_BUS_NEXUS,
 205         .bus_select_mask        = MATCH_PCI_MSI | MATCH_PLATFORM_MSI,
 206         .prefix                 = "MBI-",
 207         .init_dev_msi_info      = mbi_init_dev_msi_info,
 208 };
 209
 210 static int mbi_allocate_domain(struct irq_domain *parent)
 211 {
 212         struct irq_domain *nexus_domain;
 213
 214         nexus_domain = irq_domain_create_hierarchy(parent, 0, 0, parent->fwnode,
 215                                                    &mbi_domain_ops, NULL);
 216         if (!nexus_domain)
 217                 return -ENOMEM;
 218
 219         irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS);
 220         nexus_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
 221         nexus_domain->msi_parent_ops = &gic_v3_mbi_msi_parent_ops;
 222         return 0;
 223 }
 224
 225 int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
 226 {
 227         struct device_node *np;
 228         const __be32 *reg;
 229         int ret, n;
 230
 231         np = to_of_node(fwnode);
 232
 233         if (!of_property_read_bool(np, "msi-controller"))
 234                 return 0;
 235
 236         n = of_property_count_elems_of_size(np, "mbi-ranges", sizeof(u32));
 237         if (n <= 0 || n % 2)
 238                 return -EINVAL;
 239
 240         mbi_range_nr = n / 2;
 241         mbi_ranges = kcalloc(mbi_range_nr, sizeof(*mbi_ranges), GFP_KERNEL);
 242         if (!mbi_ranges)
 243                 return -ENOMEM;
 244
 245         for (n = 0; n < mbi_range_nr; n++) {
 246                 ret = of_property_read_u32_index(np, "mbi-ranges", n * 2,
 247                                                  &mbi_ranges[n].spi_start);
 248                 if (ret)
 249                         goto err_free_mbi;
 250                 ret = of_property_read_u32_index(np, "mbi-ranges", n * 2 + 1,
 251                                                  &mbi_ranges[n].nr_spis);
 252                 if (ret)
 253                         goto err_free_mbi;
 254
 255                 mbi_ranges[n].bm = bitmap_zalloc(mbi_ranges[n].nr_spis, GFP_KERNEL);
 256                 if (!mbi_ranges[n].bm) {
 257                         ret = -ENOMEM;
 258                         goto err_free_mbi;
 259                 }
 260                 pr_info("MBI range [%d:%d]\n", mbi_ranges[n].spi_start,
 261                         mbi_ranges[n].spi_start + mbi_ranges[n].nr_spis - 1);
 262         }
 263
 264         reg = of_get_property(np, "mbi-alias", NULL);
 265         if (reg) {
 266                 mbi_phys_base = of_translate_address(np, reg);
 267                 if (mbi_phys_base == (phys_addr_t)OF_BAD_ADDR) {
 268                         ret = -ENXIO;
 269                         goto err_free_mbi;
 270                 }
 271         } else {
 272                 struct resource res;
 273
 274                 if (of_address_to_resource(np, 0, &res)) {
 275                         ret = -ENXIO;
 276                         goto err_free_mbi;
 277                 }
 278
 279                 mbi_phys_base = res.start;
 280         }
 281
 282         pr_info("Using MBI frame %pa\n", &mbi_phys_base);
 283
 284         ret = mbi_allocate_domain(parent);
 285         if (ret)
 286                 goto err_free_mbi;
 287
 288         return 0;
 289
 290 err_free_mbi:
 291         if (mbi_ranges) {
 292                 for (n = 0; n < mbi_range_nr; n++)
 293                         bitmap_free(mbi_ranges[n].bm);
 294                 kfree(mbi_ranges);
 295         }
 296
 297         return ret;
 298 }