drivers/irqchip/irq-stm32-exti.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics 2017-2024
   5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/irqchip.h>
  13 #include <linux/irqchip/chained_irq.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17
  18 #define IRQS_PER_BANK                   32
  19
  20 struct stm32_exti_bank {
  21         u32 imr_ofst;
  22         u32 emr_ofst;
  23         u32 rtsr_ofst;
  24         u32 ftsr_ofst;
  25         u32 swier_ofst;
  26         u32 rpr_ofst;
  27 };
  28
  29 struct stm32_exti_drv_data {
  30         const struct stm32_exti_bank **exti_banks;
  31         const u8 *desc_irqs;
  32         u32 bank_nr;
  33 };
  34
  35 struct stm32_exti_chip_data {
  36         struct stm32_exti_host_data *host_data;
  37         const struct stm32_exti_bank *reg_bank;
  38         u32 wake_active;
  39         u32 mask_cache;
  40         u32 rtsr_cache;
  41         u32 ftsr_cache;
  42         u32 event_reserved;
  43 };
  44
  45 struct stm32_exti_host_data {
  46         void __iomem *base;
  47         struct device *dev;
  48         struct stm32_exti_chip_data *chips_data;
  49         const struct stm32_exti_drv_data *drv_data;
  50 };
  51
  52 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
  53         .imr_ofst       = 0x00,
  54         .emr_ofst       = 0x04,
  55         .rtsr_ofst      = 0x08,
  56         .ftsr_ofst      = 0x0C,
  57         .swier_ofst     = 0x10,
  58         .rpr_ofst       = 0x14,
  59 };
  60
  61 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
  62         &stm32f4xx_exti_b1,
  63 };
  64
  65 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
  66         .exti_banks = stm32f4xx_exti_banks,
  67         .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
  68 };
  69
  70 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
  71         .imr_ofst       = 0x80,
  72         .emr_ofst       = 0x84,
  73         .rtsr_ofst      = 0x00,
  74         .ftsr_ofst      = 0x04,
  75         .swier_ofst     = 0x08,
  76         .rpr_ofst       = 0x88,
  77 };
  78
  79 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
  80         .imr_ofst       = 0x90,
  81         .emr_ofst       = 0x94,
  82         .rtsr_ofst      = 0x20,
  83         .ftsr_ofst      = 0x24,
  84         .swier_ofst     = 0x28,
  85         .rpr_ofst       = 0x98,
  86 };
  87
  88 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
  89         .imr_ofst       = 0xA0,
  90         .emr_ofst       = 0xA4,
  91         .rtsr_ofst      = 0x40,
  92         .ftsr_ofst      = 0x44,
  93         .swier_ofst     = 0x48,
  94         .rpr_ofst       = 0xA8,
  95 };
  96
  97 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
  98         &stm32h7xx_exti_b1,
  99         &stm32h7xx_exti_b2,
 100         &stm32h7xx_exti_b3,
 101 };
 102
 103 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
 104         .exti_banks = stm32h7xx_exti_banks,
 105         .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
 106 };
 107
 108 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
 109 {
 110         struct stm32_exti_chip_data *chip_data = gc->private;
 111         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 112
 113         return irq_reg_readl(gc, stm32_bank->rpr_ofst);
 114 }
 115
 116 static void stm32_irq_handler(struct irq_desc *desc)
 117 {
 118         struct irq_domain *domain = irq_desc_get_handler_data(desc);
 119         struct irq_chip *chip = irq_desc_get_chip(desc);
 120         unsigned int nbanks = domain->gc->num_chips;
 121         struct irq_chip_generic *gc;
 122         unsigned long pending;
 123         int n, i, irq_base = 0;
 124
 125         chained_irq_enter(chip, desc);
 126
 127         for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
 128                 gc = irq_get_domain_generic_chip(domain, irq_base);
 129
 130                 while ((pending = stm32_exti_pending(gc))) {
 131                         for_each_set_bit(n, &pending, IRQS_PER_BANK)
 132                                 generic_handle_domain_irq(domain, irq_base + n);
 133                 }
 134         }
 135
 136         chained_irq_exit(chip, desc);
 137 }
 138
 139 static int stm32_exti_set_type(struct irq_data *d,
 140                                unsigned int type, u32 *rtsr, u32 *ftsr)
 141 {
 142         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 143
 144         switch (type) {
 145         case IRQ_TYPE_EDGE_RISING:
 146                 *rtsr |= mask;
 147                 *ftsr &= ~mask;
 148                 break;
 149         case IRQ_TYPE_EDGE_FALLING:
 150                 *rtsr &= ~mask;
 151                 *ftsr |= mask;
 152                 break;
 153         case IRQ_TYPE_EDGE_BOTH:
 154                 *rtsr |= mask;
 155                 *ftsr |= mask;
 156                 break;
 157         default:
 158                 return -EINVAL;
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
 165 {
 166         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 167         struct stm32_exti_chip_data *chip_data = gc->private;
 168         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 169         u32 rtsr, ftsr;
 170         int err;
 171
 172         irq_gc_lock(gc);
 173
 174         rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
 175         ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
 176
 177         err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
 178         if (err)
 179                 goto unlock;
 180
 181         irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
 182         irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
 183
 184 unlock:
 185         irq_gc_unlock(gc);
 186
 187         return err;
 188 }
 189
 190 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
 191                                u32 wake_active)
 192 {
 193         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 194         void __iomem *base = chip_data->host_data->base;
 195
 196         /* save rtsr, ftsr registers */
 197         chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
 198         chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
 199
 200         writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
 201 }
 202
 203 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
 204                               u32 mask_cache)
 205 {
 206         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 207         void __iomem *base = chip_data->host_data->base;
 208
 209         /* restore rtsr, ftsr, registers */
 210         writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
 211         writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
 212
 213         writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
 214 }
 215
 216 static void stm32_irq_suspend(struct irq_chip_generic *gc)
 217 {
 218         struct stm32_exti_chip_data *chip_data = gc->private;
 219
 220         irq_gc_lock(gc);
 221         stm32_chip_suspend(chip_data, gc->wake_active);
 222         irq_gc_unlock(gc);
 223 }
 224
 225 static void stm32_irq_resume(struct irq_chip_generic *gc)
 226 {
 227         struct stm32_exti_chip_data *chip_data = gc->private;
 228
 229         irq_gc_lock(gc);
 230         stm32_chip_resume(chip_data, gc->mask_cache);
 231         irq_gc_unlock(gc);
 232 }
 233
 234 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
 235                             unsigned int nr_irqs, void *data)
 236 {
 237         struct irq_fwspec *fwspec = data;
 238         irq_hw_number_t hwirq;
 239
 240         hwirq = fwspec->param[0];
 241
 242         irq_map_generic_chip(d, virq, hwirq);
 243
 244         return 0;
 245 }
 246
 247 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
 248                             unsigned int nr_irqs)
 249 {
 250         struct irq_data *data = irq_domain_get_irq_data(d, virq);
 251
 252         irq_domain_reset_irq_data(data);
 253 }
 254
 255 static const struct irq_domain_ops irq_exti_domain_ops = {
 256         .map    = irq_map_generic_chip,
 257         .alloc  = stm32_exti_alloc,
 258         .free   = stm32_exti_free,
 259         .xlate  = irq_domain_xlate_twocell,
 260 };
 261
 262 static void stm32_irq_ack(struct irq_data *d)
 263 {
 264         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 265         struct stm32_exti_chip_data *chip_data = gc->private;
 266         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 267
 268         irq_gc_lock(gc);
 269
 270         irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
 271
 272         irq_gc_unlock(gc);
 273 }
 274
 275 static struct
 276 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
 277                                            struct device_node *node)
 278 {
 279         struct stm32_exti_host_data *host_data;
 280
 281         host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
 282         if (!host_data)
 283                 return NULL;
 284
 285         host_data->drv_data = dd;
 286         host_data->chips_data = kcalloc(dd->bank_nr,
 287                                         sizeof(struct stm32_exti_chip_data),
 288                                         GFP_KERNEL);
 289         if (!host_data->chips_data)
 290                 goto free_host_data;
 291
 292         host_data->base = of_iomap(node, 0);
 293         if (!host_data->base) {
 294                 pr_err("%pOF: Unable to map registers\n", node);
 295                 goto free_chips_data;
 296         }
 297
 298         return host_data;
 299
 300 free_chips_data:
 301         kfree(host_data->chips_data);
 302 free_host_data:
 303         kfree(host_data);
 304
 305         return NULL;
 306 }
 307
 308 static struct
 309 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
 310                                            u32 bank_idx,
 311                                            struct device_node *node)
 312 {
 313         const struct stm32_exti_bank *stm32_bank;
 314         struct stm32_exti_chip_data *chip_data;
 315         void __iomem *base = h_data->base;
 316
 317         stm32_bank = h_data->drv_data->exti_banks[bank_idx];
 318         chip_data = &h_data->chips_data[bank_idx];
 319         chip_data->host_data = h_data;
 320         chip_data->reg_bank = stm32_bank;
 321
 322         /*
 323          * This IP has no reset, so after hot reboot we should
 324          * clear registers to avoid residue
 325          */
 326         writel_relaxed(0, base + stm32_bank->imr_ofst);
 327         writel_relaxed(0, base + stm32_bank->emr_ofst);
 328
 329         pr_info("%pOF: bank%d\n", node, bank_idx);
 330
 331         return chip_data;
 332 }
 333
 334 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 335                                   struct device_node *node)
 336 {
 337         struct stm32_exti_host_data *host_data;
 338         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 339         int nr_irqs, ret, i;
 340         struct irq_chip_generic *gc;
 341         struct irq_domain *domain;
 342
 343         host_data = stm32_exti_host_init(drv_data, node);
 344         if (!host_data)
 345                 return -ENOMEM;
 346
 347         domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
 348                                        &irq_exti_domain_ops, NULL);
 349         if (!domain) {
 350                 pr_err("%pOFn: Could not register interrupt domain.\n",
 351                        node);
 352                 ret = -ENOMEM;
 353                 goto out_unmap;
 354         }
 355
 356         ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
 357                                              handle_edge_irq, clr, 0, 0);
 358         if (ret) {
 359                 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
 360                        node);
 361                 goto out_free_domain;
 362         }
 363
 364         for (i = 0; i < drv_data->bank_nr; i++) {
 365                 const struct stm32_exti_bank *stm32_bank;
 366                 struct stm32_exti_chip_data *chip_data;
 367
 368                 stm32_bank = drv_data->exti_banks[i];
 369                 chip_data = stm32_exti_chip_init(host_data, i, node);
 370
 371                 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
 372
 373                 gc->reg_base = host_data->base;
 374                 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
 375                 gc->chip_types->chip.irq_ack = stm32_irq_ack;
 376                 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
 377                 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
 378                 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
 379                 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
 380                 gc->suspend = stm32_irq_suspend;
 381                 gc->resume = stm32_irq_resume;
 382                 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
 383
 384                 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
 385                 gc->private = (void *)chip_data;
 386         }
 387
 388         nr_irqs = of_irq_count(node);
 389         for (i = 0; i < nr_irqs; i++) {
 390                 unsigned int irq = irq_of_parse_and_map(node, i);
 391
 392                 irq_set_handler_data(irq, domain);
 393                 irq_set_chained_handler(irq, stm32_irq_handler);
 394         }
 395
 396         return 0;
 397
 398 out_free_domain:
 399         irq_domain_remove(domain);
 400 out_unmap:
 401         iounmap(host_data->base);
 402         kfree(host_data->chips_data);
 403         kfree(host_data);
 404         return ret;
 405 }
 406
 407 static int __init stm32f4_exti_of_init(struct device_node *np,
 408                                        struct device_node *parent)
 409 {
 410         return stm32_exti_init(&stm32f4xx_drv_data, np);
 411 }
 412
 413 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
 414
 415 static int __init stm32h7_exti_of_init(struct device_node *np,
 416                                        struct device_node *parent)
 417 {
 418         return stm32_exti_init(&stm32h7xx_drv_data, np);
 419 }
 420
 421 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);